ia64/xen-unstable

view old/xenolinux-2.4.16-sparse/include/asm-xeno/pgtable.h @ 235:d7d0a23b2e07

bitkeeper revision 1.93 (3e5a4e6bkPheUp3x1uufN2MS3LAB7A)

Latest and Greatest version of XenoLinux based on the Linux-2.4.21-pre4
kernel.
author iap10@labyrinth.cl.cam.ac.uk
date Mon Feb 24 16:55:07 2003 +0000 (2003-02-24)
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1 #ifndef _I386_PGTABLE_H
2 #define _I386_PGTABLE_H
4 #include <linux/config.h>
6 #define HAVE_ARCH_UNMAPPED_AREA
8 /*
9 * The Linux memory management assumes a three-level page table setup. On
10 * the i386, we use that, but "fold" the mid level into the top-level page
11 * table, so that we physically have the same two-level page table as the
12 * i386 mmu expects.
13 *
14 * This file contains the functions and defines necessary to modify and use
15 * the i386 page table tree.
16 */
17 #ifndef __ASSEMBLY__
18 #include <asm/processor.h>
19 #include <asm/hypervisor.h>
20 #include <linux/threads.h>
21 #include <asm/fixmap.h>
23 #ifndef _I386_BITOPS_H
24 #include <asm/bitops.h>
25 #endif
27 #define swapper_pg_dir 0
28 extern void paging_init(void);
30 /* Caches aren't brain-dead on the intel. */
31 #define flush_cache_all() do { } while (0)
32 #define flush_cache_mm(mm) do { } while (0)
33 #define flush_cache_range(mm, start, end) do { } while (0)
34 #define flush_cache_page(vma, vmaddr) do { } while (0)
35 #define flush_page_to_ram(page) do { } while (0)
36 #define flush_dcache_page(page) do { } while (0)
37 #define flush_icache_range(start, end) do { } while (0)
38 #define flush_icache_page(vma,pg) do { } while (0)
40 extern unsigned long pgkern_mask;
42 #define __flush_tlb() ({ queue_tlb_flush(); XENO_flush_page_update_queue(); })
43 #define __flush_tlb_global() __flush_tlb()
44 #define __flush_tlb_all() __flush_tlb_global()
45 #define __flush_tlb_one(addr) ({ queue_invlpg(addr); XENO_flush_page_update_queue(); })
47 /*
48 * ZERO_PAGE is a global shared page that is always zero: used
49 * for zero-mapped memory areas etc..
50 */
51 extern unsigned long empty_zero_page[1024];
52 #define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
54 #endif /* !__ASSEMBLY__ */
56 /*
57 * The Linux x86 paging architecture is 'compile-time dual-mode', it
58 * implements both the traditional 2-level x86 page tables and the
59 * newer 3-level PAE-mode page tables.
60 */
61 #ifndef __ASSEMBLY__
62 #if CONFIG_X86_PAE
63 # include <asm/pgtable-3level.h>
65 /*
66 * Need to initialise the X86 PAE caches
67 */
68 extern void pgtable_cache_init(void);
70 #else
71 # include <asm/pgtable-2level.h>
73 /*
74 * No page table caches to initialise
75 */
76 #define pgtable_cache_init() do { } while (0)
78 #endif
79 #endif
81 #define PMD_SIZE (1UL << PMD_SHIFT)
82 #define PMD_MASK (~(PMD_SIZE-1))
83 #define PGDIR_SIZE (1UL << PGDIR_SHIFT)
84 #define PGDIR_MASK (~(PGDIR_SIZE-1))
86 #define USER_PTRS_PER_PGD (TASK_SIZE/PGDIR_SIZE)
87 #define FIRST_USER_PGD_NR 0
89 #define USER_PGD_PTRS (PAGE_OFFSET >> PGDIR_SHIFT)
90 #define KERNEL_PGD_PTRS (PTRS_PER_PGD-USER_PGD_PTRS)
92 #define TWOLEVEL_PGDIR_SHIFT 22
93 #define BOOT_USER_PGD_PTRS (__PAGE_OFFSET >> TWOLEVEL_PGDIR_SHIFT)
94 #define BOOT_KERNEL_PGD_PTRS (1024-BOOT_USER_PGD_PTRS)
97 #ifndef __ASSEMBLY__
98 /* 4MB is just a nice "safety zone". Also, we align to a fresh pde. */
99 #define VMALLOC_OFFSET (4*1024*1024)
100 #define VMALLOC_START (((unsigned long) high_memory + 2*VMALLOC_OFFSET-1) & \
101 ~(VMALLOC_OFFSET-1))
102 #define VMALLOC_VMADDR(x) ((unsigned long)(x))
103 #define VMALLOC_END (FIXADDR_START - 2*PAGE_SIZE)
105 #define _PAGE_BIT_PRESENT 0
106 #define _PAGE_BIT_RW 1
107 #define _PAGE_BIT_USER 2
108 #define _PAGE_BIT_PWT 3
109 #define _PAGE_BIT_PCD 4
110 #define _PAGE_BIT_ACCESSED 5
111 #define _PAGE_BIT_DIRTY 6
112 #define _PAGE_BIT_PSE 7 /* 4 MB (or 2MB) page, Pentium+, if present.. */
113 #define _PAGE_BIT_GLOBAL 8 /* Global TLB entry PPro+ */
115 #define _PAGE_PRESENT 0x001
116 #define _PAGE_RW 0x002
117 #define _PAGE_USER 0x004
118 #define _PAGE_PWT 0x008
119 #define _PAGE_PCD 0x010
120 #define _PAGE_ACCESSED 0x020
121 #define _PAGE_DIRTY 0x040
122 #define _PAGE_PSE 0x080 /* 4 MB (or 2MB) page, Pentium+, if present.. */
123 #define _PAGE_GLOBAL 0x100 /* Global TLB entry PPro+ */
125 #define _PAGE_PROTNONE 0x080 /* If not present */
127 #define _PAGE_TABLE (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER | _PAGE_ACCESSED | _PAGE_DIRTY)
128 #define _KERNPG_TABLE (_PAGE_PRESENT | _PAGE_RW | _PAGE_ACCESSED | _PAGE_DIRTY)
129 #define _PAGE_CHG_MASK (PTE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY)
131 #define PAGE_NONE __pgprot(_PAGE_PROTNONE | _PAGE_ACCESSED)
132 #define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_RW | _PAGE_USER | _PAGE_ACCESSED)
133 #define PAGE_COPY __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_ACCESSED)
134 #define PAGE_READONLY __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_ACCESSED)
136 #define __PAGE_KERNEL \
137 (_PAGE_PRESENT | _PAGE_RW | _PAGE_DIRTY | _PAGE_ACCESSED)
138 #define __PAGE_KERNEL_NOCACHE \
139 (_PAGE_PRESENT | _PAGE_RW | _PAGE_DIRTY | _PAGE_PCD | _PAGE_ACCESSED)
140 #define __PAGE_KERNEL_RO \
141 (_PAGE_PRESENT | _PAGE_DIRTY | _PAGE_ACCESSED)
143 #if 0
144 #define MAKE_GLOBAL(x) __pgprot((x) | _PAGE_GLOBAL)
145 #else
146 #define MAKE_GLOBAL(x) __pgprot(x)
147 #endif
149 #define PAGE_KERNEL MAKE_GLOBAL(__PAGE_KERNEL)
150 #define PAGE_KERNEL_RO MAKE_GLOBAL(__PAGE_KERNEL_RO)
151 #define PAGE_KERNEL_NOCACHE MAKE_GLOBAL(__PAGE_KERNEL_NOCACHE)
153 /*
154 * The i386 can't do page protection for execute, and considers that
155 * the same are read. Also, write permissions imply read permissions.
156 * This is the closest we can get..
157 */
158 #define __P000 PAGE_NONE
159 #define __P001 PAGE_READONLY
160 #define __P010 PAGE_COPY
161 #define __P011 PAGE_COPY
162 #define __P100 PAGE_READONLY
163 #define __P101 PAGE_READONLY
164 #define __P110 PAGE_COPY
165 #define __P111 PAGE_COPY
167 #define __S000 PAGE_NONE
168 #define __S001 PAGE_READONLY
169 #define __S010 PAGE_SHARED
170 #define __S011 PAGE_SHARED
171 #define __S100 PAGE_READONLY
172 #define __S101 PAGE_READONLY
173 #define __S110 PAGE_SHARED
174 #define __S111 PAGE_SHARED
176 #define pte_present(x) ((x).pte_low & (_PAGE_PRESENT | _PAGE_PROTNONE))
177 #define pte_clear(xp) queue_l1_entry_update(__pa(xp), 0)
179 #define pmd_none(x) (!(x).pmd)
180 #define pmd_present(x) ((x).pmd & _PAGE_PRESENT)
181 #define pmd_clear(xp) do { set_pmd(xp, __pmd(0)); } while (0)
182 #define pmd_bad(x) (((x).pmd & (~PAGE_MASK & ~_PAGE_USER)) != _KERNPG_TABLE)
184 /*
185 * Permanent address of a page. Obviously must never be
186 * called on a highmem page.
187 */
188 #define page_address(page) ((page)->virtual)
189 #define pages_to_mb(x) ((x) >> (20-PAGE_SHIFT))
191 /*
192 * The following only work if pte_present() is true.
193 * Undefined behaviour if not..
194 */
195 static inline int pte_read(pte_t pte) { return (pte).pte_low & _PAGE_USER; }
196 static inline int pte_exec(pte_t pte) { return (pte).pte_low & _PAGE_USER; }
197 static inline int pte_dirty(pte_t pte) { return (pte).pte_low & _PAGE_DIRTY; }
198 static inline int pte_young(pte_t pte) { return (pte).pte_low & _PAGE_ACCESSED; }
199 static inline int pte_write(pte_t pte) { return (pte).pte_low & _PAGE_RW; }
201 static inline pte_t pte_rdprotect(pte_t pte) { (pte).pte_low &= ~_PAGE_USER; return pte; }
202 static inline pte_t pte_exprotect(pte_t pte) { (pte).pte_low &= ~_PAGE_USER; return pte; }
203 static inline pte_t pte_mkclean(pte_t pte) { (pte).pte_low &= ~_PAGE_DIRTY; return pte; }
204 static inline pte_t pte_mkold(pte_t pte) { (pte).pte_low &= ~_PAGE_ACCESSED; return pte; }
205 static inline pte_t pte_wrprotect(pte_t pte) { (pte).pte_low &= ~_PAGE_RW; return pte; }
206 static inline pte_t pte_mkread(pte_t pte) { (pte).pte_low |= _PAGE_USER; return pte; }
207 static inline pte_t pte_mkexec(pte_t pte) { (pte).pte_low |= _PAGE_USER; return pte; }
208 static inline pte_t pte_mkdirty(pte_t pte) { (pte).pte_low |= _PAGE_DIRTY; return pte; }
209 static inline pte_t pte_mkyoung(pte_t pte) { (pte).pte_low |= _PAGE_ACCESSED; return pte; }
210 static inline pte_t pte_mkwrite(pte_t pte) { (pte).pte_low |= _PAGE_RW; return pte; }
212 static inline int ptep_test_and_clear_dirty(pte_t *ptep)
213 {
214 unsigned long pteval = *(unsigned long *)ptep;
215 int ret = pteval & _PAGE_DIRTY;
216 if ( ret ) queue_l1_entry_update(__pa(ptep), pteval & ~_PAGE_DIRTY);
217 return ret;
218 }
219 static inline int ptep_test_and_clear_young(pte_t *ptep)
220 {
221 unsigned long pteval = *(unsigned long *)ptep;
222 int ret = pteval & _PAGE_ACCESSED;
223 if ( ret ) queue_l1_entry_update(__pa(ptep), pteval & ~_PAGE_ACCESSED);
224 return ret;
225 }
226 static inline void ptep_set_wrprotect(pte_t *ptep)
227 {
228 unsigned long pteval = *(unsigned long *)ptep;
229 if ( (pteval & _PAGE_RW) )
230 queue_l1_entry_update(__pa(ptep), pteval & ~_PAGE_RW);
231 }
232 static inline void ptep_mkdirty(pte_t *ptep)
233 {
234 unsigned long pteval = *(unsigned long *)ptep;
235 if ( !(pteval & _PAGE_DIRTY) )
236 queue_l1_entry_update(__pa(ptep), pteval | _PAGE_DIRTY);
237 }
239 /*
240 * Conversion functions: convert a page and protection to a page entry,
241 * and a page entry and page directory to the page they refer to.
242 */
244 #define mk_pte(page, pgprot) __mk_pte((page) - mem_map, (pgprot))
246 /* This takes a physical page address that is used by the remapping functions */
247 #define mk_pte_phys(physpage, pgprot) __mk_pte((physpage) >> PAGE_SHIFT, pgprot)
249 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
250 {
251 pte.pte_low &= _PAGE_CHG_MASK;
252 pte.pte_low |= pgprot_val(newprot);
253 return pte;
254 }
256 #define page_pte(page) page_pte_prot(page, __pgprot(0))
258 #define pmd_page(pmd) \
259 ((unsigned long) __va(pmd_val(pmd) & PAGE_MASK))
261 /* to find an entry in a page-table-directory. */
262 #define pgd_index(address) ((address >> PGDIR_SHIFT) & (PTRS_PER_PGD-1))
264 #define __pgd_offset(address) pgd_index(address)
266 #define pgd_offset(mm, address) ((mm)->pgd+pgd_index(address))
268 /* to find an entry in a kernel page-table-directory */
269 #define pgd_offset_k(address) pgd_offset(&init_mm, address)
271 #define __pmd_offset(address) \
272 (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1))
274 /* Find an entry in the third-level page table.. */
275 #define __pte_offset(address) \
276 ((address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
277 #define pte_offset(dir, address) ((pte_t *) pmd_page(*(dir)) + \
278 __pte_offset(address))
280 /*
281 * The i386 doesn't have any external MMU info: the kernel page
282 * tables contain all the necessary information.
283 */
284 #define update_mmu_cache(vma,address,pte) do { } while (0)
286 /* Encode and de-code a swap entry */
287 #define SWP_TYPE(x) (((x).val >> 1) & 0x3f)
288 #define SWP_OFFSET(x) ((x).val >> 8)
289 #define SWP_ENTRY(type, offset) ((swp_entry_t) { ((type) << 1) | ((offset) << 8) })
290 #define pte_to_swp_entry(pte) ((swp_entry_t) { (pte).pte_low })
291 #define swp_entry_to_pte(x) ((pte_t) { (x).val })
293 #endif /* !__ASSEMBLY__ */
295 /* Needs to be defined here and not in linux/mm.h, as it is arch dependent */
296 #define PageSkip(page) (0)
297 #define kern_addr_valid(addr) (1)
299 #define io_remap_page_range remap_page_range
301 #endif /* _I386_PGTABLE_H */