ia64/xen-unstable

view xen/include/asm-ia64/xengcc_intrin.h @ 6457:d34925e4144b

Stil more cleanup and moving to 2.6.13 base
author djm@kirby.fc.hp.com
date Thu Sep 01 11:09:27 2005 -0600 (2005-09-01)
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1 #ifndef _ASM_IA64_XENGCC_INTRIN_H
2 #define _ASM_IA64_XENGCC_INTRIN_H
3 /*
4 * Flushrs instruction stream.
5 */
6 #define ia64_flushrs() asm volatile ("flushrs;;":::"memory")
8 #define ia64_loadrs() asm volatile ("loadrs;;":::"memory")
10 #define ia64_get_rsc() \
11 ({ \
12 unsigned long val; \
13 asm volatile ("mov %0=ar.rsc;;" : "=r"(val) :: "memory"); \
14 val; \
15 })
17 #define ia64_set_rsc(val) \
18 asm volatile ("mov ar.rsc=%0;;" :: "r"(val) : "memory")
20 #define ia64_get_bspstore() \
21 ({ \
22 unsigned long val; \
23 asm volatile ("mov %0=ar.bspstore;;" : "=r"(val) :: "memory"); \
24 val; \
25 })
27 #define ia64_set_bspstore(val) \
28 asm volatile ("mov ar.bspstore=%0;;" :: "r"(val) : "memory")
30 #define ia64_get_rnat() \
31 ({ \
32 unsigned long val; \
33 asm volatile ("mov %0=ar.rnat;" : "=r"(val) :: "memory"); \
34 val; \
35 })
37 #define ia64_set_rnat(val) \
38 asm volatile ("mov ar.rnat=%0;;" :: "r"(val) : "memory")
40 #define ia64_ttag(addr) \
41 ({ \
42 __u64 ia64_intri_res; \
43 asm volatile ("ttag %0=%1" : "=r"(ia64_intri_res) : "r" (addr)); \
44 ia64_intri_res; \
45 })
47 #define ia64_get_dcr() \
48 ({ \
49 __u64 result; \
50 asm volatile ("mov %0=cr.dcr" : "=r"(result) : ); \
51 result; \
52 })
54 #define ia64_set_dcr(val) \
55 ({ \
56 asm volatile ("mov cr.dcr=%0" :: "r"(val) ); \
57 })
59 #endif /* _ASM_IA64_XENGCC_INTRIN_H */