ia64/xen-unstable

view xen/include/asm-ia64/linux-xen/asm/spinlock.h @ 6457:d34925e4144b

Stil more cleanup and moving to 2.6.13 base
author djm@kirby.fc.hp.com
date Thu Sep 01 11:09:27 2005 -0600 (2005-09-01)
parents f5c4042212b0
children 54b112b314fe
line source
1 #ifndef _ASM_IA64_SPINLOCK_H
2 #define _ASM_IA64_SPINLOCK_H
4 /*
5 * Copyright (C) 1998-2003 Hewlett-Packard Co
6 * David Mosberger-Tang <davidm@hpl.hp.com>
7 * Copyright (C) 1999 Walt Drummond <drummond@valinux.com>
8 *
9 * This file is used for SMP configurations only.
10 */
12 #include <linux/compiler.h>
13 #include <linux/kernel.h>
15 #include <asm/atomic.h>
16 #include <asm/bitops.h>
17 #include <asm/intrinsics.h>
18 #include <asm/system.h>
20 typedef struct {
21 volatile unsigned int lock;
22 #ifdef CONFIG_PREEMPT
23 unsigned int break_lock;
24 #endif
25 #ifdef XEN
26 unsigned char recurse_cpu;
27 unsigned char recurse_cnt;
28 #endif
29 } spinlock_t;
31 #define SPIN_LOCK_UNLOCKED (spinlock_t) { 0 }
32 #define spin_lock_init(x) ((x)->lock = 0)
34 #ifdef ASM_SUPPORTED
35 /*
36 * Try to get the lock. If we fail to get the lock, make a non-standard call to
37 * ia64_spinlock_contention(). We do not use a normal call because that would force all
38 * callers of spin_lock() to be non-leaf routines. Instead, ia64_spinlock_contention() is
39 * carefully coded to touch only those registers that spin_lock() marks "clobbered".
40 */
42 #define IA64_SPINLOCK_CLOBBERS "ar.ccv", "ar.pfs", "p14", "p15", "r27", "r28", "r29", "r30", "b6", "memory"
44 static inline void
45 _raw_spin_lock_flags (spinlock_t *lock, unsigned long flags)
46 {
47 register volatile unsigned int *ptr asm ("r31") = &lock->lock;
49 #if __GNUC__ < 3 || (__GNUC__ == 3 && __GNUC_MINOR__ < 3)
50 # ifdef CONFIG_ITANIUM
51 /* don't use brl on Itanium... */
52 asm volatile ("{\n\t"
53 " mov ar.ccv = r0\n\t"
54 " mov r28 = ip\n\t"
55 " mov r30 = 1;;\n\t"
56 "}\n\t"
57 "cmpxchg4.acq r30 = [%1], r30, ar.ccv\n\t"
58 "movl r29 = ia64_spinlock_contention_pre3_4;;\n\t"
59 "cmp4.ne p14, p0 = r30, r0\n\t"
60 "mov b6 = r29;;\n\t"
61 "mov r27=%2\n\t"
62 "(p14) br.cond.spnt.many b6"
63 : "=r"(ptr) : "r"(ptr), "r" (flags) : IA64_SPINLOCK_CLOBBERS);
64 # else
65 asm volatile ("{\n\t"
66 " mov ar.ccv = r0\n\t"
67 " mov r28 = ip\n\t"
68 " mov r30 = 1;;\n\t"
69 "}\n\t"
70 "cmpxchg4.acq r30 = [%1], r30, ar.ccv;;\n\t"
71 "cmp4.ne p14, p0 = r30, r0\n\t"
72 "mov r27=%2\n\t"
73 "(p14) brl.cond.spnt.many ia64_spinlock_contention_pre3_4;;"
74 : "=r"(ptr) : "r"(ptr), "r" (flags) : IA64_SPINLOCK_CLOBBERS);
75 # endif /* CONFIG_MCKINLEY */
76 #else
77 # ifdef CONFIG_ITANIUM
78 /* don't use brl on Itanium... */
79 /* mis-declare, so we get the entry-point, not it's function descriptor: */
80 asm volatile ("mov r30 = 1\n\t"
81 "mov r27=%2\n\t"
82 "mov ar.ccv = r0;;\n\t"
83 "cmpxchg4.acq r30 = [%0], r30, ar.ccv\n\t"
84 "movl r29 = ia64_spinlock_contention;;\n\t"
85 "cmp4.ne p14, p0 = r30, r0\n\t"
86 "mov b6 = r29;;\n\t"
87 "(p14) br.call.spnt.many b6 = b6"
88 : "=r"(ptr) : "r"(ptr), "r" (flags) : IA64_SPINLOCK_CLOBBERS);
89 # else
90 asm volatile ("mov r30 = 1\n\t"
91 "mov r27=%2\n\t"
92 "mov ar.ccv = r0;;\n\t"
93 "cmpxchg4.acq r30 = [%0], r30, ar.ccv;;\n\t"
94 "cmp4.ne p14, p0 = r30, r0\n\t"
95 "(p14) brl.call.spnt.many b6=ia64_spinlock_contention;;"
96 : "=r"(ptr) : "r"(ptr), "r" (flags) : IA64_SPINLOCK_CLOBBERS);
97 # endif /* CONFIG_MCKINLEY */
98 #endif
99 }
100 #define _raw_spin_lock(lock) _raw_spin_lock_flags(lock, 0)
101 #else /* !ASM_SUPPORTED */
102 #define _raw_spin_lock_flags(lock, flags) _raw_spin_lock(lock)
103 # define _raw_spin_lock(x) \
104 do { \
105 __u32 *ia64_spinlock_ptr = (__u32 *) (x); \
106 __u64 ia64_spinlock_val; \
107 ia64_spinlock_val = ia64_cmpxchg4_acq(ia64_spinlock_ptr, 1, 0); \
108 if (unlikely(ia64_spinlock_val)) { \
109 do { \
110 while (*ia64_spinlock_ptr) \
111 ia64_barrier(); \
112 ia64_spinlock_val = ia64_cmpxchg4_acq(ia64_spinlock_ptr, 1, 0); \
113 } while (ia64_spinlock_val); \
114 } \
115 } while (0)
116 #endif /* !ASM_SUPPORTED */
118 #define spin_is_locked(x) ((x)->lock != 0)
119 #define _raw_spin_unlock(x) do { barrier(); ((spinlock_t *) x)->lock = 0; } while (0)
120 #define _raw_spin_trylock(x) (cmpxchg_acq(&(x)->lock, 0, 1) == 0)
121 #define spin_unlock_wait(x) do { barrier(); } while ((x)->lock)
123 typedef struct {
124 volatile unsigned int read_counter : 31;
125 volatile unsigned int write_lock : 1;
126 #ifdef CONFIG_PREEMPT
127 unsigned int break_lock;
128 #endif
129 } rwlock_t;
130 #define RW_LOCK_UNLOCKED (rwlock_t) { 0, 0 }
132 #define rwlock_init(x) do { *(x) = RW_LOCK_UNLOCKED; } while(0)
133 #define read_can_lock(rw) (*(volatile int *)(rw) >= 0)
134 #define write_can_lock(rw) (*(volatile int *)(rw) == 0)
136 #define _raw_read_lock(rw) \
137 do { \
138 rwlock_t *__read_lock_ptr = (rw); \
139 \
140 while (unlikely(ia64_fetchadd(1, (int *) __read_lock_ptr, acq) < 0)) { \
141 ia64_fetchadd(-1, (int *) __read_lock_ptr, rel); \
142 while (*(volatile int *)__read_lock_ptr < 0) \
143 cpu_relax(); \
144 } \
145 } while (0)
147 #define _raw_read_unlock(rw) \
148 do { \
149 rwlock_t *__read_lock_ptr = (rw); \
150 ia64_fetchadd(-1, (int *) __read_lock_ptr, rel); \
151 } while (0)
153 #ifdef ASM_SUPPORTED
154 #define _raw_write_lock(rw) \
155 do { \
156 __asm__ __volatile__ ( \
157 "mov ar.ccv = r0\n" \
158 "dep r29 = -1, r0, 31, 1;;\n" \
159 "1:\n" \
160 "ld4 r2 = [%0];;\n" \
161 "cmp4.eq p0,p7 = r0,r2\n" \
162 "(p7) br.cond.spnt.few 1b \n" \
163 "cmpxchg4.acq r2 = [%0], r29, ar.ccv;;\n" \
164 "cmp4.eq p0,p7 = r0, r2\n" \
165 "(p7) br.cond.spnt.few 1b;;\n" \
166 :: "r"(rw) : "ar.ccv", "p7", "r2", "r29", "memory"); \
167 } while(0)
169 #define _raw_write_trylock(rw) \
170 ({ \
171 register long result; \
172 \
173 __asm__ __volatile__ ( \
174 "mov ar.ccv = r0\n" \
175 "dep r29 = -1, r0, 31, 1;;\n" \
176 "cmpxchg4.acq %0 = [%1], r29, ar.ccv\n" \
177 : "=r"(result) : "r"(rw) : "ar.ccv", "r29", "memory"); \
178 (result == 0); \
179 })
181 #else /* !ASM_SUPPORTED */
183 #define _raw_write_lock(l) \
184 ({ \
185 __u64 ia64_val, ia64_set_val = ia64_dep_mi(-1, 0, 31, 1); \
186 __u32 *ia64_write_lock_ptr = (__u32 *) (l); \
187 do { \
188 while (*ia64_write_lock_ptr) \
189 ia64_barrier(); \
190 ia64_val = ia64_cmpxchg4_acq(ia64_write_lock_ptr, ia64_set_val, 0); \
191 } while (ia64_val); \
192 })
194 #define _raw_write_trylock(rw) \
195 ({ \
196 __u64 ia64_val; \
197 __u64 ia64_set_val = ia64_dep_mi(-1, 0, 31,1); \
198 ia64_val = ia64_cmpxchg4_acq((__u32 *)(rw), ia64_set_val, 0); \
199 (ia64_val == 0); \
200 })
202 #endif /* !ASM_SUPPORTED */
204 #define _raw_read_trylock(lock) generic_raw_read_trylock(lock)
206 #define _raw_write_unlock(x) \
207 ({ \
208 smp_mb__before_clear_bit(); /* need barrier before releasing lock... */ \
209 clear_bit(31, (x)); \
210 })
212 #ifdef XEN
213 #include <asm/xenspinlock.h>
214 #endif
215 #endif /* _ASM_IA64_SPINLOCK_H */