ia64/xen-unstable

view xen/include/asm-ia64/linux-xen/asm/mca_asm.h @ 6457:d34925e4144b

Stil more cleanup and moving to 2.6.13 base
author djm@kirby.fc.hp.com
date Thu Sep 01 11:09:27 2005 -0600 (2005-09-01)
parents 9312a3e8a6f8
children b2f4823b6ff0
line source
1 /*
2 * File: mca_asm.h
3 *
4 * Copyright (C) 1999 Silicon Graphics, Inc.
5 * Copyright (C) Vijay Chander (vijay@engr.sgi.com)
6 * Copyright (C) Srinivasa Thirumalachar <sprasad@engr.sgi.com>
7 * Copyright (C) 2000 Hewlett-Packard Co.
8 * Copyright (C) 2000 David Mosberger-Tang <davidm@hpl.hp.com>
9 * Copyright (C) 2002 Intel Corp.
10 * Copyright (C) 2002 Jenna Hall <jenna.s.hall@intel.com>
11 */
12 #ifndef _ASM_IA64_MCA_ASM_H
13 #define _ASM_IA64_MCA_ASM_H
15 #define PSR_IC 13
16 #define PSR_I 14
17 #define PSR_DT 17
18 #define PSR_RT 27
19 #define PSR_MC 35
20 #define PSR_IT 36
21 #define PSR_BN 44
23 /*
24 * This macro converts a instruction virtual address to a physical address
25 * Right now for simulation purposes the virtual addresses are
26 * direct mapped to physical addresses.
27 * 1. Lop off bits 61 thru 63 in the virtual address
28 */
29 #ifdef XEN
30 #define INST_VA_TO_PA(addr) \
31 dep addr = 0, addr, 60, 4
32 #else
33 #define INST_VA_TO_PA(addr) \
34 dep addr = 0, addr, 61, 3
35 #endif
36 /*
37 * This macro converts a data virtual address to a physical address
38 * Right now for simulation purposes the virtual addresses are
39 * direct mapped to physical addresses.
40 * 1. Lop off bits 61 thru 63 in the virtual address
41 */
42 #define DATA_VA_TO_PA(addr) \
43 tpa addr = addr
44 /*
45 * This macro converts a data physical address to a virtual address
46 * Right now for simulation purposes the virtual addresses are
47 * direct mapped to physical addresses.
48 * 1. Put 0x7 in bits 61 thru 63.
49 */
50 #ifdef XEN
51 #define DATA_PA_TO_VA(addr,temp) \
52 mov temp = 0xf ;; \
53 dep addr = temp, addr, 60, 4
54 #else
55 #define DATA_PA_TO_VA(addr,temp) \
56 mov temp = 0x7 ;; \
57 dep addr = temp, addr, 61, 3
58 #endif
60 #ifdef XEN
61 //FIXME LATER
62 #else
63 #define GET_THIS_PADDR(reg, var) \
64 mov reg = IA64_KR(PER_CPU_DATA);; \
65 addl reg = THIS_CPU(var), reg
66 #endif
68 /*
69 * This macro jumps to the instruction at the given virtual address
70 * and starts execution in physical mode with all the address
71 * translations turned off.
72 * 1. Save the current psr
73 * 2. Make sure that all the upper 32 bits are off
74 *
75 * 3. Clear the interrupt enable and interrupt state collection bits
76 * in the psr before updating the ipsr and iip.
77 *
78 * 4. Turn off the instruction, data and rse translation bits of the psr
79 * and store the new value into ipsr
80 * Also make sure that the interrupts are disabled.
81 * Ensure that we are in little endian mode.
82 * [psr.{rt, it, dt, i, be} = 0]
83 *
84 * 5. Get the physical address corresponding to the virtual address
85 * of the next instruction bundle and put it in iip.
86 * (Using magic numbers 24 and 40 in the deposint instruction since
87 * the IA64_SDK code directly maps to lower 24bits as physical address
88 * from a virtual address).
89 *
90 * 6. Do an rfi to move the values from ipsr to psr and iip to ip.
91 */
92 #define PHYSICAL_MODE_ENTER(temp1, temp2, start_addr, old_psr) \
93 mov old_psr = psr; \
94 ;; \
95 dep old_psr = 0, old_psr, 32, 32; \
96 \
97 mov ar.rsc = 0 ; \
98 ;; \
99 srlz.d; \
100 mov temp2 = ar.bspstore; \
101 ;; \
102 DATA_VA_TO_PA(temp2); \
103 ;; \
104 mov temp1 = ar.rnat; \
105 ;; \
106 mov ar.bspstore = temp2; \
107 ;; \
108 mov ar.rnat = temp1; \
109 mov temp1 = psr; \
110 mov temp2 = psr; \
111 ;; \
112 \
113 dep temp2 = 0, temp2, PSR_IC, 2; \
114 ;; \
115 mov psr.l = temp2; \
116 ;; \
117 srlz.d; \
118 dep temp1 = 0, temp1, 32, 32; \
119 ;; \
120 dep temp1 = 0, temp1, PSR_IT, 1; \
121 ;; \
122 dep temp1 = 0, temp1, PSR_DT, 1; \
123 ;; \
124 dep temp1 = 0, temp1, PSR_RT, 1; \
125 ;; \
126 dep temp1 = 0, temp1, PSR_I, 1; \
127 ;; \
128 dep temp1 = 0, temp1, PSR_IC, 1; \
129 ;; \
130 dep temp1 = -1, temp1, PSR_MC, 1; \
131 ;; \
132 mov cr.ipsr = temp1; \
133 ;; \
134 LOAD_PHYSICAL(p0, temp2, start_addr); \
135 ;; \
136 mov cr.iip = temp2; \
137 mov cr.ifs = r0; \
138 DATA_VA_TO_PA(sp); \
139 DATA_VA_TO_PA(gp); \
140 ;; \
141 srlz.i; \
142 ;; \
143 nop 1; \
144 nop 2; \
145 nop 1; \
146 nop 2; \
147 rfi; \
148 ;;
150 /*
151 * This macro jumps to the instruction at the given virtual address
152 * and starts execution in virtual mode with all the address
153 * translations turned on.
154 * 1. Get the old saved psr
155 *
156 * 2. Clear the interrupt state collection bit in the current psr.
157 *
158 * 3. Set the instruction translation bit back in the old psr
159 * Note we have to do this since we are right now saving only the
160 * lower 32-bits of old psr.(Also the old psr has the data and
161 * rse translation bits on)
162 *
163 * 4. Set ipsr to this old_psr with "it" bit set and "bn" = 1.
164 *
165 * 5. Reset the current thread pointer (r13).
166 *
167 * 6. Set iip to the virtual address of the next instruction bundle.
168 *
169 * 7. Do an rfi to move ipsr to psr and iip to ip.
170 */
172 #define VIRTUAL_MODE_ENTER(temp1, temp2, start_addr, old_psr) \
173 mov temp2 = psr; \
174 ;; \
175 mov old_psr = temp2; \
176 ;; \
177 dep temp2 = 0, temp2, PSR_IC, 2; \
178 ;; \
179 mov psr.l = temp2; \
180 mov ar.rsc = 0; \
181 ;; \
182 srlz.d; \
183 mov r13 = ar.k6; \
184 mov temp2 = ar.bspstore; \
185 ;; \
186 DATA_PA_TO_VA(temp2,temp1); \
187 ;; \
188 mov temp1 = ar.rnat; \
189 ;; \
190 mov ar.bspstore = temp2; \
191 ;; \
192 mov ar.rnat = temp1; \
193 ;; \
194 mov temp1 = old_psr; \
195 ;; \
196 mov temp2 = 1; \
197 ;; \
198 dep temp1 = temp2, temp1, PSR_IC, 1; \
199 ;; \
200 dep temp1 = temp2, temp1, PSR_IT, 1; \
201 ;; \
202 dep temp1 = temp2, temp1, PSR_DT, 1; \
203 ;; \
204 dep temp1 = temp2, temp1, PSR_RT, 1; \
205 ;; \
206 dep temp1 = temp2, temp1, PSR_BN, 1; \
207 ;; \
208 \
209 mov cr.ipsr = temp1; \
210 movl temp2 = start_addr; \
211 ;; \
212 mov cr.iip = temp2; \
213 ;; \
214 DATA_PA_TO_VA(sp, temp1); \
215 DATA_PA_TO_VA(gp, temp2); \
216 srlz.i; \
217 ;; \
218 nop 1; \
219 nop 2; \
220 nop 1; \
221 rfi \
222 ;;
224 /*
225 * The following offsets capture the order in which the
226 * RSE related registers from the old context are
227 * saved onto the new stack frame.
228 *
229 * +-----------------------+
230 * |NDIRTY [BSP - BSPSTORE]|
231 * +-----------------------+
232 * | RNAT |
233 * +-----------------------+
234 * | BSPSTORE |
235 * +-----------------------+
236 * | IFS |
237 * +-----------------------+
238 * | PFS |
239 * +-----------------------+
240 * | RSC |
241 * +-----------------------+ <-------- Bottom of new stack frame
242 */
243 #define rse_rsc_offset 0
244 #define rse_pfs_offset (rse_rsc_offset+0x08)
245 #define rse_ifs_offset (rse_pfs_offset+0x08)
246 #define rse_bspstore_offset (rse_ifs_offset+0x08)
247 #define rse_rnat_offset (rse_bspstore_offset+0x08)
248 #define rse_ndirty_offset (rse_rnat_offset+0x08)
250 /*
251 * rse_switch_context
252 *
253 * 1. Save old RSC onto the new stack frame
254 * 2. Save PFS onto new stack frame
255 * 3. Cover the old frame and start a new frame.
256 * 4. Save IFS onto new stack frame
257 * 5. Save the old BSPSTORE on the new stack frame
258 * 6. Save the old RNAT on the new stack frame
259 * 7. Write BSPSTORE with the new backing store pointer
260 * 8. Read and save the new BSP to calculate the #dirty registers
261 * NOTE: Look at pages 11-10, 11-11 in PRM Vol 2
262 */
263 #define rse_switch_context(temp,p_stackframe,p_bspstore) \
264 ;; \
265 mov temp=ar.rsc;; \
266 st8 [p_stackframe]=temp,8;; \
267 mov temp=ar.pfs;; \
268 st8 [p_stackframe]=temp,8; \
269 cover ;; \
270 mov temp=cr.ifs;; \
271 st8 [p_stackframe]=temp,8;; \
272 mov temp=ar.bspstore;; \
273 st8 [p_stackframe]=temp,8;; \
274 mov temp=ar.rnat;; \
275 st8 [p_stackframe]=temp,8; \
276 mov ar.bspstore=p_bspstore;; \
277 mov temp=ar.bsp;; \
278 sub temp=temp,p_bspstore;; \
279 st8 [p_stackframe]=temp,8;;
281 /*
282 * rse_return_context
283 * 1. Allocate a zero-sized frame
284 * 2. Store the number of dirty registers RSC.loadrs field
285 * 3. Issue a loadrs to insure that any registers from the interrupted
286 * context which were saved on the new stack frame have been loaded
287 * back into the stacked registers
288 * 4. Restore BSPSTORE
289 * 5. Restore RNAT
290 * 6. Restore PFS
291 * 7. Restore IFS
292 * 8. Restore RSC
293 * 9. Issue an RFI
294 */
295 #define rse_return_context(psr_mask_reg,temp,p_stackframe) \
296 ;; \
297 alloc temp=ar.pfs,0,0,0,0; \
298 add p_stackframe=rse_ndirty_offset,p_stackframe;; \
299 ld8 temp=[p_stackframe];; \
300 shl temp=temp,16;; \
301 mov ar.rsc=temp;; \
302 loadrs;; \
303 add p_stackframe=-rse_ndirty_offset+rse_bspstore_offset,p_stackframe;;\
304 ld8 temp=[p_stackframe];; \
305 mov ar.bspstore=temp;; \
306 add p_stackframe=-rse_bspstore_offset+rse_rnat_offset,p_stackframe;;\
307 ld8 temp=[p_stackframe];; \
308 mov ar.rnat=temp;; \
309 add p_stackframe=-rse_rnat_offset+rse_pfs_offset,p_stackframe;; \
310 ld8 temp=[p_stackframe];; \
311 mov ar.pfs=temp;; \
312 add p_stackframe=-rse_pfs_offset+rse_ifs_offset,p_stackframe;; \
313 ld8 temp=[p_stackframe];; \
314 mov cr.ifs=temp;; \
315 add p_stackframe=-rse_ifs_offset+rse_rsc_offset,p_stackframe;; \
316 ld8 temp=[p_stackframe];; \
317 mov ar.rsc=temp ; \
318 mov temp=psr;; \
319 or temp=temp,psr_mask_reg;; \
320 mov cr.ipsr=temp;; \
321 mov temp=ip;; \
322 add temp=0x30,temp;; \
323 mov cr.iip=temp;; \
324 srlz.i;; \
325 rfi;;
327 #endif /* _ASM_IA64_MCA_ASM_H */