ia64/xen-unstable

view xen/include/asm-x86/hvm/vmx/vmcs.h @ 11153:d20e1835c24b

Various HVM clean-ups.

Signed-off-by: Steven Hand <steven@xensource.com>
author shand@kneesaa.uk.xensource.com
date Tue Aug 15 18:20:03 2006 +0100 (2006-08-15)
parents 022f29d4d2b8
children 88e6bd5e2b54
line source
1 /*
2 * vmcs.h: VMCS related definitions
3 * Copyright (c) 2004, Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
16 * Place - Suite 330, Boston, MA 02111-1307 USA.
17 *
18 */
19 #ifndef __ASM_X86_HVM_VMX_VMCS_H__
20 #define __ASM_X86_HVM_VMX_VMCS_H__
22 #include <asm/config.h>
23 #include <asm/hvm/io.h>
24 #include <asm/hvm/vmx/cpu.h>
25 #include <public/hvm/vmx_assist.h>
27 extern int start_vmx(void);
28 extern void vmcs_dump_vcpu(void);
29 extern void vmx_init_vmcs_config(void);
30 extern void setup_vmcs_dump(void);
32 enum {
33 VMX_CPU_STATE_PAE_ENABLED=0,
34 VMX_CPU_STATE_LME_ENABLED,
35 VMX_CPU_STATE_LMA_ENABLED,
36 VMX_CPU_STATE_ASSIST_ENABLED,
37 };
39 #define VMX_LONG_GUEST(ed) \
40 (test_bit(VMX_CPU_STATE_LMA_ENABLED, &ed->arch.hvm_vmx.cpu_state))
42 struct vmcs_struct {
43 u32 vmcs_revision_id;
44 unsigned char data [0]; /* vmcs size is read from MSR */
45 };
47 enum {
48 VMX_INDEX_MSR_LSTAR = 0,
49 VMX_INDEX_MSR_STAR,
50 VMX_INDEX_MSR_CSTAR,
51 VMX_INDEX_MSR_SYSCALL_MASK,
52 VMX_INDEX_MSR_EFER,
54 VMX_MSR_COUNT,
55 };
57 struct vmx_msr_state {
58 unsigned long flags;
59 unsigned long msr_items[VMX_MSR_COUNT];
60 unsigned long shadow_gs;
61 };
63 /* io bitmap is 4KBytes in size */
64 #define IO_BITMAP_SIZE 0x1000
65 #define IO_BITMAP_ORDER (get_order_from_bytes(IO_BITMAP_SIZE))
67 struct arch_vmx_struct {
68 /* Virtual address of VMCS. */
69 struct vmcs_struct *vmcs;
71 /* Protects remote usage of VMCS (VMPTRLD/VMCLEAR). */
72 spinlock_t vmcs_lock;
74 /*
75 * Activation and launch status of this VMCS.
76 * - Activated on a CPU by VMPTRLD. Deactivated by VMCLEAR.
77 * - Launched on active CPU by VMLAUNCH when current VMCS.
78 */
79 int active_cpu;
80 int launched;
82 /* Cache of cpu execution control. */
83 u32 exec_control;
85 /* If there is vector installed in the INTR_INFO_FIELD. */
86 u32 vector_injected;
88 unsigned long cpu_cr0; /* copy of guest CR0 */
89 unsigned long cpu_shadow_cr0; /* copy of guest read shadow CR0 */
90 unsigned long cpu_cr2; /* save CR2 */
91 unsigned long cpu_cr3;
92 unsigned long cpu_state;
93 unsigned long cpu_based_exec_control;
94 struct vmx_msr_state msr_content;
95 void *io_bitmap_a, *io_bitmap_b;
96 struct timer hlt_timer; /* hlt ins emulation wakeup timer */
97 };
99 #define vmx_schedule_tail(next) \
100 (next)->thread.arch_vmx.arch_vmx_schedule_tail((next))
102 void vmx_do_resume(struct vcpu *);
104 struct vmcs_struct *vmx_alloc_host_vmcs(void);
105 void vmx_free_host_vmcs(struct vmcs_struct *vmcs);
107 int vmx_create_vmcs(struct vcpu *v);
108 void vmx_destroy_vmcs(struct vcpu *v);
109 void vmx_vmcs_enter(struct vcpu *v);
110 void vmx_vmcs_exit(struct vcpu *v);
112 #define VMCS_USE_HOST_ENV 1
113 #define VMCS_USE_SEPARATE_ENV 0
115 extern int vmcs_version;
117 #define CPU_BASED_VIRTUAL_INTR_PENDING 0x00000004
118 #define CPU_BASED_USE_TSC_OFFSETING 0x00000008
119 #define CPU_BASED_HLT_EXITING 0x00000080
120 #define CPU_BASED_INVDPG_EXITING 0x00000200
121 #define CPU_BASED_MWAIT_EXITING 0x00000400
122 #define CPU_BASED_RDPMC_EXITING 0x00000800
123 #define CPU_BASED_RDTSC_EXITING 0x00001000
124 #define CPU_BASED_CR8_LOAD_EXITING 0x00080000
125 #define CPU_BASED_CR8_STORE_EXITING 0x00100000
126 #define CPU_BASED_TPR_SHADOW 0x00200000
127 #define CPU_BASED_MOV_DR_EXITING 0x00800000
128 #define CPU_BASED_UNCOND_IO_EXITING 0x01000000
129 #define CPU_BASED_ACTIVATE_IO_BITMAP 0x02000000
130 #define CPU_BASED_MONITOR_EXITING 0x20000000
131 #define CPU_BASED_PAUSE_EXITING 0x40000000
132 #define PIN_BASED_EXT_INTR_MASK 0x1
133 #define PIN_BASED_NMI_EXITING 0x8
135 #define VM_EXIT_ACK_INTR_ON_EXIT 0x00008000
136 #define VM_EXIT_HOST_ADD_SPACE_SIZE 0x00000200
139 /* VMCS Encordings */
140 enum vmcs_field {
141 GUEST_ES_SELECTOR = 0x00000800,
142 GUEST_CS_SELECTOR = 0x00000802,
143 GUEST_SS_SELECTOR = 0x00000804,
144 GUEST_DS_SELECTOR = 0x00000806,
145 GUEST_FS_SELECTOR = 0x00000808,
146 GUEST_GS_SELECTOR = 0x0000080a,
147 GUEST_LDTR_SELECTOR = 0x0000080c,
148 GUEST_TR_SELECTOR = 0x0000080e,
149 HOST_ES_SELECTOR = 0x00000c00,
150 HOST_CS_SELECTOR = 0x00000c02,
151 HOST_SS_SELECTOR = 0x00000c04,
152 HOST_DS_SELECTOR = 0x00000c06,
153 HOST_FS_SELECTOR = 0x00000c08,
154 HOST_GS_SELECTOR = 0x00000c0a,
155 HOST_TR_SELECTOR = 0x00000c0c,
156 IO_BITMAP_A = 0x00002000,
157 IO_BITMAP_A_HIGH = 0x00002001,
158 IO_BITMAP_B = 0x00002002,
159 IO_BITMAP_B_HIGH = 0x00002003,
160 VM_EXIT_MSR_STORE_ADDR = 0x00002006,
161 VM_EXIT_MSR_STORE_ADDR_HIGH = 0x00002007,
162 VM_EXIT_MSR_LOAD_ADDR = 0x00002008,
163 VM_EXIT_MSR_LOAD_ADDR_HIGH = 0x00002009,
164 VM_ENTRY_MSR_LOAD_ADDR = 0x0000200a,
165 VM_ENTRY_MSR_LOAD_ADDR_HIGH = 0x0000200b,
166 TSC_OFFSET = 0x00002010,
167 TSC_OFFSET_HIGH = 0x00002011,
168 VIRTUAL_APIC_PAGE_ADDR = 0x00002012,
169 VIRTUAL_APIC_PAGE_ADDR_HIGH = 0x00002013,
170 VMCS_LINK_POINTER = 0x00002800,
171 VMCS_LINK_POINTER_HIGH = 0x00002801,
172 GUEST_IA32_DEBUGCTL = 0x00002802,
173 GUEST_IA32_DEBUGCTL_HIGH = 0x00002803,
174 PIN_BASED_VM_EXEC_CONTROL = 0x00004000,
175 CPU_BASED_VM_EXEC_CONTROL = 0x00004002,
176 EXCEPTION_BITMAP = 0x00004004,
177 PAGE_FAULT_ERROR_CODE_MASK = 0x00004006,
178 PAGE_FAULT_ERROR_CODE_MATCH = 0x00004008,
179 CR3_TARGET_COUNT = 0x0000400a,
180 VM_EXIT_CONTROLS = 0x0000400c,
181 VM_EXIT_MSR_STORE_COUNT = 0x0000400e,
182 VM_EXIT_MSR_LOAD_COUNT = 0x00004010,
183 VM_ENTRY_CONTROLS = 0x00004012,
184 VM_ENTRY_MSR_LOAD_COUNT = 0x00004014,
185 VM_ENTRY_INTR_INFO_FIELD = 0x00004016,
186 VM_ENTRY_EXCEPTION_ERROR_CODE = 0x00004018,
187 VM_ENTRY_INSTRUCTION_LEN = 0x0000401a,
188 TPR_THRESHOLD = 0x0000401c,
189 SECONDARY_VM_EXEC_CONTROL = 0x0000401e,
190 VM_INSTRUCTION_ERROR = 0x00004400,
191 VM_EXIT_REASON = 0x00004402,
192 VM_EXIT_INTR_INFO = 0x00004404,
193 VM_EXIT_INTR_ERROR_CODE = 0x00004406,
194 IDT_VECTORING_INFO_FIELD = 0x00004408,
195 IDT_VECTORING_ERROR_CODE = 0x0000440a,
196 VM_EXIT_INSTRUCTION_LEN = 0x0000440c,
197 VMX_INSTRUCTION_INFO = 0x0000440e,
198 GUEST_ES_LIMIT = 0x00004800,
199 GUEST_CS_LIMIT = 0x00004802,
200 GUEST_SS_LIMIT = 0x00004804,
201 GUEST_DS_LIMIT = 0x00004806,
202 GUEST_FS_LIMIT = 0x00004808,
203 GUEST_GS_LIMIT = 0x0000480a,
204 GUEST_LDTR_LIMIT = 0x0000480c,
205 GUEST_TR_LIMIT = 0x0000480e,
206 GUEST_GDTR_LIMIT = 0x00004810,
207 GUEST_IDTR_LIMIT = 0x00004812,
208 GUEST_ES_AR_BYTES = 0x00004814,
209 GUEST_CS_AR_BYTES = 0x00004816,
210 GUEST_SS_AR_BYTES = 0x00004818,
211 GUEST_DS_AR_BYTES = 0x0000481a,
212 GUEST_FS_AR_BYTES = 0x0000481c,
213 GUEST_GS_AR_BYTES = 0x0000481e,
214 GUEST_LDTR_AR_BYTES = 0x00004820,
215 GUEST_TR_AR_BYTES = 0x00004822,
216 GUEST_INTERRUPTIBILITY_INFO = 0x00004824,
217 GUEST_SYSENTER_CS = 0x0000482A,
218 HOST_IA32_SYSENTER_CS = 0x00004c00,
219 CR0_GUEST_HOST_MASK = 0x00006000,
220 CR4_GUEST_HOST_MASK = 0x00006002,
221 CR0_READ_SHADOW = 0x00006004,
222 CR4_READ_SHADOW = 0x00006006,
223 CR3_TARGET_VALUE0 = 0x00006008,
224 CR3_TARGET_VALUE1 = 0x0000600a,
225 CR3_TARGET_VALUE2 = 0x0000600c,
226 CR3_TARGET_VALUE3 = 0x0000600e,
227 EXIT_QUALIFICATION = 0x00006400,
228 GUEST_LINEAR_ADDRESS = 0x0000640a,
229 GUEST_CR0 = 0x00006800,
230 GUEST_CR3 = 0x00006802,
231 GUEST_CR4 = 0x00006804,
232 GUEST_ES_BASE = 0x00006806,
233 GUEST_CS_BASE = 0x00006808,
234 GUEST_SS_BASE = 0x0000680a,
235 GUEST_DS_BASE = 0x0000680c,
236 GUEST_FS_BASE = 0x0000680e,
237 GUEST_GS_BASE = 0x00006810,
238 GUEST_LDTR_BASE = 0x00006812,
239 GUEST_TR_BASE = 0x00006814,
240 GUEST_GDTR_BASE = 0x00006816,
241 GUEST_IDTR_BASE = 0x00006818,
242 GUEST_DR7 = 0x0000681a,
243 GUEST_RSP = 0x0000681c,
244 GUEST_RIP = 0x0000681e,
245 GUEST_RFLAGS = 0x00006820,
246 GUEST_PENDING_DBG_EXCEPTIONS = 0x00006822,
247 GUEST_SYSENTER_ESP = 0x00006824,
248 GUEST_SYSENTER_EIP = 0x00006826,
249 HOST_CR0 = 0x00006c00,
250 HOST_CR3 = 0x00006c02,
251 HOST_CR4 = 0x00006c04,
252 HOST_FS_BASE = 0x00006c06,
253 HOST_GS_BASE = 0x00006c08,
254 HOST_TR_BASE = 0x00006c0a,
255 HOST_GDTR_BASE = 0x00006c0c,
256 HOST_IDTR_BASE = 0x00006c0e,
257 HOST_IA32_SYSENTER_ESP = 0x00006c10,
258 HOST_IA32_SYSENTER_EIP = 0x00006c12,
259 HOST_RSP = 0x00006c14,
260 HOST_RIP = 0x00006c16,
261 };
263 #endif /* ASM_X86_HVM_VMX_VMCS_H__ */
265 /*
266 * Local variables:
267 * mode: C
268 * c-set-style: "BSD"
269 * c-basic-offset: 4
270 * tab-width: 4
271 * indent-tabs-mode: nil
272 * End:
273 */