ia64/xen-unstable

view xen/include/asm-x86/hvm/vlapic.h @ 9016:cf1c1bb9f6d2

Bring up AP of VMX domain.
1) add INIT-SIPI-SIPI IPI sequence handling code to HVM virtual lapic
code.
2) add an new interface init_ap_context to hvm_funcs, and implement the
VMX side.
3) add a hvm generic function hvm_bringup_ap, which in turn calls
init_ap_context.

Signed-off-by: Xin Li <xin.b.li@intel.com>
Signed-off-by: Yunhong Jiang <yunhong.jiang@intel.com>
author kaf24@firebug.cl.cam.ac.uk
date Fri Feb 24 17:32:58 2006 +0100 (2006-02-24)
parents f1b361b05bf3
children 503c4d8454e5
line source
1 /*
2 * hvm_vlapic.h: virtualize LAPIC definitions.
3 *
4 * Copyright (c) 2004, Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along with
16 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
17 * Place - Suite 330, Boston, MA 02111-1307 USA.
18 */
20 #ifndef __ASM_X86_HVM_VLAPIC_H__
21 #define __ASM_X86_HVM_VLAPIC_H__
23 #include <asm/msr.h>
24 #include <public/hvm/ioreq.h>
26 #if defined(__i386__) || defined(__x86_64__)
27 static inline int __fls(uint32_t word)
28 {
29 int bit;
31 __asm__("bsrl %1,%0"
32 :"=r" (bit)
33 :"rm" (word));
34 return word ? bit : -1;
35 }
36 #else
37 #define __fls(x) generic_fls(x)
38 static __inline__ int generic_fls(uint32_t x)
39 {
40 int r = 31;
42 if (!x)
43 return -1;
44 if (!(x & 0xffff0000u)) {
45 x <<= 16;
46 r -= 16;
47 }
48 if (!(x & 0xff000000u)) {
49 x <<= 8;
50 r -= 8;
51 }
52 if (!(x & 0xf0000000u)) {
53 x <<= 4;
54 r -= 4;
55 }
56 if (!(x & 0xc0000000u)) {
57 x <<= 2;
58 r -= 2;
59 }
60 if (!(x & 0x80000000u)) {
61 x <<= 1;
62 r -= 1;
63 }
64 return r;
65 }
66 #endif
68 static __inline__ int find_highest_bit(uint32_t *data, int length)
69 {
70 while(length && !data[--length]);
71 return __fls(data[length]) + 32 * length;
72 }
74 #define VLAPIC(v) (v->arch.hvm_vcpu.vlapic)
76 #define VAPIC_ID_MASK 0xff
77 #define VAPIC_LDR_MASK (VAPIC_ID_MASK << 24)
78 #define VLAPIC_VERSION 0x00050014
80 #define VLAPIC_BASE_MSR_MASK 0x00000000fffff900ULL
81 #define VLAPIC_BASE_MSR_INIT_BASE_ADDR 0xfee00000U
82 #define VLAPIC_BASE_MSR_BASE_ADDR_MASK 0xfffff000U
83 #define VLAPIC_BASE_MSR_INIT_VALUE (VLAPIC_BASE_MSR_INIT_BASE_ADDR | \
84 MSR_IA32_APICBASE_ENABLE)
85 #define VLOCAL_APIC_MEM_LENGTH (1 << 12)
87 #define VLAPIC_LVT_TIMER 0
88 #define VLAPIC_LVT_THERMAL 1
89 #define VLAPIC_LVT_PERFORM 2
90 #define VLAPIC_LVT_LINT0 3
91 #define VLAPIC_LVT_LINT1 4
92 #define VLAPIC_LVT_ERROR 5
93 #define VLAPIC_LVT_NUM 6
95 #define VLAPIC_LVT_BIT_MASK (1 << 16)
96 #define VLAPIC_LVT_BIT_VECTOR 0xff
97 #define VLAPIC_LVT_BIT_DELIMOD (0x7 << 8)
98 #define VLAPIC_LVT_BIT_DELISTATUS (1 << 12)
99 #define VLAPIC_LVT_BIT_POLARITY (1 << 13)
100 #define VLAPIC_LVT_BIT_IRR (1 << 14)
101 #define VLAPIC_LVT_BIT_TRIG (1 << 15)
102 #define VLAPIC_LVT_TIMERMODE (1 << 17)
104 #define VLAPIC_DELIV_MODE_FIXED 0x0
105 #define VLAPIC_DELIV_MODE_LPRI 0x1
106 #define VLAPIC_DELIV_MODE_SMI 0x2
107 #define VLAPIC_DELIV_MODE_RESERVED 0x3
108 #define VLAPIC_DELIV_MODE_NMI 0x4
109 #define VLAPIC_DELIV_MODE_INIT 0x5
110 #define VLAPIC_DELIV_MODE_STARTUP 0x6
111 #define VLAPIC_DELIV_MODE_EXT 0x7
115 #define VLAPIC_NO_SHORTHAND 0x0
116 #define VLAPIC_SHORTHAND_SELF 0x1
117 #define VLAPIC_SHORTHAND_INCLUDE_SELF 0x2
118 #define VLAPIC_SHORTHAND_EXCLUDE_SELF 0x3
120 #define vlapic_lvt_timer_enabled(vlapic) \
121 (!(vlapic->lvt[VLAPIC_LVT_TIMER] & VLAPIC_LVT_BIT_MASK))
123 #define vlapic_lvt_vector(vlapic, type) \
124 (vlapic->lvt[type] & VLAPIC_LVT_BIT_VECTOR)
126 #define vlapic_lvt_dm(value) ((value >> 8) && 7)
127 #define vlapic_lvt_timer_period(vlapic) \
128 (vlapic->lvt[VLAPIC_LVT_TIMER] & VLAPIC_LVT_TIMERMODE)
130 #define vlapic_isr_status(vlapic,vector) \
131 test_bit(vector, &vlapic->isr[0])
133 #define vlapic_irr_status(vlapic,vector) \
134 test_bit(vector, &vlapic->irr[0])
136 #define vlapic_set_isr(vlapic,vector) \
137 test_and_set_bit(vector, &vlapic->isr[0])
139 #define vlapic_set_irr(vlapic,vector) \
140 test_and_set_bit(vector, &vlapic->irr[0])
142 #define vlapic_clear_irr(vlapic,vector) \
143 clear_bit(vector, &vlapic->irr[0])
144 #define vlapic_clear_isr(vlapic,vector) \
145 clear_bit(vector, &vlapic->isr[0])
147 #define vlapic_enabled(vlapic) \
148 (!(vlapic->status & \
149 (VLAPIC_GLOB_DISABLE_MASK | VLAPIC_SOFTWARE_DISABLE_MASK)))
151 #define vlapic_global_enabled(vlapic) \
152 !(test_bit(_VLAPIC_GLOB_DISABLE, &(vlapic)->status))
154 #define VLAPIC_IRR(t) ((t)->irr[0])
155 #define VLAPIC_ID(t) ((t)->id)
157 typedef struct direct_intr_info {
158 int deliver_mode;
159 int source[6];
160 } direct_intr_info_t;
162 struct vlapic
163 {
164 //FIXME check what would be 64 bit on EM64T
165 uint32_t version;
166 #define _VLAPIC_GLOB_DISABLE 0x0
167 #define VLAPIC_GLOB_DISABLE_MASK 0x1
168 #define VLAPIC_SOFTWARE_DISABLE_MASK 0x2
169 #define _VLAPIC_BSP_ACCEPT_PIC 0x3
170 uint32_t status;
171 uint32_t id;
172 uint32_t vcpu_id;
173 unsigned long base_address;
174 uint32_t isr[8];
175 uint32_t irr[INTR_LEN_32];
176 uint32_t tmr[INTR_LEN_32];
177 uint32_t task_priority;
178 uint32_t processor_priority;
179 uint32_t logical_dest;
180 uint32_t dest_format;
181 uint32_t spurious_vec;
182 uint32_t lvt[6];
183 uint32_t timer_initial;
184 uint32_t timer_current;
185 uint32_t timer_divconf;
186 uint32_t timer_divide_counter;
187 struct timer vlapic_timer;
188 int intr_pending_count[MAX_VECTOR];
189 s_time_t timer_current_update;
190 uint32_t icr_high;
191 uint32_t icr_low;
192 direct_intr_info_t direct_intr;
193 uint32_t err_status;
194 unsigned long init_ticks;
195 uint32_t err_write_count;
196 uint64_t apic_base_msr;
197 struct vcpu *vcpu;
198 struct domain *domain;
199 };
201 static inline int vlapic_set_irq(struct vlapic *t, uint8_t vec, uint8_t trig)
202 {
203 int ret;
205 ret = test_and_set_bit(vec, &t->irr[0]);
206 if (trig)
207 test_and_set_bit(vec, &t->tmr[0]);
209 /* We may need to wake up target vcpu, besides set pending bit here */
210 return ret;
211 }
213 static inline int vlapic_timer_active(struct vlapic *vlapic)
214 {
215 return active_timer(&(vlapic->vlapic_timer));
216 }
218 int vlapic_find_highest_irr(struct vlapic *vlapic);
220 int vlapic_find_highest_isr(struct vlapic *vlapic);
222 static uint32_t inline vlapic_get_base_address(struct vlapic *vlapic)
223 {
224 return (vlapic->apic_base_msr & VLAPIC_BASE_MSR_BASE_ADDR_MASK);
225 }
227 void vlapic_post_injection(struct vcpu* v, int vector, int deliver_mode);
229 int cpu_get_apic_interrupt(struct vcpu* v, int *mode);
231 extern uint32_t vlapic_update_ppr(struct vlapic *vlapic);
233 int vlapic_update(struct vcpu *v);
235 extern int vlapic_init(struct vcpu *vc);
237 extern void vlapic_msr_set(struct vlapic *vlapic, uint64_t value);
239 int vlapic_accept_pic_intr(struct vcpu *v);
241 struct vlapic* apic_round_robin(struct domain *d,
242 uint8_t dest_mode,
243 uint8_t vector,
244 uint32_t bitmap);
246 s_time_t get_apictime_scheduled(struct vcpu *v);
247 int hvm_apic_support(struct domain *d);
249 #endif /* __ASM_X86_HVM_VLAPIC_H__ */