ia64/xen-unstable

view xen/include/asm-ia64/linux-xen/asm/pgtable.h @ 9770:ced37bea0647

[IA64] FPH enabling + cleanup

Move contents of switch_to macro from xensystem.h to context_switch function.
Initialize FPU on all processors. FPH is always enabled in Xen.
Speed up context-switch (a little bit!) by not enabling/disabling FPH.
Cleanup (unused function/variablesi/fields, debug printf...)
vmx_ia64_switch_to removed (was unused).

Signed-off-by: Tristan Gingold <tristan.gingold@bull.net>
author awilliam@xenbuild.aw
date Tue Apr 25 22:35:41 2006 -0600 (2006-04-25)
parents 1055f276cc4d
children 7296d8fb07ff
line source
1 #ifndef _ASM_IA64_PGTABLE_H
2 #define _ASM_IA64_PGTABLE_H
4 /*
5 * This file contains the functions and defines necessary to modify and use
6 * the IA-64 page table tree.
7 *
8 * This hopefully works with any (fixed) IA-64 page-size, as defined
9 * in <asm/page.h>.
10 *
11 * Copyright (C) 1998-2005 Hewlett-Packard Co
12 * David Mosberger-Tang <davidm@hpl.hp.com>
13 */
15 #include <linux/config.h>
17 #include <asm/mman.h>
18 #include <asm/page.h>
19 #include <asm/processor.h>
20 #include <asm/system.h>
21 #include <asm/types.h>
22 #ifdef XEN
23 #ifndef __ASSEMBLY__
24 #include <xen/sched.h> /* needed for mm_struct (via asm/domain.h) */
25 #endif
26 #endif
28 #define IA64_MAX_PHYS_BITS 50 /* max. number of physical address bits (architected) */
30 /*
31 * First, define the various bits in a PTE. Note that the PTE format
32 * matches the VHPT short format, the firt doubleword of the VHPD long
33 * format, and the first doubleword of the TLB insertion format.
34 */
35 #define _PAGE_P_BIT 0
36 #define _PAGE_A_BIT 5
37 #define _PAGE_D_BIT 6
39 #define _PAGE_P (1 << _PAGE_P_BIT) /* page present bit */
40 #define _PAGE_MA_WB (0x0 << 2) /* write back memory attribute */
41 #define _PAGE_MA_UC (0x4 << 2) /* uncacheable memory attribute */
42 #define _PAGE_MA_UCE (0x5 << 2) /* UC exported attribute */
43 #define _PAGE_MA_WC (0x6 << 2) /* write coalescing memory attribute */
44 #define _PAGE_MA_NAT (0x7 << 2) /* not-a-thing attribute */
45 #define _PAGE_MA_MASK (0x7 << 2)
46 #define _PAGE_PL_0 (0 << 7) /* privilege level 0 (kernel) */
47 #define _PAGE_PL_1 (1 << 7) /* privilege level 1 (unused) */
48 #define _PAGE_PL_2 (2 << 7) /* privilege level 2 (unused) */
49 #define _PAGE_PL_3 (3 << 7) /* privilege level 3 (user) */
50 #define _PAGE_PL_MASK (3 << 7)
51 #define _PAGE_AR_R (0 << 9) /* read only */
52 #define _PAGE_AR_RX (1 << 9) /* read & execute */
53 #define _PAGE_AR_RW (2 << 9) /* read & write */
54 #define _PAGE_AR_RWX (3 << 9) /* read, write & execute */
55 #define _PAGE_AR_R_RW (4 << 9) /* read / read & write */
56 #define _PAGE_AR_RX_RWX (5 << 9) /* read & exec / read, write & exec */
57 #define _PAGE_AR_RWX_RW (6 << 9) /* read, write & exec / read & write */
58 #define _PAGE_AR_X_RX (7 << 9) /* exec & promote / read & exec */
59 #define _PAGE_AR_MASK (7 << 9)
60 #define _PAGE_AR_SHIFT 9
61 #define _PAGE_A (1 << _PAGE_A_BIT) /* page accessed bit */
62 #define _PAGE_D (1 << _PAGE_D_BIT) /* page dirty bit */
63 #define _PAGE_PPN_MASK (((__IA64_UL(1) << IA64_MAX_PHYS_BITS) - 1) & ~0xfffUL)
64 #define _PAGE_ED (__IA64_UL(1) << 52) /* exception deferral */
65 #define _PAGE_PROTNONE (__IA64_UL(1) << 63)
67 /* Valid only for a PTE with the present bit cleared: */
68 #define _PAGE_FILE (1 << 1) /* see swap & file pte remarks below */
70 #define _PFN_MASK _PAGE_PPN_MASK
71 /* Mask of bits which may be changed by pte_modify(); the odd bits are there for _PAGE_PROTNONE */
72 #define _PAGE_CHG_MASK (_PAGE_P | _PAGE_PROTNONE | _PAGE_PL_MASK | _PAGE_AR_MASK | _PAGE_ED)
74 #define _PAGE_SIZE_4K 12
75 #define _PAGE_SIZE_8K 13
76 #define _PAGE_SIZE_16K 14
77 #define _PAGE_SIZE_64K 16
78 #define _PAGE_SIZE_256K 18
79 #define _PAGE_SIZE_1M 20
80 #define _PAGE_SIZE_4M 22
81 #define _PAGE_SIZE_16M 24
82 #define _PAGE_SIZE_64M 26
83 #define _PAGE_SIZE_256M 28
84 #define _PAGE_SIZE_1G 30
85 #define _PAGE_SIZE_4G 32
87 #define __ACCESS_BITS _PAGE_ED | _PAGE_A | _PAGE_P | _PAGE_MA_WB
88 #define __DIRTY_BITS_NO_ED _PAGE_A | _PAGE_P | _PAGE_D | _PAGE_MA_WB
89 #define __DIRTY_BITS _PAGE_ED | __DIRTY_BITS_NO_ED
91 /*
92 * Definitions for first level:
93 *
94 * PGDIR_SHIFT determines what a first-level page table entry can map.
95 */
96 #define PGDIR_SHIFT (PAGE_SHIFT + 2*(PAGE_SHIFT-3))
97 #define PGDIR_SIZE (__IA64_UL(1) << PGDIR_SHIFT)
98 #define PGDIR_MASK (~(PGDIR_SIZE-1))
99 #define PTRS_PER_PGD (1UL << (PAGE_SHIFT-3))
100 #define USER_PTRS_PER_PGD (5*PTRS_PER_PGD/8) /* regions 0-4 are user regions */
101 #define FIRST_USER_ADDRESS 0
103 /*
104 * Definitions for second level:
105 *
106 * PMD_SHIFT determines the size of the area a second-level page table
107 * can map.
108 */
109 #define PMD_SHIFT (PAGE_SHIFT + (PAGE_SHIFT-3))
110 #define PMD_SIZE (1UL << PMD_SHIFT)
111 #define PMD_MASK (~(PMD_SIZE-1))
112 #define PTRS_PER_PMD (1UL << (PAGE_SHIFT-3))
114 /*
115 * Definitions for third level:
116 */
117 #define PTRS_PER_PTE (__IA64_UL(1) << (PAGE_SHIFT-3))
119 /*
120 * All the normal masks have the "page accessed" bits on, as any time
121 * they are used, the page is accessed. They are cleared only by the
122 * page-out routines.
123 */
124 #define PAGE_NONE __pgprot(_PAGE_PROTNONE | _PAGE_A)
125 #define PAGE_SHARED __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_RW)
126 #define PAGE_READONLY __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_R)
127 #define PAGE_COPY __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_R)
128 #define PAGE_COPY_EXEC __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_RX)
129 #define PAGE_GATE __pgprot(__ACCESS_BITS | _PAGE_PL_0 | _PAGE_AR_X_RX)
130 #define PAGE_KERNEL __pgprot(__DIRTY_BITS | _PAGE_PL_0 | _PAGE_AR_RWX)
131 #define PAGE_KERNELRX __pgprot(__ACCESS_BITS | _PAGE_PL_0 | _PAGE_AR_RX)
133 # ifndef __ASSEMBLY__
135 #include <asm/bitops.h>
136 #include <asm/cacheflush.h>
137 #include <asm/mmu_context.h>
138 #include <asm/processor.h>
140 /*
141 * Next come the mappings that determine how mmap() protection bits
142 * (PROT_EXEC, PROT_READ, PROT_WRITE, PROT_NONE) get implemented. The
143 * _P version gets used for a private shared memory segment, the _S
144 * version gets used for a shared memory segment with MAP_SHARED on.
145 * In a private shared memory segment, we do a copy-on-write if a task
146 * attempts to write to the page.
147 */
148 /* xwr */
149 #define __P000 PAGE_NONE
150 #define __P001 PAGE_READONLY
151 #define __P010 PAGE_READONLY /* write to priv pg -> copy & make writable */
152 #define __P011 PAGE_READONLY /* ditto */
153 #define __P100 __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_X_RX)
154 #define __P101 __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_RX)
155 #define __P110 PAGE_COPY_EXEC
156 #define __P111 PAGE_COPY_EXEC
158 #define __S000 PAGE_NONE
159 #define __S001 PAGE_READONLY
160 #define __S010 PAGE_SHARED /* we don't have (and don't need) write-only */
161 #define __S011 PAGE_SHARED
162 #define __S100 __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_X_RX)
163 #define __S101 __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_RX)
164 #define __S110 __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_RWX)
165 #define __S111 __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_RWX)
167 #define pgd_ERROR(e) printk("%s:%d: bad pgd %016lx.\n", __FILE__, __LINE__, pgd_val(e))
168 #define pmd_ERROR(e) printk("%s:%d: bad pmd %016lx.\n", __FILE__, __LINE__, pmd_val(e))
169 #define pte_ERROR(e) printk("%s:%d: bad pte %016lx.\n", __FILE__, __LINE__, pte_val(e))
172 /*
173 * Some definitions to translate between mem_map, PTEs, and page addresses:
174 */
177 /* Quick test to see if ADDR is a (potentially) valid physical address. */
178 static inline long
179 ia64_phys_addr_valid (unsigned long addr)
180 {
181 return (addr & (local_cpu_data->unimpl_pa_mask)) == 0;
182 }
184 /*
185 * kern_addr_valid(ADDR) tests if ADDR is pointing to valid kernel
186 * memory. For the return value to be meaningful, ADDR must be >=
187 * PAGE_OFFSET. This operation can be relatively expensive (e.g.,
188 * require a hash-, or multi-level tree-lookup or something of that
189 * sort) but it guarantees to return TRUE only if accessing the page
190 * at that address does not cause an error. Note that there may be
191 * addresses for which kern_addr_valid() returns FALSE even though an
192 * access would not cause an error (e.g., this is typically true for
193 * memory mapped I/O regions.
194 *
195 * XXX Need to implement this for IA-64.
196 */
197 #define kern_addr_valid(addr) (1)
200 /*
201 * Now come the defines and routines to manage and access the three-level
202 * page table.
203 */
205 /*
206 * On some architectures, special things need to be done when setting
207 * the PTE in a page table. Nothing special needs to be on IA-64.
208 */
209 #define set_pte(ptep, pteval) (*(ptep) = (pteval))
210 #define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval)
212 #define RGN_SIZE (1UL << 61)
213 #define RGN_KERNEL 7
215 #define VMALLOC_START 0xa000000200000000UL
216 #ifdef CONFIG_VIRTUAL_MEM_MAP
217 # define VMALLOC_END_INIT (0xa000000000000000UL + (1UL << (4*PAGE_SHIFT - 9)))
218 # define VMALLOC_END vmalloc_end
219 extern unsigned long vmalloc_end;
220 #else
221 # define VMALLOC_END (0xa000000000000000UL + (1UL << (4*PAGE_SHIFT - 9)))
222 #endif
224 /* fs/proc/kcore.c */
225 #define kc_vaddr_to_offset(v) ((v) - 0xa000000000000000UL)
226 #define kc_offset_to_vaddr(o) ((o) + 0xa000000000000000UL)
228 /*
229 * Conversion functions: convert page frame number (pfn) and a protection value to a page
230 * table entry (pte).
231 */
232 #define pfn_pte(pfn, pgprot) \
233 ({ pte_t __pte; pte_val(__pte) = ((pfn) << PAGE_SHIFT) | pgprot_val(pgprot); __pte; })
235 /* Extract pfn from pte. */
236 #define pte_pfn(_pte) ((pte_val(_pte) & _PFN_MASK) >> PAGE_SHIFT)
238 #define mk_pte(page, pgprot) pfn_pte(page_to_mfn(page), (pgprot))
240 /* This takes a physical page address that is used by the remapping functions */
241 #define mk_pte_phys(physpage, pgprot) \
242 ({ pte_t __pte; pte_val(__pte) = physpage + pgprot_val(pgprot); __pte; })
244 #define pte_modify(_pte, newprot) \
245 (__pte((pte_val(_pte) & ~_PAGE_CHG_MASK) | (pgprot_val(newprot) & _PAGE_CHG_MASK)))
247 #define page_pte_prot(page,prot) mk_pte(page, prot)
248 #define page_pte(page) page_pte_prot(page, __pgprot(0))
250 #define pte_none(pte) (!pte_val(pte))
251 #define pte_present(pte) (pte_val(pte) & (_PAGE_P | _PAGE_PROTNONE))
252 #define pte_clear(mm,addr,pte) (pte_val(*(pte)) = 0UL)
253 /* pte_page() returns the "struct page *" corresponding to the PTE: */
254 #define pte_page(pte) virt_to_page(((pte_val(pte) & _PFN_MASK) + PAGE_OFFSET))
256 #define pmd_none(pmd) (!pmd_val(pmd))
257 #define pmd_bad(pmd) (!ia64_phys_addr_valid(pmd_val(pmd)))
258 #define pmd_present(pmd) (pmd_val(pmd) != 0UL)
259 #define pmd_clear(pmdp) (pmd_val(*(pmdp)) = 0UL)
260 #define pmd_page_kernel(pmd) ((unsigned long) __va(pmd_val(pmd) & _PFN_MASK))
261 #define pmd_page(pmd) virt_to_page((pmd_val(pmd) + PAGE_OFFSET))
263 #define pud_none(pud) (!pud_val(pud))
264 #define pud_bad(pud) (!ia64_phys_addr_valid(pud_val(pud)))
265 #define pud_present(pud) (pud_val(pud) != 0UL)
266 #define pud_clear(pudp) (pud_val(*(pudp)) = 0UL)
268 #define pud_page(pud) ((unsigned long) __va(pud_val(pud) & _PFN_MASK))
270 /*
271 * The following have defined behavior only work if pte_present() is true.
272 */
273 #define pte_user(pte) ((pte_val(pte) & _PAGE_PL_MASK) == _PAGE_PL_3)
274 #define pte_read(pte) (((pte_val(pte) & _PAGE_AR_MASK) >> _PAGE_AR_SHIFT) < 6)
275 #define pte_write(pte) ((unsigned) (((pte_val(pte) & _PAGE_AR_MASK) >> _PAGE_AR_SHIFT) - 2) <= 4)
276 #define pte_exec(pte) ((pte_val(pte) & _PAGE_AR_RX) != 0)
277 #define pte_dirty(pte) ((pte_val(pte) & _PAGE_D) != 0)
278 #define pte_young(pte) ((pte_val(pte) & _PAGE_A) != 0)
279 #define pte_file(pte) ((pte_val(pte) & _PAGE_FILE) != 0)
280 /*
281 * Note: we convert AR_RWX to AR_RX and AR_RW to AR_R by clearing the 2nd bit in the
282 * access rights:
283 */
284 #define pte_wrprotect(pte) (__pte(pte_val(pte) & ~_PAGE_AR_RW))
285 #define pte_mkwrite(pte) (__pte(pte_val(pte) | _PAGE_AR_RW))
286 #define pte_mkexec(pte) (__pte(pte_val(pte) | _PAGE_AR_RX))
287 #define pte_mkold(pte) (__pte(pte_val(pte) & ~_PAGE_A))
288 #define pte_mkyoung(pte) (__pte(pte_val(pte) | _PAGE_A))
289 #define pte_mkclean(pte) (__pte(pte_val(pte) & ~_PAGE_D))
290 #define pte_mkdirty(pte) (__pte(pte_val(pte) | _PAGE_D))
291 #define pte_mkhuge(pte) (__pte(pte_val(pte) | _PAGE_P))
293 /*
294 * Macro to a page protection value as "uncacheable". Note that "protection" is really a
295 * misnomer here as the protection value contains the memory attribute bits, dirty bits,
296 * and various other bits as well.
297 */
298 #define pgprot_noncached(prot) __pgprot((pgprot_val(prot) & ~_PAGE_MA_MASK) | _PAGE_MA_UC)
300 /*
301 * Macro to make mark a page protection value as "write-combining".
302 * Note that "protection" is really a misnomer here as the protection
303 * value contains the memory attribute bits, dirty bits, and various
304 * other bits as well. Accesses through a write-combining translation
305 * works bypasses the caches, but does allow for consecutive writes to
306 * be combined into single (but larger) write transactions.
307 */
308 #define pgprot_writecombine(prot) __pgprot((pgprot_val(prot) & ~_PAGE_MA_MASK) | _PAGE_MA_WC)
310 static inline unsigned long
311 pgd_index (unsigned long address)
312 {
313 unsigned long region = address >> 61;
314 unsigned long l1index = (address >> PGDIR_SHIFT) & ((PTRS_PER_PGD >> 3) - 1);
316 return (region << (PAGE_SHIFT - 6)) | l1index;
317 }
319 /* The offset in the 1-level directory is given by the 3 region bits
320 (61..63) and the level-1 bits. */
321 static inline pgd_t*
322 pgd_offset (struct mm_struct *mm, unsigned long address)
323 {
324 return mm->pgd + pgd_index(address);
325 }
327 /* In the kernel's mapped region we completely ignore the region number
328 (since we know it's in region number 5). */
329 #define pgd_offset_k(addr) \
330 (init_mm.pgd + (((addr) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1)))
332 /* Look up a pgd entry in the gate area. On IA-64, the gate-area
333 resides in the kernel-mapped segment, hence we use pgd_offset_k()
334 here. */
335 #define pgd_offset_gate(mm, addr) pgd_offset_k(addr)
337 /* Find an entry in the second-level page table.. */
338 #define pmd_offset(dir,addr) \
339 ((pmd_t *) pud_page(*(dir)) + (((addr) >> PMD_SHIFT) & (PTRS_PER_PMD - 1)))
341 /*
342 * Find an entry in the third-level page table. This looks more complicated than it
343 * should be because some platforms place page tables in high memory.
344 */
345 #define pte_index(addr) (((addr) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
346 #define pte_offset_kernel(dir,addr) ((pte_t *) pmd_page_kernel(*(dir)) + pte_index(addr))
347 #define pte_offset_map(dir,addr) pte_offset_kernel(dir, addr)
348 #define pte_offset_map_nested(dir,addr) pte_offset_map(dir, addr)
349 #define pte_unmap(pte) do { } while (0)
350 #define pte_unmap_nested(pte) do { } while (0)
352 #ifndef XEN
353 /* atomic versions of the some PTE manipulations: */
355 static inline int
356 ptep_test_and_clear_young (struct vm_area_struct *vma, unsigned long addr, pte_t *ptep)
357 {
358 #ifdef CONFIG_SMP
359 if (!pte_young(*ptep))
360 return 0;
361 return test_and_clear_bit(_PAGE_A_BIT, ptep);
362 #else
363 pte_t pte = *ptep;
364 if (!pte_young(pte))
365 return 0;
366 set_pte_at(vma->vm_mm, addr, ptep, pte_mkold(pte));
367 return 1;
368 #endif
369 }
371 static inline int
372 ptep_test_and_clear_dirty (struct vm_area_struct *vma, unsigned long addr, pte_t *ptep)
373 {
374 #ifdef CONFIG_SMP
375 if (!pte_dirty(*ptep))
376 return 0;
377 return test_and_clear_bit(_PAGE_D_BIT, ptep);
378 #else
379 pte_t pte = *ptep;
380 if (!pte_dirty(pte))
381 return 0;
382 set_pte_at(vma->vm_mm, addr, ptep, pte_mkclean(pte));
383 return 1;
384 #endif
385 }
387 static inline pte_t
388 ptep_get_and_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
389 {
390 #ifdef CONFIG_SMP
391 return __pte(xchg((long *) ptep, 0));
392 #else
393 pte_t pte = *ptep;
394 pte_clear(mm, addr, ptep);
395 return pte;
396 #endif
397 }
399 static inline void
400 ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
401 {
402 #ifdef CONFIG_SMP
403 unsigned long new, old;
405 do {
406 old = pte_val(*ptep);
407 new = pte_val(pte_wrprotect(__pte (old)));
408 } while (cmpxchg((unsigned long *) ptep, old, new) != old);
409 #else
410 pte_t old_pte = *ptep;
411 set_pte_at(mm, addr, ptep, pte_wrprotect(old_pte));
412 #endif
413 }
415 static inline int
416 pte_same (pte_t a, pte_t b)
417 {
418 return pte_val(a) == pte_val(b);
419 }
421 #define update_mmu_cache(vma, address, pte) do { } while (0)
422 #endif /* XEN */
424 extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
425 extern void paging_init (void);
427 /*
428 * Note: The macros below rely on the fact that MAX_SWAPFILES_SHIFT <= number of
429 * bits in the swap-type field of the swap pte. It would be nice to
430 * enforce that, but we can't easily include <linux/swap.h> here.
431 * (Of course, better still would be to define MAX_SWAPFILES_SHIFT here...).
432 *
433 * Format of swap pte:
434 * bit 0 : present bit (must be zero)
435 * bit 1 : _PAGE_FILE (must be zero)
436 * bits 2- 8: swap-type
437 * bits 9-62: swap offset
438 * bit 63 : _PAGE_PROTNONE bit
439 *
440 * Format of file pte:
441 * bit 0 : present bit (must be zero)
442 * bit 1 : _PAGE_FILE (must be one)
443 * bits 2-62: file_offset/PAGE_SIZE
444 * bit 63 : _PAGE_PROTNONE bit
445 */
446 #define __swp_type(entry) (((entry).val >> 2) & 0x7f)
447 #define __swp_offset(entry) (((entry).val << 1) >> 10)
448 #define __swp_entry(type,offset) ((swp_entry_t) { ((type) << 2) | ((long) (offset) << 9) })
449 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
450 #define __swp_entry_to_pte(x) ((pte_t) { (x).val })
452 #define PTE_FILE_MAX_BITS 61
453 #define pte_to_pgoff(pte) ((pte_val(pte) << 1) >> 3)
454 #define pgoff_to_pte(off) ((pte_t) { ((off) << 2) | _PAGE_FILE })
456 /* XXX is this right? */
457 #define io_remap_page_range(vma, vaddr, paddr, size, prot) \
458 remap_pfn_range(vma, vaddr, (paddr) >> PAGE_SHIFT, size, prot)
460 #define io_remap_pfn_range(vma, vaddr, pfn, size, prot) \
461 remap_pfn_range(vma, vaddr, pfn, size, prot)
463 #define MK_IOSPACE_PFN(space, pfn) (pfn)
464 #define GET_IOSPACE(pfn) 0
465 #define GET_PFN(pfn) (pfn)
467 /*
468 * ZERO_PAGE is a global shared page that is always zero: used
469 * for zero-mapped memory areas etc..
470 */
471 extern unsigned long empty_zero_page[PAGE_SIZE/sizeof(unsigned long)];
472 #ifndef XEN
473 extern struct page *zero_page_memmap_ptr;
474 #define ZERO_PAGE(vaddr) (zero_page_memmap_ptr)
475 #endif
477 /* We provide our own get_unmapped_area to cope with VA holes for userland */
478 #define HAVE_ARCH_UNMAPPED_AREA
480 #ifdef CONFIG_HUGETLB_PAGE
481 #define HUGETLB_PGDIR_SHIFT (HPAGE_SHIFT + 2*(PAGE_SHIFT-3))
482 #define HUGETLB_PGDIR_SIZE (__IA64_UL(1) << HUGETLB_PGDIR_SHIFT)
483 #define HUGETLB_PGDIR_MASK (~(HUGETLB_PGDIR_SIZE-1))
484 struct mmu_gather;
485 void hugetlb_free_pgd_range(struct mmu_gather **tlb, unsigned long addr,
486 unsigned long end, unsigned long floor, unsigned long ceiling);
487 #endif
489 /*
490 * IA-64 doesn't have any external MMU info: the page tables contain all the necessary
491 * information. However, we use this routine to take care of any (delayed) i-cache
492 * flushing that may be necessary.
493 */
494 extern void lazy_mmu_prot_update (pte_t pte);
496 #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
497 /*
498 * Update PTEP with ENTRY, which is guaranteed to be a less
499 * restrictive PTE. That is, ENTRY may have the ACCESSED, DIRTY, and
500 * WRITABLE bits turned on, when the value at PTEP did not. The
501 * WRITABLE bit may only be turned if SAFELY_WRITABLE is TRUE.
502 *
503 * SAFELY_WRITABLE is TRUE if we can update the value at PTEP without
504 * having to worry about races. On SMP machines, there are only two
505 * cases where this is true:
506 *
507 * (1) *PTEP has the PRESENT bit turned OFF
508 * (2) ENTRY has the DIRTY bit turned ON
509 *
510 * On ia64, we could implement this routine with a cmpxchg()-loop
511 * which ORs in the _PAGE_A/_PAGE_D bit if they're set in ENTRY.
512 * However, like on x86, we can get a more streamlined version by
513 * observing that it is OK to drop ACCESSED bit updates when
514 * SAFELY_WRITABLE is FALSE. Besides being rare, all that would do is
515 * result in an extra Access-bit fault, which would then turn on the
516 * ACCESSED bit in the low-level fault handler (iaccess_bit or
517 * daccess_bit in ivt.S).
518 */
519 #ifdef CONFIG_SMP
520 # define ptep_set_access_flags(__vma, __addr, __ptep, __entry, __safely_writable) \
521 do { \
522 if (__safely_writable) { \
523 set_pte(__ptep, __entry); \
524 flush_tlb_page(__vma, __addr); \
525 } \
526 } while (0)
527 #else
528 # define ptep_set_access_flags(__vma, __addr, __ptep, __entry, __safely_writable) \
529 ptep_establish(__vma, __addr, __ptep, __entry)
530 #endif
532 # ifdef CONFIG_VIRTUAL_MEM_MAP
533 /* arch mem_map init routine is needed due to holes in a virtual mem_map */
534 # define __HAVE_ARCH_MEMMAP_INIT
535 extern void memmap_init (unsigned long size, int nid, unsigned long zone,
536 unsigned long start_pfn);
537 # endif /* CONFIG_VIRTUAL_MEM_MAP */
538 # endif /* !__ASSEMBLY__ */
540 /*
541 * Identity-mapped regions use a large page size. We'll call such large pages
542 * "granules". If you can think of a better name that's unambiguous, let me
543 * know...
544 */
545 #if defined(CONFIG_IA64_GRANULE_64MB)
546 # define IA64_GRANULE_SHIFT _PAGE_SIZE_64M
547 #elif defined(CONFIG_IA64_GRANULE_16MB)
548 # define IA64_GRANULE_SHIFT _PAGE_SIZE_16M
549 #endif
550 #define IA64_GRANULE_SIZE (1 << IA64_GRANULE_SHIFT)
551 /*
552 * log2() of the page size we use to map the kernel image (IA64_TR_KERNEL):
553 */
554 #define KERNEL_TR_PAGE_SHIFT _PAGE_SIZE_64M
555 #define KERNEL_TR_PAGE_SIZE (1 << KERNEL_TR_PAGE_SHIFT)
557 /*
558 * No page table caches to initialise
559 */
560 #define pgtable_cache_init() do { } while (0)
562 /* These tell get_user_pages() that the first gate page is accessible from user-level. */
563 #define FIXADDR_USER_START GATE_ADDR
564 #ifdef HAVE_BUGGY_SEGREL
565 # define FIXADDR_USER_END (GATE_ADDR + 2*PAGE_SIZE)
566 #else
567 # define FIXADDR_USER_END (GATE_ADDR + 2*PERCPU_PAGE_SIZE)
568 #endif
570 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
571 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_DIRTY
572 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR
573 #define __HAVE_ARCH_PTEP_SET_WRPROTECT
574 #define __HAVE_ARCH_PTE_SAME
575 #define __HAVE_ARCH_PGD_OFFSET_GATE
576 #define __HAVE_ARCH_LAZY_MMU_PROT_UPDATE
578 #include <asm-generic/pgtable-nopud.h>
579 #include <asm-generic/pgtable.h>
581 #endif /* _ASM_IA64_PGTABLE_H */