ia64/xen-unstable

view xen/arch/ia64/linux-xen/setup.c @ 9770:ced37bea0647

[IA64] FPH enabling + cleanup

Move contents of switch_to macro from xensystem.h to context_switch function.
Initialize FPU on all processors. FPH is always enabled in Xen.
Speed up context-switch (a little bit!) by not enabling/disabling FPH.
Cleanup (unused function/variablesi/fields, debug printf...)
vmx_ia64_switch_to removed (was unused).

Signed-off-by: Tristan Gingold <tristan.gingold@bull.net>
author awilliam@xenbuild.aw
date Tue Apr 25 22:35:41 2006 -0600 (2006-04-25)
parents bdb08c9ef3d1
children ddcd9c267612
line source
1 /*
2 * Architecture-specific setup.
3 *
4 * Copyright (C) 1998-2001, 2003-2004 Hewlett-Packard Co
5 * David Mosberger-Tang <davidm@hpl.hp.com>
6 * Stephane Eranian <eranian@hpl.hp.com>
7 * Copyright (C) 2000, 2004 Intel Corp
8 * Rohit Seth <rohit.seth@intel.com>
9 * Suresh Siddha <suresh.b.siddha@intel.com>
10 * Gordon Jin <gordon.jin@intel.com>
11 * Copyright (C) 1999 VA Linux Systems
12 * Copyright (C) 1999 Walt Drummond <drummond@valinux.com>
13 *
14 * 12/26/04 S.Siddha, G.Jin, R.Seth
15 * Add multi-threading and multi-core detection
16 * 11/12/01 D.Mosberger Convert get_cpuinfo() to seq_file based show_cpuinfo().
17 * 04/04/00 D.Mosberger renamed cpu_initialized to cpu_online_map
18 * 03/31/00 R.Seth cpu_initialized and current->processor fixes
19 * 02/04/00 D.Mosberger some more get_cpuinfo fixes...
20 * 02/01/00 R.Seth fixed get_cpuinfo for SMP
21 * 01/07/99 S.Eranian added the support for command line argument
22 * 06/24/99 W.Drummond added boot_cpu_data.
23 * 05/28/05 Z. Menyhart Dynamic stride size for "flush_icache_range()"
24 */
25 #include <linux/config.h>
26 #include <linux/module.h>
27 #include <linux/init.h>
29 #include <linux/acpi.h>
30 #include <linux/bootmem.h>
31 #include <linux/console.h>
32 #include <linux/delay.h>
33 #include <linux/kernel.h>
34 #include <linux/reboot.h>
35 #include <linux/sched.h>
36 #include <linux/seq_file.h>
37 #include <linux/string.h>
38 #include <linux/threads.h>
39 #include <linux/tty.h>
40 #include <linux/serial.h>
41 #include <linux/serial_core.h>
42 #include <linux/efi.h>
43 #include <linux/initrd.h>
44 #ifndef XEN
45 #include <linux/platform.h>
46 #include <linux/pm.h>
47 #endif
49 #include <asm/ia32.h>
50 #include <asm/machvec.h>
51 #include <asm/mca.h>
52 #include <asm/meminit.h>
53 #include <asm/page.h>
54 #include <asm/patch.h>
55 #include <asm/pgtable.h>
56 #include <asm/processor.h>
57 #include <asm/sal.h>
58 #include <asm/sections.h>
59 #include <asm/serial.h>
60 #include <asm/setup.h>
61 #include <asm/smp.h>
62 #include <asm/system.h>
63 #include <asm/unistd.h>
64 #ifdef XEN
65 #include <asm/vmx.h>
66 #include <asm/io.h>
67 #endif
69 #if defined(CONFIG_SMP) && (IA64_CPU_SIZE > PAGE_SIZE)
70 # error "struct cpuinfo_ia64 too big!"
71 #endif
73 #ifdef CONFIG_SMP
74 unsigned long __per_cpu_offset[NR_CPUS];
75 EXPORT_SYMBOL(__per_cpu_offset);
76 #endif
78 DEFINE_PER_CPU(struct cpuinfo_ia64, cpu_info);
79 #ifdef XEN
80 DEFINE_PER_CPU(cpu_kr_ia64_t, cpu_kr);
81 #endif
82 DEFINE_PER_CPU(unsigned long, local_per_cpu_offset);
83 DEFINE_PER_CPU(unsigned long, ia64_phys_stacked_size_p8);
84 unsigned long ia64_cycles_per_usec;
85 struct ia64_boot_param *ia64_boot_param;
86 struct screen_info screen_info;
87 unsigned long vga_console_iobase;
88 unsigned long vga_console_membase;
90 unsigned long ia64_max_cacheline_size;
91 unsigned long ia64_iobase; /* virtual address for I/O accesses */
92 EXPORT_SYMBOL(ia64_iobase);
93 struct io_space io_space[MAX_IO_SPACES];
94 EXPORT_SYMBOL(io_space);
95 unsigned int num_io_spaces;
97 #ifdef XEN
98 extern void early_cmdline_parse(char **);
99 #endif
101 /*
102 * "flush_icache_range()" needs to know what processor dependent stride size to use
103 * when it makes i-cache(s) coherent with d-caches.
104 */
105 #define I_CACHE_STRIDE_SHIFT 5 /* Safest way to go: 32 bytes by 32 bytes */
106 unsigned long ia64_i_cache_stride_shift = ~0;
108 #ifdef XEN
109 #define D_CACHE_STRIDE_SHIFT 5 /* Safest. */
110 unsigned long ia64_d_cache_stride_shift = ~0;
111 #endif
113 /*
114 * The merge_mask variable needs to be set to (max(iommu_page_size(iommu)) - 1). This
115 * mask specifies a mask of address bits that must be 0 in order for two buffers to be
116 * mergeable by the I/O MMU (i.e., the end address of the first buffer and the start
117 * address of the second buffer must be aligned to (merge_mask+1) in order to be
118 * mergeable). By default, we assume there is no I/O MMU which can merge physically
119 * discontiguous buffers, so we set the merge_mask to ~0UL, which corresponds to a iommu
120 * page-size of 2^64.
121 */
122 unsigned long ia64_max_iommu_merge_mask = ~0UL;
123 EXPORT_SYMBOL(ia64_max_iommu_merge_mask);
125 /*
126 * We use a special marker for the end of memory and it uses the extra (+1) slot
127 */
128 struct rsvd_region rsvd_region[IA64_MAX_RSVD_REGIONS + 1];
129 int num_rsvd_regions;
132 /*
133 * Filter incoming memory segments based on the primitive map created from the boot
134 * parameters. Segments contained in the map are removed from the memory ranges. A
135 * caller-specified function is called with the memory ranges that remain after filtering.
136 * This routine does not assume the incoming segments are sorted.
137 */
138 int
139 filter_rsvd_memory (unsigned long start, unsigned long end, void *arg)
140 {
141 unsigned long range_start, range_end, prev_start;
142 void (*func)(unsigned long, unsigned long, int);
143 int i;
145 #if IGNORE_PFN0
146 if (start == PAGE_OFFSET) {
147 printk(KERN_WARNING "warning: skipping physical page 0\n");
148 start += PAGE_SIZE;
149 if (start >= end) return 0;
150 }
151 #endif
152 /*
153 * lowest possible address(walker uses virtual)
154 */
155 prev_start = PAGE_OFFSET;
156 func = arg;
158 for (i = 0; i < num_rsvd_regions; ++i) {
159 range_start = max(start, prev_start);
160 range_end = min(end, rsvd_region[i].start);
162 if (range_start < range_end)
163 #ifdef XEN
164 {
165 /* init_boot_pages requires "ps, pe" */
166 printk("Init boot pages: 0x%lx -> 0x%lx.\n",
167 __pa(range_start), __pa(range_end));
168 (*func)(__pa(range_start), __pa(range_end), 0);
169 }
170 #else
171 call_pernode_memory(__pa(range_start), range_end - range_start, func);
172 #endif
174 /* nothing more available in this segment */
175 if (range_end == end) return 0;
177 prev_start = rsvd_region[i].end;
178 }
179 /* end of memory marker allows full processing inside loop body */
180 return 0;
181 }
183 static void
184 sort_regions (struct rsvd_region *rsvd_region, int max)
185 {
186 int j;
188 /* simple bubble sorting */
189 while (max--) {
190 for (j = 0; j < max; ++j) {
191 if (rsvd_region[j].start > rsvd_region[j+1].start) {
192 struct rsvd_region tmp;
193 tmp = rsvd_region[j];
194 rsvd_region[j] = rsvd_region[j + 1];
195 rsvd_region[j + 1] = tmp;
196 }
197 }
198 }
199 }
201 /**
202 * reserve_memory - setup reserved memory areas
203 *
204 * Setup the reserved memory areas set aside for the boot parameters,
205 * initrd, etc. There are currently %IA64_MAX_RSVD_REGIONS defined,
206 * see include/asm-ia64/meminit.h if you need to define more.
207 */
208 void
209 reserve_memory (void)
210 {
211 int n = 0;
213 /*
214 * none of the entries in this table overlap
215 */
216 rsvd_region[n].start = (unsigned long) ia64_boot_param;
217 rsvd_region[n].end = rsvd_region[n].start + sizeof(*ia64_boot_param);
218 n++;
220 rsvd_region[n].start = (unsigned long) __va(ia64_boot_param->efi_memmap);
221 rsvd_region[n].end = rsvd_region[n].start + ia64_boot_param->efi_memmap_size;
222 n++;
224 rsvd_region[n].start = (unsigned long) __va(ia64_boot_param->command_line);
225 rsvd_region[n].end = (rsvd_region[n].start
226 + strlen(__va(ia64_boot_param->command_line)) + 1);
227 n++;
229 rsvd_region[n].start = (unsigned long) ia64_imva((void *)KERNEL_START);
230 #ifdef XEN
231 /* Reserve xen image/bitmap/xen-heap */
232 rsvd_region[n].end = rsvd_region[n].start + xenheap_size;
233 #else
234 rsvd_region[n].end = (unsigned long) ia64_imva(_end);
235 #endif
236 n++;
238 #ifdef CONFIG_BLK_DEV_INITRD
239 if (ia64_boot_param->initrd_start) {
240 rsvd_region[n].start = (unsigned long)__va(ia64_boot_param->initrd_start);
241 rsvd_region[n].end = rsvd_region[n].start + ia64_boot_param->initrd_size;
242 n++;
243 }
244 #endif
246 /* end of memory marker */
247 rsvd_region[n].start = ~0UL;
248 rsvd_region[n].end = ~0UL;
249 n++;
251 num_rsvd_regions = n;
253 sort_regions(rsvd_region, num_rsvd_regions);
254 }
256 /**
257 * find_initrd - get initrd parameters from the boot parameter structure
258 *
259 * Grab the initrd start and end from the boot parameter struct given us by
260 * the boot loader.
261 */
262 void
263 find_initrd (void)
264 {
265 #ifdef CONFIG_BLK_DEV_INITRD
266 if (ia64_boot_param->initrd_start) {
267 initrd_start = (unsigned long)__va(ia64_boot_param->initrd_start);
268 initrd_end = initrd_start+ia64_boot_param->initrd_size;
270 printk(KERN_INFO "Initial ramdisk at: 0x%lx (%lu bytes)\n",
271 initrd_start, ia64_boot_param->initrd_size);
272 }
273 #endif
274 }
276 static void __init
277 io_port_init (void)
278 {
279 extern unsigned long ia64_iobase;
280 unsigned long phys_iobase;
282 /*
283 * Set `iobase' to the appropriate address in region 6 (uncached access range).
284 *
285 * The EFI memory map is the "preferred" location to get the I/O port space base,
286 * rather the relying on AR.KR0. This should become more clear in future SAL
287 * specs. We'll fall back to getting it out of AR.KR0 if no appropriate entry is
288 * found in the memory map.
289 */
290 phys_iobase = efi_get_iobase();
291 if (phys_iobase)
292 /* set AR.KR0 since this is all we use it for anyway */
293 ia64_set_kr(IA64_KR_IO_BASE, phys_iobase);
294 else {
295 phys_iobase = ia64_get_kr(IA64_KR_IO_BASE);
296 printk(KERN_INFO "No I/O port range found in EFI memory map, falling back "
297 "to AR.KR0\n");
298 printk(KERN_INFO "I/O port base = 0x%lx\n", phys_iobase);
299 }
300 ia64_iobase = (unsigned long) ioremap(phys_iobase, 0);
302 /* setup legacy IO port space */
303 io_space[0].mmio_base = ia64_iobase;
304 io_space[0].sparse = 1;
305 num_io_spaces = 1;
306 }
308 /**
309 * early_console_setup - setup debugging console
310 *
311 * Consoles started here require little enough setup that we can start using
312 * them very early in the boot process, either right after the machine
313 * vector initialization, or even before if the drivers can detect their hw.
314 *
315 * Returns non-zero if a console couldn't be setup.
316 */
317 static inline int __init
318 early_console_setup (char *cmdline)
319 {
320 int earlycons = 0;
322 #ifdef CONFIG_SERIAL_SGI_L1_CONSOLE
323 {
324 extern int sn_serial_console_early_setup(void);
325 if (!sn_serial_console_early_setup())
326 earlycons++;
327 }
328 #endif
329 #ifdef CONFIG_EFI_PCDP
330 if (!efi_setup_pcdp_console(cmdline))
331 earlycons++;
332 #endif
333 #ifdef CONFIG_SERIAL_8250_CONSOLE
334 if (!early_serial_console_init(cmdline))
335 earlycons++;
336 #endif
338 return (earlycons) ? 0 : -1;
339 }
341 static inline void
342 mark_bsp_online (void)
343 {
344 #ifdef CONFIG_SMP
345 /* If we register an early console, allow CPU 0 to printk */
346 cpu_set(smp_processor_id(), cpu_online_map);
347 #endif
348 }
350 #ifdef CONFIG_SMP
351 static void
352 check_for_logical_procs (void)
353 {
354 pal_logical_to_physical_t info;
355 s64 status;
357 status = ia64_pal_logical_to_phys(0, &info);
358 if (status == -1) {
359 printk(KERN_INFO "No logical to physical processor mapping "
360 "available\n");
361 return;
362 }
363 if (status) {
364 printk(KERN_ERR "ia64_pal_logical_to_phys failed with %ld\n",
365 status);
366 return;
367 }
368 /*
369 * Total number of siblings that BSP has. Though not all of them
370 * may have booted successfully. The correct number of siblings
371 * booted is in info.overview_num_log.
372 */
373 smp_num_siblings = info.overview_tpc;
374 smp_num_cpucores = info.overview_cpp;
375 }
376 #endif
378 void __init
379 #ifdef XEN
380 early_setup_arch (char **cmdline_p)
381 #else
382 setup_arch (char **cmdline_p)
383 #endif
384 {
385 unw_init();
387 #ifndef XEN
388 ia64_patch_vtop((u64) __start___vtop_patchlist, (u64) __end___vtop_patchlist);
389 #endif
391 *cmdline_p = __va(ia64_boot_param->command_line);
392 #ifndef XEN
393 strlcpy(saved_command_line, *cmdline_p, COMMAND_LINE_SIZE);
394 #else
395 early_cmdline_parse(cmdline_p);
396 cmdline_parse(*cmdline_p);
397 #endif
399 efi_init();
400 io_port_init();
402 #ifdef CONFIG_IA64_GENERIC
403 {
404 const char *mvec_name = strstr (*cmdline_p, "machvec=");
405 char str[64];
407 if (mvec_name) {
408 const char *end;
409 size_t len;
411 mvec_name += 8;
412 end = strchr (mvec_name, ' ');
413 if (end)
414 len = end - mvec_name;
415 else
416 len = strlen (mvec_name);
417 len = min(len, sizeof (str) - 1);
418 strncpy (str, mvec_name, len);
419 str[len] = '\0';
420 mvec_name = str;
421 } else
422 mvec_name = acpi_get_sysname();
423 machvec_init(mvec_name);
424 }
425 #endif
427 if (early_console_setup(*cmdline_p) == 0)
428 mark_bsp_online();
430 #ifdef XEN
431 }
433 void __init
434 late_setup_arch (char **cmdline_p)
435 {
436 #endif
437 #ifdef CONFIG_ACPI_BOOT
438 /* Initialize the ACPI boot-time table parser */
439 acpi_table_init();
440 # ifdef CONFIG_ACPI_NUMA
441 acpi_numa_init();
442 # endif
443 #else
444 # ifdef CONFIG_SMP
445 smp_build_cpu_map(); /* happens, e.g., with the Ski simulator */
446 # endif
447 #endif /* CONFIG_APCI_BOOT */
449 #ifndef XEN
450 find_memory();
451 #endif
453 /* process SAL system table: */
454 ia64_sal_init(efi.sal_systab);
456 #ifdef CONFIG_SMP
457 #ifdef XEN
458 init_smp_config ();
459 #endif
461 cpu_physical_id(0) = hard_smp_processor_id();
463 cpu_set(0, cpu_sibling_map[0]);
464 cpu_set(0, cpu_core_map[0]);
466 check_for_logical_procs();
467 if (smp_num_cpucores > 1)
468 printk(KERN_INFO
469 "cpu package is Multi-Core capable: number of cores=%d\n",
470 smp_num_cpucores);
471 if (smp_num_siblings > 1)
472 printk(KERN_INFO
473 "cpu package is Multi-Threading capable: number of siblings=%d\n",
474 smp_num_siblings);
475 #endif
477 #ifdef XEN
478 identify_vmx_feature();
479 #endif
481 cpu_init(); /* initialize the bootstrap CPU */
483 #ifdef CONFIG_ACPI_BOOT
484 acpi_boot_init();
485 #endif
487 #ifdef CONFIG_VT
488 if (!conswitchp) {
489 # if defined(CONFIG_DUMMY_CONSOLE)
490 conswitchp = &dummy_con;
491 # endif
492 # if defined(CONFIG_VGA_CONSOLE)
493 /*
494 * Non-legacy systems may route legacy VGA MMIO range to system
495 * memory. vga_con probes the MMIO hole, so memory looks like
496 * a VGA device to it. The EFI memory map can tell us if it's
497 * memory so we can avoid this problem.
498 */
499 if (efi_mem_type(0xA0000) != EFI_CONVENTIONAL_MEMORY)
500 conswitchp = &vga_con;
501 # endif
502 }
503 #endif
505 /* enable IA-64 Machine Check Abort Handling unless disabled */
506 if (!strstr(saved_command_line, "nomca"))
507 ia64_mca_init();
509 platform_setup(cmdline_p);
510 paging_init();
511 }
513 #ifndef XEN
514 /*
515 * Display cpu info for all cpu's.
516 */
517 static int
518 show_cpuinfo (struct seq_file *m, void *v)
519 {
520 #ifdef CONFIG_SMP
521 # define lpj c->loops_per_jiffy
522 # define cpunum c->cpu
523 #else
524 # define lpj loops_per_jiffy
525 # define cpunum 0
526 #endif
527 static struct {
528 unsigned long mask;
529 const char *feature_name;
530 } feature_bits[] = {
531 { 1UL << 0, "branchlong" },
532 { 1UL << 1, "spontaneous deferral"},
533 { 1UL << 2, "16-byte atomic ops" }
534 };
535 char family[32], features[128], *cp, sep;
536 struct cpuinfo_ia64 *c = v;
537 unsigned long mask;
538 int i;
540 mask = c->features;
542 switch (c->family) {
543 case 0x07: memcpy(family, "Itanium", 8); break;
544 case 0x1f: memcpy(family, "Itanium 2", 10); break;
545 default: sprintf(family, "%u", c->family); break;
546 }
548 /* build the feature string: */
549 memcpy(features, " standard", 10);
550 cp = features;
551 sep = 0;
552 for (i = 0; i < (int) ARRAY_SIZE(feature_bits); ++i) {
553 if (mask & feature_bits[i].mask) {
554 if (sep)
555 *cp++ = sep;
556 sep = ',';
557 *cp++ = ' ';
558 strcpy(cp, feature_bits[i].feature_name);
559 cp += strlen(feature_bits[i].feature_name);
560 mask &= ~feature_bits[i].mask;
561 }
562 }
563 if (mask) {
564 /* print unknown features as a hex value: */
565 if (sep)
566 *cp++ = sep;
567 sprintf(cp, " 0x%lx", mask);
568 }
570 seq_printf(m,
571 "processor : %d\n"
572 "vendor : %s\n"
573 "arch : IA-64\n"
574 "family : %s\n"
575 "model : %u\n"
576 "revision : %u\n"
577 "archrev : %u\n"
578 "features :%s\n" /* don't change this---it _is_ right! */
579 "cpu number : %lu\n"
580 "cpu regs : %u\n"
581 "cpu MHz : %lu.%06lu\n"
582 "itc MHz : %lu.%06lu\n"
583 "BogoMIPS : %lu.%02lu\n",
584 cpunum, c->vendor, family, c->model, c->revision, c->archrev,
585 features, c->ppn, c->number,
586 c->proc_freq / 1000000, c->proc_freq % 1000000,
587 c->itc_freq / 1000000, c->itc_freq % 1000000,
588 lpj*HZ/500000, (lpj*HZ/5000) % 100);
589 #ifdef CONFIG_SMP
590 seq_printf(m, "siblings : %u\n", c->num_log);
591 if (c->threads_per_core > 1 || c->cores_per_socket > 1)
592 seq_printf(m,
593 "physical id: %u\n"
594 "core id : %u\n"
595 "thread id : %u\n",
596 c->socket_id, c->core_id, c->thread_id);
597 #endif
598 seq_printf(m,"\n");
600 return 0;
601 }
603 static void *
604 c_start (struct seq_file *m, loff_t *pos)
605 {
606 #ifdef CONFIG_SMP
607 while (*pos < NR_CPUS && !cpu_isset(*pos, cpu_online_map))
608 ++*pos;
609 #endif
610 return *pos < NR_CPUS ? cpu_data(*pos) : NULL;
611 }
613 static void *
614 c_next (struct seq_file *m, void *v, loff_t *pos)
615 {
616 ++*pos;
617 return c_start(m, pos);
618 }
620 static void
621 c_stop (struct seq_file *m, void *v)
622 {
623 }
625 struct seq_operations cpuinfo_op = {
626 .start = c_start,
627 .next = c_next,
628 .stop = c_stop,
629 .show = show_cpuinfo
630 };
631 #endif /* XEN */
633 void
634 identify_cpu (struct cpuinfo_ia64 *c)
635 {
636 union {
637 unsigned long bits[5];
638 struct {
639 /* id 0 & 1: */
640 char vendor[16];
642 /* id 2 */
643 u64 ppn; /* processor serial number */
645 /* id 3: */
646 unsigned number : 8;
647 unsigned revision : 8;
648 unsigned model : 8;
649 unsigned family : 8;
650 unsigned archrev : 8;
651 unsigned reserved : 24;
653 /* id 4: */
654 u64 features;
655 } field;
656 } cpuid;
657 pal_vm_info_1_u_t vm1;
658 pal_vm_info_2_u_t vm2;
659 pal_status_t status;
660 unsigned long impl_va_msb = 50, phys_addr_size = 44; /* Itanium defaults */
661 int i;
663 for (i = 0; i < 5; ++i)
664 cpuid.bits[i] = ia64_get_cpuid(i);
666 memcpy(c->vendor, cpuid.field.vendor, 16);
667 #ifdef CONFIG_SMP
668 c->cpu = smp_processor_id();
670 /* below default values will be overwritten by identify_siblings()
671 * for Multi-Threading/Multi-Core capable cpu's
672 */
673 c->threads_per_core = c->cores_per_socket = c->num_log = 1;
674 c->socket_id = -1;
676 identify_siblings(c);
677 #endif
678 c->ppn = cpuid.field.ppn;
679 c->number = cpuid.field.number;
680 c->revision = cpuid.field.revision;
681 c->model = cpuid.field.model;
682 c->family = cpuid.field.family;
683 c->archrev = cpuid.field.archrev;
684 c->features = cpuid.field.features;
686 status = ia64_pal_vm_summary(&vm1, &vm2);
687 if (status == PAL_STATUS_SUCCESS) {
688 impl_va_msb = vm2.pal_vm_info_2_s.impl_va_msb;
689 phys_addr_size = vm1.pal_vm_info_1_s.phys_add_size;
690 }
691 c->unimpl_va_mask = ~((7L<<61) | ((1L << (impl_va_msb + 1)) - 1));
692 c->unimpl_pa_mask = ~((1L<<63) | ((1L << phys_addr_size) - 1));
694 #ifdef XEN
695 /* If vmx feature is on, do necessary initialization for vmx */
696 if (vmx_enabled)
697 vmx_init_env();
698 #endif
699 }
701 void
702 setup_per_cpu_areas (void)
703 {
704 /* start_kernel() requires this... */
705 }
707 /*
708 * Calculate the max. cache line size.
709 *
710 * In addition, the minimum of the i-cache stride sizes is calculated for
711 * "flush_icache_range()".
712 */
713 static void
714 get_max_cacheline_size (void)
715 {
716 unsigned long line_size, max = 1;
717 u64 l, levels, unique_caches;
718 pal_cache_config_info_t cci;
719 s64 status;
721 status = ia64_pal_cache_summary(&levels, &unique_caches);
722 if (status != 0) {
723 printk(KERN_ERR "%s: ia64_pal_cache_summary() failed (status=%ld)\n",
724 __FUNCTION__, status);
725 max = SMP_CACHE_BYTES;
726 /* Safest setup for "flush_icache_range()" */
727 ia64_i_cache_stride_shift = I_CACHE_STRIDE_SHIFT;
728 #ifdef XEN
729 ia64_d_cache_stride_shift = D_CACHE_STRIDE_SHIFT;
730 #endif
731 goto out;
732 }
734 for (l = 0; l < levels; ++l) {
735 status = ia64_pal_cache_config_info(l, /* cache_type (data_or_unified)= */ 2,
736 &cci);
737 if (status != 0) {
738 printk(KERN_ERR
739 "%s: ia64_pal_cache_config_info(l=%lu, 2) failed (status=%ld)\n",
740 __FUNCTION__, l, status);
741 max = SMP_CACHE_BYTES;
742 /* The safest setup for "flush_icache_range()" */
743 cci.pcci_stride = I_CACHE_STRIDE_SHIFT;
744 cci.pcci_unified = 1;
745 }
746 #ifdef XEN
747 if (cci.pcci_stride < ia64_d_cache_stride_shift)
748 ia64_d_cache_stride_shift = cci.pcci_stride;
749 #endif
750 line_size = 1 << cci.pcci_line_size;
751 if (line_size > max)
752 max = line_size;
753 if (!cci.pcci_unified) {
754 status = ia64_pal_cache_config_info(l,
755 /* cache_type (instruction)= */ 1,
756 &cci);
757 if (status != 0) {
758 printk(KERN_ERR
759 "%s: ia64_pal_cache_config_info(l=%lu, 1) failed (status=%ld)\n",
760 __FUNCTION__, l, status);
761 /* The safest setup for "flush_icache_range()" */
762 cci.pcci_stride = I_CACHE_STRIDE_SHIFT;
763 }
764 }
765 if (cci.pcci_stride < ia64_i_cache_stride_shift)
766 ia64_i_cache_stride_shift = cci.pcci_stride;
767 }
768 out:
769 if (max > ia64_max_cacheline_size)
770 ia64_max_cacheline_size = max;
771 #ifdef XEN
772 if (ia64_d_cache_stride_shift > ia64_i_cache_stride_shift)
773 ia64_d_cache_stride_shift = ia64_i_cache_stride_shift;
774 #endif
776 }
778 /*
779 * cpu_init() initializes state that is per-CPU. This function acts
780 * as a 'CPU state barrier', nothing should get across.
781 */
782 void
783 cpu_init (void)
784 {
785 extern void __devinit ia64_mmu_init (void *);
786 unsigned long num_phys_stacked;
787 #ifndef XEN
788 pal_vm_info_2_u_t vmi;
789 unsigned int max_ctx;
790 #endif
791 struct cpuinfo_ia64 *cpu_info;
792 void *cpu_data;
794 cpu_data = per_cpu_init();
796 #ifdef XEN
797 printf ("cpu_init: current=%p, current->domain->arch.mm=%p\n",
798 current, current->domain->arch.mm);
799 #endif
801 /*
802 * We set ar.k3 so that assembly code in MCA handler can compute
803 * physical addresses of per cpu variables with a simple:
804 * phys = ar.k3 + &per_cpu_var
805 */
806 ia64_set_kr(IA64_KR_PER_CPU_DATA,
807 ia64_tpa(cpu_data) - (long) __per_cpu_start);
809 get_max_cacheline_size();
811 /*
812 * We can't pass "local_cpu_data" to identify_cpu() because we haven't called
813 * ia64_mmu_init() yet. And we can't call ia64_mmu_init() first because it
814 * depends on the data returned by identify_cpu(). We break the dependency by
815 * accessing cpu_data() through the canonical per-CPU address.
816 */
817 cpu_info = cpu_data + ((char *) &__ia64_per_cpu_var(cpu_info) - __per_cpu_start);
818 identify_cpu(cpu_info);
820 #ifdef CONFIG_MCKINLEY
821 {
822 # define FEATURE_SET 16
823 struct ia64_pal_retval iprv;
825 if (cpu_info->family == 0x1f) {
826 PAL_CALL_PHYS(iprv, PAL_PROC_GET_FEATURES, 0, FEATURE_SET, 0);
827 if ((iprv.status == 0) && (iprv.v0 & 0x80) && (iprv.v2 & 0x80))
828 PAL_CALL_PHYS(iprv, PAL_PROC_SET_FEATURES,
829 (iprv.v1 | 0x80), FEATURE_SET, 0);
830 }
831 }
832 #endif
834 /* Clear the stack memory reserved for pt_regs: */
835 memset(ia64_task_regs(current), 0, sizeof(struct pt_regs));
837 ia64_set_kr(IA64_KR_FPU_OWNER, 0);
839 /*
840 * Initialize the page-table base register to a global
841 * directory with all zeroes. This ensure that we can handle
842 * TLB-misses to user address-space even before we created the
843 * first user address-space. This may happen, e.g., due to
844 * aggressive use of lfetch.fault.
845 */
846 ia64_set_kr(IA64_KR_PT_BASE, __pa(ia64_imva(empty_zero_page)));
848 /*
849 * Initialize default control register to defer speculative faults except
850 * for those arising from TLB misses, which are not deferred. The
851 * kernel MUST NOT depend on a particular setting of these bits (in other words,
852 * the kernel must have recovery code for all speculative accesses). Turn on
853 * dcr.lc as per recommendation by the architecture team. Most IA-32 apps
854 * shouldn't be affected by this (moral: keep your ia32 locks aligned and you'll
855 * be fine).
856 */
857 #ifdef XEN
858 ia64_setreg(_IA64_REG_CR_DCR, ( IA64_DCR_DP | IA64_DCR_DK | IA64_DCR_DX | IA64_DCR_DR
859 | IA64_DCR_PP | IA64_DCR_DA | IA64_DCR_DD | IA64_DCR_LC));
860 #else
861 ia64_setreg(_IA64_REG_CR_DCR, ( IA64_DCR_DP | IA64_DCR_DK | IA64_DCR_DX | IA64_DCR_DR
862 | IA64_DCR_DA | IA64_DCR_DD | IA64_DCR_LC));
863 #endif
864 #ifndef XEN
865 atomic_inc(&init_mm.mm_count);
866 current->active_mm = &init_mm;
867 #endif
868 #ifdef XEN
869 if (current->domain->arch.mm)
870 #else
871 if (current->mm)
872 #endif
873 BUG();
875 #ifdef XEN
876 ia64_fph_enable();
877 __ia64_init_fpu();
878 #endif
880 ia64_mmu_init(ia64_imva(cpu_data));
881 ia64_mca_cpu_init(ia64_imva(cpu_data));
883 #ifdef CONFIG_IA32_SUPPORT
884 ia32_cpu_init();
885 #endif
887 /* Clear ITC to eliminiate sched_clock() overflows in human time. */
888 ia64_set_itc(0);
890 /* disable all local interrupt sources: */
891 ia64_set_itv(1 << 16);
892 ia64_set_lrr0(1 << 16);
893 ia64_set_lrr1(1 << 16);
894 ia64_setreg(_IA64_REG_CR_PMV, 1 << 16);
895 ia64_setreg(_IA64_REG_CR_CMCV, 1 << 16);
897 /* clear TPR & XTP to enable all interrupt classes: */
898 ia64_setreg(_IA64_REG_CR_TPR, 0);
899 #ifdef CONFIG_SMP
900 normal_xtp();
901 #endif
903 #ifndef XEN
904 /* set ia64_ctx.max_rid to the maximum RID that is supported by all CPUs: */
905 if (ia64_pal_vm_summary(NULL, &vmi) == 0)
906 max_ctx = (1U << (vmi.pal_vm_info_2_s.rid_size - 3)) - 1;
907 else {
908 printk(KERN_WARNING "cpu_init: PAL VM summary failed, assuming 18 RID bits\n");
909 max_ctx = (1U << 15) - 1; /* use architected minimum */
910 }
911 while (max_ctx < ia64_ctx.max_ctx) {
912 unsigned int old = ia64_ctx.max_ctx;
913 if (cmpxchg(&ia64_ctx.max_ctx, old, max_ctx) == old)
914 break;
915 }
916 #endif
918 if (ia64_pal_rse_info(&num_phys_stacked, NULL) != 0) {
919 printk(KERN_WARNING "cpu_init: PAL RSE info failed; assuming 96 physical "
920 "stacked regs\n");
921 num_phys_stacked = 96;
922 }
923 /* size of physical stacked register partition plus 8 bytes: */
924 __get_cpu_var(ia64_phys_stacked_size_p8) = num_phys_stacked*8 + 8;
925 platform_cpu_init();
926 #ifndef XEN
927 pm_idle = default_idle;
928 #endif
930 #ifdef XEN
931 /* surrender usage of kernel registers to domain, use percpu area instead */
932 __get_cpu_var(cpu_kr)._kr[IA64_KR_IO_BASE] = ia64_get_kr(IA64_KR_IO_BASE);
933 __get_cpu_var(cpu_kr)._kr[IA64_KR_PER_CPU_DATA] = ia64_get_kr(IA64_KR_PER_CPU_DATA);
934 __get_cpu_var(cpu_kr)._kr[IA64_KR_CURRENT_STACK] = ia64_get_kr(IA64_KR_CURRENT_STACK);
935 __get_cpu_var(cpu_kr)._kr[IA64_KR_FPU_OWNER] = ia64_get_kr(IA64_KR_FPU_OWNER);
936 __get_cpu_var(cpu_kr)._kr[IA64_KR_CURRENT] = ia64_get_kr(IA64_KR_CURRENT);
937 __get_cpu_var(cpu_kr)._kr[IA64_KR_PT_BASE] = ia64_get_kr(IA64_KR_PT_BASE);
938 #endif
939 }
941 #ifndef XEN
942 void
943 check_bugs (void)
944 {
945 ia64_patch_mckinley_e9((unsigned long) __start___mckinley_e9_bundles,
946 (unsigned long) __end___mckinley_e9_bundles);
947 }
948 #endif