ia64/xen-unstable

view xen/arch/ia64/linux-xen/head.S @ 9770:ced37bea0647

[IA64] FPH enabling + cleanup

Move contents of switch_to macro from xensystem.h to context_switch function.
Initialize FPU on all processors. FPH is always enabled in Xen.
Speed up context-switch (a little bit!) by not enabling/disabling FPH.
Cleanup (unused function/variablesi/fields, debug printf...)
vmx_ia64_switch_to removed (was unused).

Signed-off-by: Tristan Gingold <tristan.gingold@bull.net>
author awilliam@xenbuild.aw
date Tue Apr 25 22:35:41 2006 -0600 (2006-04-25)
parents bdb08c9ef3d1
children 4174856876f9
line source
1 /*
2 * Here is where the ball gets rolling as far as the kernel is concerned.
3 * When control is transferred to _start, the bootload has already
4 * loaded us to the correct address. All that's left to do here is
5 * to set up the kernel's global pointer and jump to the kernel
6 * entry point.
7 *
8 * Copyright (C) 1998-2001, 2003, 2005 Hewlett-Packard Co
9 * David Mosberger-Tang <davidm@hpl.hp.com>
10 * Stephane Eranian <eranian@hpl.hp.com>
11 * Copyright (C) 1999 VA Linux Systems
12 * Copyright (C) 1999 Walt Drummond <drummond@valinux.com>
13 * Copyright (C) 1999 Intel Corp.
14 * Copyright (C) 1999 Asit Mallick <Asit.K.Mallick@intel.com>
15 * Copyright (C) 1999 Don Dugger <Don.Dugger@intel.com>
16 * Copyright (C) 2002 Fenghua Yu <fenghua.yu@intel.com>
17 * -Optimize __ia64_save_fpu() and __ia64_load_fpu() for Itanium 2.
18 * Copyright (C) 2004 Ashok Raj <ashok.raj@intel.com>
19 * Support for CPU Hotplug
20 */
22 #include <linux/config.h>
24 #include <asm/asmmacro.h>
25 #include <asm/fpu.h>
26 #include <asm/kregs.h>
27 #include <asm/mmu_context.h>
28 #include <asm/offsets.h>
29 #include <asm/pal.h>
30 #include <asm/pgtable.h>
31 #include <asm/processor.h>
32 #include <asm/ptrace.h>
33 #include <asm/system.h>
34 #include <asm/mca_asm.h>
36 #ifdef CONFIG_HOTPLUG_CPU
37 #define SAL_PSR_BITS_TO_SET \
38 (IA64_PSR_AC | IA64_PSR_BN | IA64_PSR_MFH | IA64_PSR_MFL)
40 #define SAVE_FROM_REG(src, ptr, dest) \
41 mov dest=src;; \
42 st8 [ptr]=dest,0x08
44 #define RESTORE_REG(reg, ptr, _tmp) \
45 ld8 _tmp=[ptr],0x08;; \
46 mov reg=_tmp
48 #define SAVE_BREAK_REGS(ptr, _idx, _breg, _dest)\
49 mov ar.lc=IA64_NUM_DBG_REGS-1;; \
50 mov _idx=0;; \
51 1: \
52 SAVE_FROM_REG(_breg[_idx], ptr, _dest);; \
53 add _idx=1,_idx;; \
54 br.cloop.sptk.many 1b
56 #define RESTORE_BREAK_REGS(ptr, _idx, _breg, _tmp, _lbl)\
57 mov ar.lc=IA64_NUM_DBG_REGS-1;; \
58 mov _idx=0;; \
59 _lbl: RESTORE_REG(_breg[_idx], ptr, _tmp);; \
60 add _idx=1, _idx;; \
61 br.cloop.sptk.many _lbl
63 #define SAVE_ONE_RR(num, _reg, _tmp) \
64 movl _tmp=(num<<61);; \
65 mov _reg=rr[_tmp]
67 #define SAVE_REGION_REGS(_tmp, _r0, _r1, _r2, _r3, _r4, _r5, _r6, _r7) \
68 SAVE_ONE_RR(0,_r0, _tmp);; \
69 SAVE_ONE_RR(1,_r1, _tmp);; \
70 SAVE_ONE_RR(2,_r2, _tmp);; \
71 SAVE_ONE_RR(3,_r3, _tmp);; \
72 SAVE_ONE_RR(4,_r4, _tmp);; \
73 SAVE_ONE_RR(5,_r5, _tmp);; \
74 SAVE_ONE_RR(6,_r6, _tmp);; \
75 SAVE_ONE_RR(7,_r7, _tmp);;
77 #define STORE_REGION_REGS(ptr, _r0, _r1, _r2, _r3, _r4, _r5, _r6, _r7) \
78 st8 [ptr]=_r0, 8;; \
79 st8 [ptr]=_r1, 8;; \
80 st8 [ptr]=_r2, 8;; \
81 st8 [ptr]=_r3, 8;; \
82 st8 [ptr]=_r4, 8;; \
83 st8 [ptr]=_r5, 8;; \
84 st8 [ptr]=_r6, 8;; \
85 st8 [ptr]=_r7, 8;;
87 #define RESTORE_REGION_REGS(ptr, _idx1, _idx2, _tmp) \
88 mov ar.lc=0x08-1;; \
89 movl _idx1=0x00;; \
90 RestRR: \
91 dep.z _idx2=_idx1,61,3;; \
92 ld8 _tmp=[ptr],8;; \
93 mov rr[_idx2]=_tmp;; \
94 srlz.d;; \
95 add _idx1=1,_idx1;; \
96 br.cloop.sptk.few RestRR
98 #define SET_AREA_FOR_BOOTING_CPU(reg1, reg2) \
99 movl reg1=sal_state_for_booting_cpu;; \
100 ld8 reg2=[reg1];;
102 /*
103 * Adjust region registers saved before starting to save
104 * break regs and rest of the states that need to be preserved.
105 */
106 #define SAL_TO_OS_BOOT_HANDOFF_STATE_SAVE(_reg1,_reg2,_pred) \
107 SAVE_FROM_REG(b0,_reg1,_reg2);; \
108 SAVE_FROM_REG(b1,_reg1,_reg2);; \
109 SAVE_FROM_REG(b2,_reg1,_reg2);; \
110 SAVE_FROM_REG(b3,_reg1,_reg2);; \
111 SAVE_FROM_REG(b4,_reg1,_reg2);; \
112 SAVE_FROM_REG(b5,_reg1,_reg2);; \
113 st8 [_reg1]=r1,0x08;; \
114 st8 [_reg1]=r12,0x08;; \
115 st8 [_reg1]=r13,0x08;; \
116 SAVE_FROM_REG(ar.fpsr,_reg1,_reg2);; \
117 SAVE_FROM_REG(ar.pfs,_reg1,_reg2);; \
118 SAVE_FROM_REG(ar.rnat,_reg1,_reg2);; \
119 SAVE_FROM_REG(ar.unat,_reg1,_reg2);; \
120 SAVE_FROM_REG(ar.bspstore,_reg1,_reg2);; \
121 SAVE_FROM_REG(cr.dcr,_reg1,_reg2);; \
122 SAVE_FROM_REG(cr.iva,_reg1,_reg2);; \
123 SAVE_FROM_REG(cr.pta,_reg1,_reg2);; \
124 SAVE_FROM_REG(cr.itv,_reg1,_reg2);; \
125 SAVE_FROM_REG(cr.pmv,_reg1,_reg2);; \
126 SAVE_FROM_REG(cr.cmcv,_reg1,_reg2);; \
127 SAVE_FROM_REG(cr.lrr0,_reg1,_reg2);; \
128 SAVE_FROM_REG(cr.lrr1,_reg1,_reg2);; \
129 st8 [_reg1]=r4,0x08;; \
130 st8 [_reg1]=r5,0x08;; \
131 st8 [_reg1]=r6,0x08;; \
132 st8 [_reg1]=r7,0x08;; \
133 st8 [_reg1]=_pred,0x08;; \
134 SAVE_FROM_REG(ar.lc, _reg1, _reg2);; \
135 stf.spill.nta [_reg1]=f2,16;; \
136 stf.spill.nta [_reg1]=f3,16;; \
137 stf.spill.nta [_reg1]=f4,16;; \
138 stf.spill.nta [_reg1]=f5,16;; \
139 stf.spill.nta [_reg1]=f16,16;; \
140 stf.spill.nta [_reg1]=f17,16;; \
141 stf.spill.nta [_reg1]=f18,16;; \
142 stf.spill.nta [_reg1]=f19,16;; \
143 stf.spill.nta [_reg1]=f20,16;; \
144 stf.spill.nta [_reg1]=f21,16;; \
145 stf.spill.nta [_reg1]=f22,16;; \
146 stf.spill.nta [_reg1]=f23,16;; \
147 stf.spill.nta [_reg1]=f24,16;; \
148 stf.spill.nta [_reg1]=f25,16;; \
149 stf.spill.nta [_reg1]=f26,16;; \
150 stf.spill.nta [_reg1]=f27,16;; \
151 stf.spill.nta [_reg1]=f28,16;; \
152 stf.spill.nta [_reg1]=f29,16;; \
153 stf.spill.nta [_reg1]=f30,16;; \
154 stf.spill.nta [_reg1]=f31,16;;
156 #else
157 #define SET_AREA_FOR_BOOTING_CPU(a1, a2)
158 #define SAL_TO_OS_BOOT_HANDOFF_STATE_SAVE(a1,a2, a3)
159 #define SAVE_REGION_REGS(_tmp, _r0, _r1, _r2, _r3, _r4, _r5, _r6, _r7)
160 #define STORE_REGION_REGS(ptr, _r0, _r1, _r2, _r3, _r4, _r5, _r6, _r7)
161 #endif
163 #ifdef XEN
164 #define SET_ONE_RR(num, pgsize, _tmp1, _tmp2, vhpt) \
165 movl _tmp1=(num << 61);; \
166 movl _tmp2=((ia64_rid(IA64_REGION_ID_KERNEL, (num<<61)) << 8) | (pgsize << 2) | vhpt);; \
167 mov rr[_tmp1]=_tmp2
168 #else
169 #define SET_ONE_RR(num, pgsize, _tmp1, _tmp2, vhpt) \
170 movl _tmp1=(num << 61);; \
171 mov _tmp2=((ia64_rid(IA64_REGION_ID_KERNEL, (num<<61)) << 8) | (pgsize << 2) | vhpt);; \
172 mov rr[_tmp1]=_tmp2
173 #endif
175 .section __special_page_section,"ax"
177 .global empty_zero_page
178 empty_zero_page:
179 .skip PAGE_SIZE
181 #ifndef XEN
182 .global swapper_pg_dir
183 swapper_pg_dir:
184 .skip PAGE_SIZE
185 #endif
187 #if defined(XEN) && defined(CONFIG_VIRTUAL_FRAME_TABLE)
188 .global frametable_pg_dir
189 frametable_pg_dir:
190 .skip PAGE_SIZE
191 #endif
193 .rodata
194 halt_msg:
195 stringz "Halting kernel\n"
197 .text
199 .global start_ap
201 /*
202 * Start the kernel. When the bootloader passes control to _start(), r28
203 * points to the address of the boot parameter area. Execution reaches
204 * here in physical mode.
205 */
206 GLOBAL_ENTRY(_start)
207 start_ap:
208 .prologue
209 .save rp, r0 // terminate unwind chain with a NULL rp
210 .body
212 rsm psr.i | psr.ic
213 ;;
214 srlz.i
215 ;;
216 /*
217 * Save the region registers, predicate before they get clobbered
218 */
219 SAVE_REGION_REGS(r2, r8,r9,r10,r11,r12,r13,r14,r15);
220 mov r25=pr;;
222 /*
223 * Initialize kernel region registers:
224 * rr[0]: VHPT enabled, page size = PAGE_SHIFT
225 * rr[1]: VHPT enabled, page size = PAGE_SHIFT
226 * rr[2]: VHPT enabled, page size = PAGE_SHIFT
227 * rr[3]: VHPT enabled, page size = PAGE_SHIFT
228 * rr[4]: VHPT enabled, page size = PAGE_SHIFT
229 * rr[5]: VHPT enabled, page size = PAGE_SHIFT
230 * rr[6]: VHPT disabled, page size = IA64_GRANULE_SHIFT
231 * rr[7]: VHPT disabled, page size = IA64_GRANULE_SHIFT
232 * We initialize all of them to prevent inadvertently assuming
233 * something about the state of address translation early in boot.
234 */
235 SET_ONE_RR(0, PAGE_SHIFT, r2, r16, 1);;
236 SET_ONE_RR(1, PAGE_SHIFT, r2, r16, 1);;
237 SET_ONE_RR(2, PAGE_SHIFT, r2, r16, 1);;
238 SET_ONE_RR(3, PAGE_SHIFT, r2, r16, 1);;
239 SET_ONE_RR(4, PAGE_SHIFT, r2, r16, 1);;
240 SET_ONE_RR(5, PAGE_SHIFT, r2, r16, 1);;
241 SET_ONE_RR(6, IA64_GRANULE_SHIFT, r2, r16, 0);;
242 SET_ONE_RR(7, IA64_GRANULE_SHIFT, r2, r16, 0);;
243 /*
244 * Now pin mappings into the TLB for kernel text and data
245 */
246 mov r18=KERNEL_TR_PAGE_SHIFT<<2
247 movl r17=KERNEL_START
248 ;;
249 mov cr.itir=r18
250 mov cr.ifa=r17
251 mov r16=IA64_TR_KERNEL
252 mov r3=ip
253 movl r18=PAGE_KERNEL
254 ;;
255 dep r2=0,r3,0,KERNEL_TR_PAGE_SHIFT
256 ;;
257 or r18=r2,r18
258 ;;
259 srlz.i
260 ;;
261 itr.i itr[r16]=r18
262 ;;
263 itr.d dtr[r16]=r18
264 ;;
265 srlz.i
267 /*
268 * Switch into virtual mode:
269 */
270 #if defined(XEN) && defined(VALIDATE_VT)
271 movl r16=(IA64_PSR_IT|IA64_PSR_IC|IA64_PSR_DT|IA64_PSR_RT|IA64_PSR_DFH\
272 |IA64_PSR_DI)
273 #else
274 movl r16=(IA64_PSR_IT|IA64_PSR_IC|IA64_PSR_DT|IA64_PSR_RT|IA64_PSR_DFH|IA64_PSR_BN \
275 |IA64_PSR_DI)
276 #endif
277 ;;
278 mov cr.ipsr=r16
279 movl r17=1f
280 ;;
281 mov cr.iip=r17
282 mov cr.ifs=r0
283 ;;
284 rfi
285 ;;
286 1: // now we are in virtual mode
288 SET_AREA_FOR_BOOTING_CPU(r2, r16);
290 STORE_REGION_REGS(r16, r8,r9,r10,r11,r12,r13,r14,r15);
291 SAL_TO_OS_BOOT_HANDOFF_STATE_SAVE(r16,r17,r25)
292 ;;
294 // set IVT entry point---can't access I/O ports without it
295 #if defined(XEN) && defined(VALIDATE_VT)
296 movl r3=vmx_ia64_ivt
297 #else
298 movl r3=ia64_ivt
299 #endif
300 ;;
301 mov cr.iva=r3
302 movl r2=FPSR_DEFAULT
303 ;;
304 srlz.i
305 movl gp=__gp
307 mov ar.fpsr=r2
308 ;;
310 #define isAP p2 // are we an Application Processor?
311 #define isBP p3 // are we the Bootstrap Processor?
313 #ifdef CONFIG_SMP
314 /*
315 * Find the init_task for the currently booting CPU. At poweron, and in
316 * UP mode, task_for_booting_cpu is NULL.
317 */
318 movl r3=task_for_booting_cpu
319 ;;
320 ld8 r3=[r3]
321 movl r2=init_task
322 ;;
323 cmp.eq isBP,isAP=r3,r0
324 ;;
325 (isAP) mov r2=r3
326 #else
327 movl r2=init_task
328 cmp.eq isBP,isAP=r0,r0
329 #endif
330 ;;
331 tpa r3=r2 // r3 == phys addr of task struct
332 mov r16=-1
333 (isBP) br.cond.dpnt .load_current // BP stack is on region 5 --- no need to map it
335 #ifndef XEN
336 // XEN: stack is allocated in xenheap, which is currently always
337 // mapped.
338 // load mapping for stack (virtaddr in r2, physaddr in r3)
339 rsm psr.ic
340 movl r17=PAGE_KERNEL
341 ;;
342 srlz.d
343 dep r18=0,r3,0,12
344 ;;
345 or r18=r17,r18
346 #ifdef XEN
347 dep r2=-1,r3,60,4 // IMVA of task
348 #else
349 dep r2=-1,r3,61,3 // IMVA of task
350 #endif
351 ;;
352 mov r17=rr[r2]
353 shr.u r16=r3,IA64_GRANULE_SHIFT
354 ;;
355 dep r17=0,r17,8,24
356 ;;
357 mov cr.itir=r17
358 mov cr.ifa=r2
360 mov r19=IA64_TR_CURRENT_STACK
361 ;;
362 itr.d dtr[r19]=r18
363 ;;
364 ssm psr.ic
365 srlz.d
366 ;;
367 #endif
369 .load_current:
370 // load the "current" pointer (r13) and ar.k6 with the current task
371 #if defined(XEN) && defined(VALIDATE_VT)
372 mov r21=r2
373 ;;
374 bsw.1
375 ;;
376 #else
377 mov IA64_KR(CURRENT)=r2 // virtual address
378 mov IA64_KR(CURRENT_STACK)=r16
379 #endif
380 mov r13=r2
381 /*
382 * Reserve space at the top of the stack for "struct pt_regs". Kernel
383 * threads don't store interesting values in that structure, but the space
384 * still needs to be there because time-critical stuff such as the context
385 * switching can be implemented more efficiently (for example, __switch_to()
386 * always sets the psr.dfh bit of the task it is switching to).
387 */
389 addl r12=IA64_STK_OFFSET-IA64_PT_REGS_SIZE-16,r2
390 addl r2=IA64_RBS_OFFSET,r2 // initialize the RSE
391 mov ar.rsc=0 // place RSE in enforced lazy mode
392 ;;
393 loadrs // clear the dirty partition
394 ;;
395 mov ar.bspstore=r2 // establish the new RSE stack
396 ;;
397 mov ar.rsc=0x3 // place RSE in eager mode
399 #ifdef XEN
400 (isBP) dep r28=-1,r28,60,4 // make address virtual
401 #else
402 (isBP) dep r28=-1,r28,61,3 // make address virtual
403 #endif
404 (isBP) movl r2=ia64_boot_param
405 ;;
406 (isBP) st8 [r2]=r28 // save the address of the boot param area passed by the bootloader
408 #ifdef CONFIG_SMP
409 (isAP) br.call.sptk.many rp=start_secondary
410 .ret0:
411 (isAP) br.cond.sptk self
412 #endif
414 // This is executed by the bootstrap processor (bsp) only:
416 #ifdef CONFIG_IA64_FW_EMU
417 // initialize PAL & SAL emulator:
418 br.call.sptk.many rp=sys_fw_init
419 .ret1:
420 #endif
421 br.call.sptk.many rp=start_kernel
422 .ret2: addl r3=@ltoff(halt_msg),gp
423 ;;
424 alloc r2=ar.pfs,8,0,2,0
425 ;;
426 ld8 out0=[r3]
427 br.call.sptk.many b0=console_print
429 self: hint @pause
430 #ifdef XEN
431 ;;
432 br.sptk.many self // endless loop
433 ;;
434 #else
435 br.sptk.many self // endless loop
436 #endif
437 END(_start)
439 GLOBAL_ENTRY(ia64_save_debug_regs)
440 alloc r16=ar.pfs,1,0,0,0
441 mov r20=ar.lc // preserve ar.lc
442 mov ar.lc=IA64_NUM_DBG_REGS-1
443 mov r18=0
444 add r19=IA64_NUM_DBG_REGS*8,in0
445 ;;
446 1: mov r16=dbr[r18]
447 #ifdef CONFIG_ITANIUM
448 ;;
449 srlz.d
450 #endif
451 mov r17=ibr[r18]
452 add r18=1,r18
453 ;;
454 st8.nta [in0]=r16,8
455 st8.nta [r19]=r17,8
456 br.cloop.sptk.many 1b
457 ;;
458 mov ar.lc=r20 // restore ar.lc
459 br.ret.sptk.many rp
460 END(ia64_save_debug_regs)
462 GLOBAL_ENTRY(ia64_load_debug_regs)
463 alloc r16=ar.pfs,1,0,0,0
464 lfetch.nta [in0]
465 mov r20=ar.lc // preserve ar.lc
466 add r19=IA64_NUM_DBG_REGS*8,in0
467 mov ar.lc=IA64_NUM_DBG_REGS-1
468 mov r18=-1
469 ;;
470 1: ld8.nta r16=[in0],8
471 ld8.nta r17=[r19],8
472 add r18=1,r18
473 ;;
474 mov dbr[r18]=r16
475 #ifdef CONFIG_ITANIUM
476 ;;
477 srlz.d // Errata 132 (NoFix status)
478 #endif
479 mov ibr[r18]=r17
480 br.cloop.sptk.many 1b
481 ;;
482 mov ar.lc=r20 // restore ar.lc
483 br.ret.sptk.many rp
484 END(ia64_load_debug_regs)
486 GLOBAL_ENTRY(__ia64_save_fpu)
487 alloc r2=ar.pfs,1,4,0,0
488 adds loc0=96*16-16,in0
489 adds loc1=96*16-16-128,in0
490 ;;
491 stf.spill.nta [loc0]=f127,-256
492 stf.spill.nta [loc1]=f119,-256
493 ;;
494 stf.spill.nta [loc0]=f111,-256
495 stf.spill.nta [loc1]=f103,-256
496 ;;
497 stf.spill.nta [loc0]=f95,-256
498 stf.spill.nta [loc1]=f87,-256
499 ;;
500 stf.spill.nta [loc0]=f79,-256
501 stf.spill.nta [loc1]=f71,-256
502 ;;
503 stf.spill.nta [loc0]=f63,-256
504 stf.spill.nta [loc1]=f55,-256
505 adds loc2=96*16-32,in0
506 ;;
507 stf.spill.nta [loc0]=f47,-256
508 stf.spill.nta [loc1]=f39,-256
509 adds loc3=96*16-32-128,in0
510 ;;
511 stf.spill.nta [loc2]=f126,-256
512 stf.spill.nta [loc3]=f118,-256
513 ;;
514 stf.spill.nta [loc2]=f110,-256
515 stf.spill.nta [loc3]=f102,-256
516 ;;
517 stf.spill.nta [loc2]=f94,-256
518 stf.spill.nta [loc3]=f86,-256
519 ;;
520 stf.spill.nta [loc2]=f78,-256
521 stf.spill.nta [loc3]=f70,-256
522 ;;
523 stf.spill.nta [loc2]=f62,-256
524 stf.spill.nta [loc3]=f54,-256
525 adds loc0=96*16-48,in0
526 ;;
527 stf.spill.nta [loc2]=f46,-256
528 stf.spill.nta [loc3]=f38,-256
529 adds loc1=96*16-48-128,in0
530 ;;
531 stf.spill.nta [loc0]=f125,-256
532 stf.spill.nta [loc1]=f117,-256
533 ;;
534 stf.spill.nta [loc0]=f109,-256
535 stf.spill.nta [loc1]=f101,-256
536 ;;
537 stf.spill.nta [loc0]=f93,-256
538 stf.spill.nta [loc1]=f85,-256
539 ;;
540 stf.spill.nta [loc0]=f77,-256
541 stf.spill.nta [loc1]=f69,-256
542 ;;
543 stf.spill.nta [loc0]=f61,-256
544 stf.spill.nta [loc1]=f53,-256
545 adds loc2=96*16-64,in0
546 ;;
547 stf.spill.nta [loc0]=f45,-256
548 stf.spill.nta [loc1]=f37,-256
549 adds loc3=96*16-64-128,in0
550 ;;
551 stf.spill.nta [loc2]=f124,-256
552 stf.spill.nta [loc3]=f116,-256
553 ;;
554 stf.spill.nta [loc2]=f108,-256
555 stf.spill.nta [loc3]=f100,-256
556 ;;
557 stf.spill.nta [loc2]=f92,-256
558 stf.spill.nta [loc3]=f84,-256
559 ;;
560 stf.spill.nta [loc2]=f76,-256
561 stf.spill.nta [loc3]=f68,-256
562 ;;
563 stf.spill.nta [loc2]=f60,-256
564 stf.spill.nta [loc3]=f52,-256
565 adds loc0=96*16-80,in0
566 ;;
567 stf.spill.nta [loc2]=f44,-256
568 stf.spill.nta [loc3]=f36,-256
569 adds loc1=96*16-80-128,in0
570 ;;
571 stf.spill.nta [loc0]=f123,-256
572 stf.spill.nta [loc1]=f115,-256
573 ;;
574 stf.spill.nta [loc0]=f107,-256
575 stf.spill.nta [loc1]=f99,-256
576 ;;
577 stf.spill.nta [loc0]=f91,-256
578 stf.spill.nta [loc1]=f83,-256
579 ;;
580 stf.spill.nta [loc0]=f75,-256
581 stf.spill.nta [loc1]=f67,-256
582 ;;
583 stf.spill.nta [loc0]=f59,-256
584 stf.spill.nta [loc1]=f51,-256
585 adds loc2=96*16-96,in0
586 ;;
587 stf.spill.nta [loc0]=f43,-256
588 stf.spill.nta [loc1]=f35,-256
589 adds loc3=96*16-96-128,in0
590 ;;
591 stf.spill.nta [loc2]=f122,-256
592 stf.spill.nta [loc3]=f114,-256
593 ;;
594 stf.spill.nta [loc2]=f106,-256
595 stf.spill.nta [loc3]=f98,-256
596 ;;
597 stf.spill.nta [loc2]=f90,-256
598 stf.spill.nta [loc3]=f82,-256
599 ;;
600 stf.spill.nta [loc2]=f74,-256
601 stf.spill.nta [loc3]=f66,-256
602 ;;
603 stf.spill.nta [loc2]=f58,-256
604 stf.spill.nta [loc3]=f50,-256
605 adds loc0=96*16-112,in0
606 ;;
607 stf.spill.nta [loc2]=f42,-256
608 stf.spill.nta [loc3]=f34,-256
609 adds loc1=96*16-112-128,in0
610 ;;
611 stf.spill.nta [loc0]=f121,-256
612 stf.spill.nta [loc1]=f113,-256
613 ;;
614 stf.spill.nta [loc0]=f105,-256
615 stf.spill.nta [loc1]=f97,-256
616 ;;
617 stf.spill.nta [loc0]=f89,-256
618 stf.spill.nta [loc1]=f81,-256
619 ;;
620 stf.spill.nta [loc0]=f73,-256
621 stf.spill.nta [loc1]=f65,-256
622 ;;
623 stf.spill.nta [loc0]=f57,-256
624 stf.spill.nta [loc1]=f49,-256
625 adds loc2=96*16-128,in0
626 ;;
627 stf.spill.nta [loc0]=f41,-256
628 stf.spill.nta [loc1]=f33,-256
629 adds loc3=96*16-128-128,in0
630 ;;
631 stf.spill.nta [loc2]=f120,-256
632 stf.spill.nta [loc3]=f112,-256
633 ;;
634 stf.spill.nta [loc2]=f104,-256
635 stf.spill.nta [loc3]=f96,-256
636 ;;
637 stf.spill.nta [loc2]=f88,-256
638 stf.spill.nta [loc3]=f80,-256
639 ;;
640 stf.spill.nta [loc2]=f72,-256
641 stf.spill.nta [loc3]=f64,-256
642 ;;
643 stf.spill.nta [loc2]=f56,-256
644 stf.spill.nta [loc3]=f48,-256
645 ;;
646 stf.spill.nta [loc2]=f40
647 stf.spill.nta [loc3]=f32
648 br.ret.sptk.many rp
649 END(__ia64_save_fpu)
651 GLOBAL_ENTRY(__ia64_load_fpu)
652 alloc r2=ar.pfs,1,2,0,0
653 adds r3=128,in0
654 adds r14=256,in0
655 adds r15=384,in0
656 mov loc0=512
657 mov loc1=-1024+16
658 ;;
659 ldf.fill.nta f32=[in0],loc0
660 ldf.fill.nta f40=[ r3],loc0
661 ldf.fill.nta f48=[r14],loc0
662 ldf.fill.nta f56=[r15],loc0
663 ;;
664 ldf.fill.nta f64=[in0],loc0
665 ldf.fill.nta f72=[ r3],loc0
666 ldf.fill.nta f80=[r14],loc0
667 ldf.fill.nta f88=[r15],loc0
668 ;;
669 ldf.fill.nta f96=[in0],loc1
670 ldf.fill.nta f104=[ r3],loc1
671 ldf.fill.nta f112=[r14],loc1
672 ldf.fill.nta f120=[r15],loc1
673 ;;
674 ldf.fill.nta f33=[in0],loc0
675 ldf.fill.nta f41=[ r3],loc0
676 ldf.fill.nta f49=[r14],loc0
677 ldf.fill.nta f57=[r15],loc0
678 ;;
679 ldf.fill.nta f65=[in0],loc0
680 ldf.fill.nta f73=[ r3],loc0
681 ldf.fill.nta f81=[r14],loc0
682 ldf.fill.nta f89=[r15],loc0
683 ;;
684 ldf.fill.nta f97=[in0],loc1
685 ldf.fill.nta f105=[ r3],loc1
686 ldf.fill.nta f113=[r14],loc1
687 ldf.fill.nta f121=[r15],loc1
688 ;;
689 ldf.fill.nta f34=[in0],loc0
690 ldf.fill.nta f42=[ r3],loc0
691 ldf.fill.nta f50=[r14],loc0
692 ldf.fill.nta f58=[r15],loc0
693 ;;
694 ldf.fill.nta f66=[in0],loc0
695 ldf.fill.nta f74=[ r3],loc0
696 ldf.fill.nta f82=[r14],loc0
697 ldf.fill.nta f90=[r15],loc0
698 ;;
699 ldf.fill.nta f98=[in0],loc1
700 ldf.fill.nta f106=[ r3],loc1
701 ldf.fill.nta f114=[r14],loc1
702 ldf.fill.nta f122=[r15],loc1
703 ;;
704 ldf.fill.nta f35=[in0],loc0
705 ldf.fill.nta f43=[ r3],loc0
706 ldf.fill.nta f51=[r14],loc0
707 ldf.fill.nta f59=[r15],loc0
708 ;;
709 ldf.fill.nta f67=[in0],loc0
710 ldf.fill.nta f75=[ r3],loc0
711 ldf.fill.nta f83=[r14],loc0
712 ldf.fill.nta f91=[r15],loc0
713 ;;
714 ldf.fill.nta f99=[in0],loc1
715 ldf.fill.nta f107=[ r3],loc1
716 ldf.fill.nta f115=[r14],loc1
717 ldf.fill.nta f123=[r15],loc1
718 ;;
719 ldf.fill.nta f36=[in0],loc0
720 ldf.fill.nta f44=[ r3],loc0
721 ldf.fill.nta f52=[r14],loc0
722 ldf.fill.nta f60=[r15],loc0
723 ;;
724 ldf.fill.nta f68=[in0],loc0
725 ldf.fill.nta f76=[ r3],loc0
726 ldf.fill.nta f84=[r14],loc0
727 ldf.fill.nta f92=[r15],loc0
728 ;;
729 ldf.fill.nta f100=[in0],loc1
730 ldf.fill.nta f108=[ r3],loc1
731 ldf.fill.nta f116=[r14],loc1
732 ldf.fill.nta f124=[r15],loc1
733 ;;
734 ldf.fill.nta f37=[in0],loc0
735 ldf.fill.nta f45=[ r3],loc0
736 ldf.fill.nta f53=[r14],loc0
737 ldf.fill.nta f61=[r15],loc0
738 ;;
739 ldf.fill.nta f69=[in0],loc0
740 ldf.fill.nta f77=[ r3],loc0
741 ldf.fill.nta f85=[r14],loc0
742 ldf.fill.nta f93=[r15],loc0
743 ;;
744 ldf.fill.nta f101=[in0],loc1
745 ldf.fill.nta f109=[ r3],loc1
746 ldf.fill.nta f117=[r14],loc1
747 ldf.fill.nta f125=[r15],loc1
748 ;;
749 ldf.fill.nta f38 =[in0],loc0
750 ldf.fill.nta f46 =[ r3],loc0
751 ldf.fill.nta f54 =[r14],loc0
752 ldf.fill.nta f62 =[r15],loc0
753 ;;
754 ldf.fill.nta f70 =[in0],loc0
755 ldf.fill.nta f78 =[ r3],loc0
756 ldf.fill.nta f86 =[r14],loc0
757 ldf.fill.nta f94 =[r15],loc0
758 ;;
759 ldf.fill.nta f102=[in0],loc1
760 ldf.fill.nta f110=[ r3],loc1
761 ldf.fill.nta f118=[r14],loc1
762 ldf.fill.nta f126=[r15],loc1
763 ;;
764 ldf.fill.nta f39 =[in0],loc0
765 ldf.fill.nta f47 =[ r3],loc0
766 ldf.fill.nta f55 =[r14],loc0
767 ldf.fill.nta f63 =[r15],loc0
768 ;;
769 ldf.fill.nta f71 =[in0],loc0
770 ldf.fill.nta f79 =[ r3],loc0
771 ldf.fill.nta f87 =[r14],loc0
772 ldf.fill.nta f95 =[r15],loc0
773 ;;
774 ldf.fill.nta f103=[in0]
775 ldf.fill.nta f111=[ r3]
776 ldf.fill.nta f119=[r14]
777 ldf.fill.nta f127=[r15]
778 br.ret.sptk.many rp
779 END(__ia64_load_fpu)
781 GLOBAL_ENTRY(__ia64_init_fpu)
782 stf.spill [sp]=f0 // M3
783 mov f32=f0 // F
784 nop.b 0
786 ldfps f33,f34=[sp] // M0
787 ldfps f35,f36=[sp] // M1
788 mov f37=f0 // F
789 ;;
791 setf.s f38=r0 // M2
792 setf.s f39=r0 // M3
793 mov f40=f0 // F
795 ldfps f41,f42=[sp] // M0
796 ldfps f43,f44=[sp] // M1
797 mov f45=f0 // F
799 setf.s f46=r0 // M2
800 setf.s f47=r0 // M3
801 mov f48=f0 // F
803 ldfps f49,f50=[sp] // M0
804 ldfps f51,f52=[sp] // M1
805 mov f53=f0 // F
807 setf.s f54=r0 // M2
808 setf.s f55=r0 // M3
809 mov f56=f0 // F
811 ldfps f57,f58=[sp] // M0
812 ldfps f59,f60=[sp] // M1
813 mov f61=f0 // F
815 setf.s f62=r0 // M2
816 setf.s f63=r0 // M3
817 mov f64=f0 // F
819 ldfps f65,f66=[sp] // M0
820 ldfps f67,f68=[sp] // M1
821 mov f69=f0 // F
823 setf.s f70=r0 // M2
824 setf.s f71=r0 // M3
825 mov f72=f0 // F
827 ldfps f73,f74=[sp] // M0
828 ldfps f75,f76=[sp] // M1
829 mov f77=f0 // F
831 setf.s f78=r0 // M2
832 setf.s f79=r0 // M3
833 mov f80=f0 // F
835 ldfps f81,f82=[sp] // M0
836 ldfps f83,f84=[sp] // M1
837 mov f85=f0 // F
839 setf.s f86=r0 // M2
840 setf.s f87=r0 // M3
841 mov f88=f0 // F
843 /*
844 * When the instructions are cached, it would be faster to initialize
845 * the remaining registers with simply mov instructions (F-unit).
846 * This gets the time down to ~29 cycles. However, this would use up
847 * 33 bundles, whereas continuing with the above pattern yields
848 * 10 bundles and ~30 cycles.
849 */
851 ldfps f89,f90=[sp] // M0
852 ldfps f91,f92=[sp] // M1
853 mov f93=f0 // F
855 setf.s f94=r0 // M2
856 setf.s f95=r0 // M3
857 mov f96=f0 // F
859 ldfps f97,f98=[sp] // M0
860 ldfps f99,f100=[sp] // M1
861 mov f101=f0 // F
863 setf.s f102=r0 // M2
864 setf.s f103=r0 // M3
865 mov f104=f0 // F
867 ldfps f105,f106=[sp] // M0
868 ldfps f107,f108=[sp] // M1
869 mov f109=f0 // F
871 setf.s f110=r0 // M2
872 setf.s f111=r0 // M3
873 mov f112=f0 // F
875 ldfps f113,f114=[sp] // M0
876 ldfps f115,f116=[sp] // M1
877 mov f117=f0 // F
879 setf.s f118=r0 // M2
880 setf.s f119=r0 // M3
881 mov f120=f0 // F
883 ldfps f121,f122=[sp] // M0
884 ldfps f123,f124=[sp] // M1
885 mov f125=f0 // F
887 setf.s f126=r0 // M2
888 setf.s f127=r0 // M3
889 br.ret.sptk.many rp // F
890 END(__ia64_init_fpu)
892 /*
893 * Switch execution mode from virtual to physical
894 *
895 * Inputs:
896 * r16 = new psr to establish
897 * Output:
898 * r19 = old virtual address of ar.bsp
899 * r20 = old virtual address of sp
900 *
901 * Note: RSE must already be in enforced lazy mode
902 */
903 GLOBAL_ENTRY(ia64_switch_mode_phys)
904 {
905 alloc r2=ar.pfs,0,0,0,0
906 rsm psr.i | psr.ic // disable interrupts and interrupt collection
907 mov r15=ip
908 }
909 ;;
910 {
911 flushrs // must be first insn in group
912 srlz.i
913 }
914 ;;
915 mov cr.ipsr=r16 // set new PSR
916 add r3=1f-ia64_switch_mode_phys,r15
918 mov r19=ar.bsp
919 mov r20=sp
920 mov r14=rp // get return address into a general register
921 ;;
923 // going to physical mode, use tpa to translate virt->phys
924 tpa r17=r19
925 tpa r3=r3
926 tpa sp=sp
927 tpa r14=r14
928 ;;
930 mov r18=ar.rnat // save ar.rnat
931 mov ar.bspstore=r17 // this steps on ar.rnat
932 mov cr.iip=r3
933 mov cr.ifs=r0
934 ;;
935 mov ar.rnat=r18 // restore ar.rnat
936 rfi // must be last insn in group
937 ;;
938 1: mov rp=r14
939 br.ret.sptk.many rp
940 END(ia64_switch_mode_phys)
942 /*
943 * Switch execution mode from physical to virtual
944 *
945 * Inputs:
946 * r16 = new psr to establish
947 * r19 = new bspstore to establish
948 * r20 = new sp to establish
949 *
950 * Note: RSE must already be in enforced lazy mode
951 */
952 GLOBAL_ENTRY(ia64_switch_mode_virt)
953 {
954 alloc r2=ar.pfs,0,0,0,0
955 rsm psr.i | psr.ic // disable interrupts and interrupt collection
956 mov r15=ip
957 }
958 ;;
959 {
960 flushrs // must be first insn in group
961 srlz.i
962 }
963 ;;
964 mov cr.ipsr=r16 // set new PSR
965 add r3=1f-ia64_switch_mode_virt,r15
967 mov r14=rp // get return address into a general register
968 ;;
970 // going to virtual
971 // - for code addresses, set upper bits of addr to KERNEL_START
972 // - for stack addresses, copy from input argument
973 movl r18=KERNEL_START
974 dep r3=0,r3,KERNEL_TR_PAGE_SHIFT,64-KERNEL_TR_PAGE_SHIFT
975 dep r14=0,r14,KERNEL_TR_PAGE_SHIFT,64-KERNEL_TR_PAGE_SHIFT
976 mov sp=r20
977 ;;
978 or r3=r3,r18
979 or r14=r14,r18
980 ;;
982 mov r18=ar.rnat // save ar.rnat
983 mov ar.bspstore=r19 // this steps on ar.rnat
984 mov cr.iip=r3
985 mov cr.ifs=r0
986 ;;
987 mov ar.rnat=r18 // restore ar.rnat
988 rfi // must be last insn in group
989 ;;
990 1: mov rp=r14
991 br.ret.sptk.many rp
992 END(ia64_switch_mode_virt)
994 GLOBAL_ENTRY(ia64_delay_loop)
995 .prologue
996 { nop 0 // work around GAS unwind info generation bug...
997 .save ar.lc,r2
998 mov r2=ar.lc
999 .body
1000 ;;
1001 mov ar.lc=r32
1003 ;;
1004 // force loop to be 32-byte aligned (GAS bug means we cannot use .align
1005 // inside function body without corrupting unwind info).
1006 { nop 0 }
1007 1: br.cloop.sptk.few 1b
1008 ;;
1009 mov ar.lc=r2
1010 br.ret.sptk.many rp
1011 END(ia64_delay_loop)
1013 /*
1014 * Return a CPU-local timestamp in nano-seconds. This timestamp is
1015 * NOT synchronized across CPUs its return value must never be
1016 * compared against the values returned on another CPU. The usage in
1017 * kernel/sched.c ensures that.
1019 * The return-value of sched_clock() is NOT supposed to wrap-around.
1020 * If it did, it would cause some scheduling hiccups (at the worst).
1021 * Fortunately, with a 64-bit cycle-counter ticking at 100GHz, even
1022 * that would happen only once every 5+ years.
1024 * The code below basically calculates:
1026 * (ia64_get_itc() * local_cpu_data->nsec_per_cyc) >> IA64_NSEC_PER_CYC_SHIFT
1028 * except that the multiplication and the shift are done with 128-bit
1029 * intermediate precision so that we can produce a full 64-bit result.
1030 */
1031 GLOBAL_ENTRY(sched_clock)
1032 #ifdef XEN
1033 movl r8=THIS_CPU(cpu_info) + IA64_CPUINFO_NSEC_PER_CYC_OFFSET
1034 #else
1035 addl r8=THIS_CPU(cpu_info) + IA64_CPUINFO_NSEC_PER_CYC_OFFSET,r0
1036 #endif
1037 mov.m r9=ar.itc // fetch cycle-counter (35 cyc)
1038 ;;
1039 ldf8 f8=[r8]
1040 ;;
1041 setf.sig f9=r9 // certain to stall, so issue it _after_ ldf8...
1042 ;;
1043 xmpy.lu f10=f9,f8 // calculate low 64 bits of 128-bit product (4 cyc)
1044 xmpy.hu f11=f9,f8 // calculate high 64 bits of 128-bit product
1045 ;;
1046 getf.sig r8=f10 // (5 cyc)
1047 getf.sig r9=f11
1048 ;;
1049 shrp r8=r9,r8,IA64_NSEC_PER_CYC_SHIFT
1050 br.ret.sptk.many rp
1051 END(sched_clock)
1053 GLOBAL_ENTRY(start_kernel_thread)
1054 .prologue
1055 .save rp, r0 // this is the end of the call-chain
1056 .body
1057 alloc r2 = ar.pfs, 0, 0, 2, 0
1058 mov out0 = r9
1059 mov out1 = r11;;
1060 br.call.sptk.many rp = kernel_thread_helper;;
1061 mov out0 = r8
1062 br.call.sptk.many rp = sys_exit;;
1063 1: br.sptk.few 1b // not reached
1064 END(start_kernel_thread)
1066 #ifdef CONFIG_IA64_BRL_EMU
1068 /*
1069 * Assembly routines used by brl_emu.c to set preserved register state.
1070 */
1072 #define SET_REG(reg) \
1073 GLOBAL_ENTRY(ia64_set_##reg); \
1074 alloc r16=ar.pfs,1,0,0,0; \
1075 mov reg=r32; \
1076 ;; \
1077 br.ret.sptk.many rp; \
1078 END(ia64_set_##reg)
1080 SET_REG(b1);
1081 SET_REG(b2);
1082 SET_REG(b3);
1083 SET_REG(b4);
1084 SET_REG(b5);
1086 #endif /* CONFIG_IA64_BRL_EMU */
1088 #ifdef CONFIG_SMP
1089 /*
1090 * This routine handles spinlock contention. It uses a non-standard calling
1091 * convention to avoid converting leaf routines into interior routines. Because
1092 * of this special convention, there are several restrictions:
1094 * - do not use gp relative variables, this code is called from the kernel
1095 * and from modules, r1 is undefined.
1096 * - do not use stacked registers, the caller owns them.
1097 * - do not use the scratch stack space, the caller owns it.
1098 * - do not use any registers other than the ones listed below
1100 * Inputs:
1101 * ar.pfs - saved CFM of caller
1102 * ar.ccv - 0 (and available for use)
1103 * r27 - flags from spin_lock_irqsave or 0. Must be preserved.
1104 * r28 - available for use.
1105 * r29 - available for use.
1106 * r30 - available for use.
1107 * r31 - address of lock, available for use.
1108 * b6 - return address
1109 * p14 - available for use.
1110 * p15 - used to track flag status.
1112 * If you patch this code to use more registers, do not forget to update
1113 * the clobber lists for spin_lock() in include/asm-ia64/spinlock.h.
1114 */
1116 #if __GNUC__ < 3 || (__GNUC__ == 3 && __GNUC_MINOR__ < 3)
1118 GLOBAL_ENTRY(ia64_spinlock_contention_pre3_4)
1119 .prologue
1120 .save ar.pfs, r0 // this code effectively has a zero frame size
1121 .save rp, r28
1122 .body
1123 nop 0
1124 tbit.nz p15,p0=r27,IA64_PSR_I_BIT
1125 .restore sp // pop existing prologue after next insn
1126 mov b6 = r28
1127 .prologue
1128 .save ar.pfs, r0
1129 .altrp b6
1130 .body
1131 ;;
1132 (p15) ssm psr.i // reenable interrupts if they were on
1133 // DavidM says that srlz.d is slow and is not required in this case
1134 .wait:
1135 // exponential backoff, kdb, lockmeter etc. go in here
1136 hint @pause
1137 ld4 r30=[r31] // don't use ld4.bias; if it's contended, we won't write the word
1138 nop 0
1139 ;;
1140 cmp4.ne p14,p0=r30,r0
1141 (p14) br.cond.sptk.few .wait
1142 (p15) rsm psr.i // disable interrupts if we reenabled them
1143 br.cond.sptk.few b6 // lock is now free, try to acquire
1144 .global ia64_spinlock_contention_pre3_4_end // for kernprof
1145 ia64_spinlock_contention_pre3_4_end:
1146 END(ia64_spinlock_contention_pre3_4)
1148 #else
1150 GLOBAL_ENTRY(ia64_spinlock_contention)
1151 .prologue
1152 .altrp b6
1153 .body
1154 tbit.nz p15,p0=r27,IA64_PSR_I_BIT
1155 ;;
1156 .wait:
1157 (p15) ssm psr.i // reenable interrupts if they were on
1158 // DavidM says that srlz.d is slow and is not required in this case
1159 .wait2:
1160 // exponential backoff, kdb, lockmeter etc. go in here
1161 hint @pause
1162 ld4 r30=[r31] // don't use ld4.bias; if it's contended, we won't write the word
1163 ;;
1164 cmp4.ne p14,p0=r30,r0
1165 mov r30 = 1
1166 (p14) br.cond.sptk.few .wait2
1167 (p15) rsm psr.i // disable interrupts if we reenabled them
1168 ;;
1169 cmpxchg4.acq r30=[r31], r30, ar.ccv
1170 ;;
1171 cmp4.ne p14,p0=r0,r30
1172 (p14) br.cond.sptk.few .wait
1174 br.ret.sptk.many b6 // lock is now taken
1175 END(ia64_spinlock_contention)
1177 #endif
1179 #ifdef CONFIG_HOTPLUG_CPU
1180 GLOBAL_ENTRY(ia64_jump_to_sal)
1181 alloc r16=ar.pfs,1,0,0,0;;
1182 rsm psr.i | psr.ic
1184 flushrs
1185 srlz.i
1187 tpa r25=in0
1188 movl r18=tlb_purge_done;;
1189 DATA_VA_TO_PA(r18);;
1190 mov b1=r18 // Return location
1191 movl r18=ia64_do_tlb_purge;;
1192 DATA_VA_TO_PA(r18);;
1193 mov b2=r18 // doing tlb_flush work
1194 mov ar.rsc=0 // Put RSE in enforced lazy, LE mode
1195 movl r17=1f;;
1196 DATA_VA_TO_PA(r17);;
1197 mov cr.iip=r17
1198 movl r16=SAL_PSR_BITS_TO_SET;;
1199 mov cr.ipsr=r16
1200 mov cr.ifs=r0;;
1201 rfi;;
1202 1:
1203 /*
1204 * Invalidate all TLB data/inst
1205 */
1206 br.sptk.many b2;; // jump to tlb purge code
1208 tlb_purge_done:
1209 RESTORE_REGION_REGS(r25, r17,r18,r19);;
1210 RESTORE_REG(b0, r25, r17);;
1211 RESTORE_REG(b1, r25, r17);;
1212 RESTORE_REG(b2, r25, r17);;
1213 RESTORE_REG(b3, r25, r17);;
1214 RESTORE_REG(b4, r25, r17);;
1215 RESTORE_REG(b5, r25, r17);;
1216 ld8 r1=[r25],0x08;;
1217 ld8 r12=[r25],0x08;;
1218 ld8 r13=[r25],0x08;;
1219 RESTORE_REG(ar.fpsr, r25, r17);;
1220 RESTORE_REG(ar.pfs, r25, r17);;
1221 RESTORE_REG(ar.rnat, r25, r17);;
1222 RESTORE_REG(ar.unat, r25, r17);;
1223 RESTORE_REG(ar.bspstore, r25, r17);;
1224 RESTORE_REG(cr.dcr, r25, r17);;
1225 RESTORE_REG(cr.iva, r25, r17);;
1226 RESTORE_REG(cr.pta, r25, r17);;
1227 RESTORE_REG(cr.itv, r25, r17);;
1228 RESTORE_REG(cr.pmv, r25, r17);;
1229 RESTORE_REG(cr.cmcv, r25, r17);;
1230 RESTORE_REG(cr.lrr0, r25, r17);;
1231 RESTORE_REG(cr.lrr1, r25, r17);;
1232 ld8 r4=[r25],0x08;;
1233 ld8 r5=[r25],0x08;;
1234 ld8 r6=[r25],0x08;;
1235 ld8 r7=[r25],0x08;;
1236 ld8 r17=[r25],0x08;;
1237 mov pr=r17,-1;;
1238 RESTORE_REG(ar.lc, r25, r17);;
1239 /*
1240 * Now Restore floating point regs
1241 */
1242 ldf.fill.nta f2=[r25],16;;
1243 ldf.fill.nta f3=[r25],16;;
1244 ldf.fill.nta f4=[r25],16;;
1245 ldf.fill.nta f5=[r25],16;;
1246 ldf.fill.nta f16=[r25],16;;
1247 ldf.fill.nta f17=[r25],16;;
1248 ldf.fill.nta f18=[r25],16;;
1249 ldf.fill.nta f19=[r25],16;;
1250 ldf.fill.nta f20=[r25],16;;
1251 ldf.fill.nta f21=[r25],16;;
1252 ldf.fill.nta f22=[r25],16;;
1253 ldf.fill.nta f23=[r25],16;;
1254 ldf.fill.nta f24=[r25],16;;
1255 ldf.fill.nta f25=[r25],16;;
1256 ldf.fill.nta f26=[r25],16;;
1257 ldf.fill.nta f27=[r25],16;;
1258 ldf.fill.nta f28=[r25],16;;
1259 ldf.fill.nta f29=[r25],16;;
1260 ldf.fill.nta f30=[r25],16;;
1261 ldf.fill.nta f31=[r25],16;;
1263 /*
1264 * Now that we have done all the register restores
1265 * we are now ready for the big DIVE to SAL Land
1266 */
1267 ssm psr.ic;;
1268 srlz.d;;
1269 br.ret.sptk.many b0;;
1270 END(ia64_jump_to_sal)
1271 #endif /* CONFIG_HOTPLUG_CPU */
1273 #endif /* CONFIG_SMP */