ia64/xen-unstable

view xen/arch/ia64/linux-xen/entry.h @ 9770:ced37bea0647

[IA64] FPH enabling + cleanup

Move contents of switch_to macro from xensystem.h to context_switch function.
Initialize FPU on all processors. FPH is always enabled in Xen.
Speed up context-switch (a little bit!) by not enabling/disabling FPH.
Cleanup (unused function/variablesi/fields, debug printf...)
vmx_ia64_switch_to removed (was unused).

Signed-off-by: Tristan Gingold <tristan.gingold@bull.net>
author awilliam@xenbuild.aw
date Tue Apr 25 22:35:41 2006 -0600 (2006-04-25)
parents 06d84bf87159
children
line source
1 #include <linux/config.h>
3 /*
4 * Preserved registers that are shared between code in ivt.S and
5 * entry.S. Be careful not to step on these!
6 */
7 #define PRED_LEAVE_SYSCALL 1 /* TRUE iff leave from syscall */
8 #define PRED_KERNEL_STACK 2 /* returning to kernel-stacks? */
9 #define PRED_USER_STACK 3 /* returning to user-stacks? */
10 #define PRED_SYSCALL 4 /* inside a system call? */
11 #define PRED_NON_SYSCALL 5 /* complement of PRED_SYSCALL */
13 #ifdef __ASSEMBLY__
14 # define PASTE2(x,y) x##y
15 # define PASTE(x,y) PASTE2(x,y)
17 # define pLvSys PASTE(p,PRED_LEAVE_SYSCALL)
18 # define pKStk PASTE(p,PRED_KERNEL_STACK)
19 # define pUStk PASTE(p,PRED_USER_STACK)
20 # define pSys PASTE(p,PRED_SYSCALL)
21 # define pNonSys PASTE(p,PRED_NON_SYSCALL)
22 #endif
24 #define PT(f) (IA64_PT_REGS_##f##_OFFSET)
25 #define SW(f) (IA64_SWITCH_STACK_##f##_OFFSET)
26 #ifdef XEN
27 #define VPD(f) (VPD_##f##_START_OFFSET)
28 #endif
30 #define PT_REGS_SAVES(off) \
31 .unwabi 3, 'i'; \
32 .fframe IA64_PT_REGS_SIZE+16+(off); \
33 .spillsp rp, PT(CR_IIP)+16+(off); \
34 .spillsp ar.pfs, PT(CR_IFS)+16+(off); \
35 .spillsp ar.unat, PT(AR_UNAT)+16+(off); \
36 .spillsp ar.fpsr, PT(AR_FPSR)+16+(off); \
37 .spillsp pr, PT(PR)+16+(off);
39 #define PT_REGS_UNWIND_INFO(off) \
40 .prologue; \
41 PT_REGS_SAVES(off); \
42 .body
44 #define SWITCH_STACK_SAVES(off) \
45 .savesp ar.unat,SW(CALLER_UNAT)+16+(off); \
46 .savesp ar.fpsr,SW(AR_FPSR)+16+(off); \
47 .spillsp f2,SW(F2)+16+(off); .spillsp f3,SW(F3)+16+(off); \
48 .spillsp f4,SW(F4)+16+(off); .spillsp f5,SW(F5)+16+(off); \
49 .spillsp f16,SW(F16)+16+(off); .spillsp f17,SW(F17)+16+(off); \
50 .spillsp f18,SW(F18)+16+(off); .spillsp f19,SW(F19)+16+(off); \
51 .spillsp f20,SW(F20)+16+(off); .spillsp f21,SW(F21)+16+(off); \
52 .spillsp f22,SW(F22)+16+(off); .spillsp f23,SW(F23)+16+(off); \
53 .spillsp f24,SW(F24)+16+(off); .spillsp f25,SW(F25)+16+(off); \
54 .spillsp f26,SW(F26)+16+(off); .spillsp f27,SW(F27)+16+(off); \
55 .spillsp f28,SW(F28)+16+(off); .spillsp f29,SW(F29)+16+(off); \
56 .spillsp f30,SW(F30)+16+(off); .spillsp f31,SW(F31)+16+(off); \
57 .spillsp r4,SW(R4)+16+(off); .spillsp r5,SW(R5)+16+(off); \
58 .spillsp r6,SW(R6)+16+(off); .spillsp r7,SW(R7)+16+(off); \
59 .spillsp b0,SW(B0)+16+(off); .spillsp b1,SW(B1)+16+(off); \
60 .spillsp b2,SW(B2)+16+(off); .spillsp b3,SW(B3)+16+(off); \
61 .spillsp b4,SW(B4)+16+(off); .spillsp b5,SW(B5)+16+(off); \
62 .spillsp ar.pfs,SW(AR_PFS)+16+(off); .spillsp ar.lc,SW(AR_LC)+16+(off); \
63 .spillsp @priunat,SW(AR_UNAT)+16+(off); \
64 .spillsp ar.rnat,SW(AR_RNAT)+16+(off); \
65 .spillsp ar.bspstore,SW(AR_BSPSTORE)+16+(off); \
66 .spillsp pr,SW(PR)+16+(off)
68 #define DO_SAVE_SWITCH_STACK \
69 movl r28=1f; \
70 ;; \
71 .fframe IA64_SWITCH_STACK_SIZE; \
72 adds sp=-IA64_SWITCH_STACK_SIZE,sp; \
73 mov.ret.sptk b7=r28,1f; \
74 SWITCH_STACK_SAVES(0); \
75 br.cond.sptk.many save_switch_stack; \
76 1:
78 #define DO_LOAD_SWITCH_STACK \
79 movl r28=1f; \
80 ;; \
81 invala; \
82 mov.ret.sptk b7=r28,1f; \
83 br.cond.sptk.many load_switch_stack; \
84 1: .restore sp; \
85 adds sp=IA64_SWITCH_STACK_SIZE,sp