ia64/xen-unstable

view xen/include/public/arch-ia64.h @ 5797:ca44d2dbb273

Intel's pre-bk->hg transition patches
Signed-off-by Eddie Dong <Eddie.dong@intel.com>
Signed-off-by Anthony Xu <Anthony.xu@intel.com>
Signed-off-by Kevin Tian <Kevin.tian@intel.com>
author djm@kirby.fc.hp.com
date Sat Jul 09 07:58:56 2005 -0700 (2005-07-09)
parents 2b6c1a809807
children a83ac0806d6b
line source
1 /******************************************************************************
2 * arch-ia64/hypervisor-if.h
3 *
4 * Guest OS interface to IA64 Xen.
5 */
7 #ifndef __HYPERVISOR_IF_IA64_H__
8 #define __HYPERVISOR_IF_IA64_H__
10 /* Maximum number of virtual CPUs in multi-processor guests. */
11 /* WARNING: before changing this, check that shared_info fits on a page */
12 #define MAX_VIRT_CPUS 1
14 #ifndef __ASSEMBLY__
16 /* NB. Both the following are 64 bits each. */
17 typedef unsigned long memory_t; /* Full-sized pointer/address/memory-size. */
19 #define MAX_NR_SECTION 32 // at most 32 memory holes
20 typedef struct {
21 unsigned long start; /* start of memory hole */
22 unsigned long end; /* end of memory hole */
23 } mm_section_t;
25 typedef struct {
26 unsigned long mfn : 56;
27 unsigned long type: 8;
28 } pmt_entry_t;
30 #define GPFN_MEM (0UL << 56) /* Guest pfn is normal mem */
31 #define GPFN_FRAME_BUFFER (1UL << 56) /* VGA framebuffer */
32 #define GPFN_LOW_MMIO (2UL << 56) /* Low MMIO range */
33 #define GPFN_PIB (3UL << 56) /* PIB base */
34 #define GPFN_IOSAPIC (4UL << 56) /* IOSAPIC base */
35 #define GPFN_LEGACY_IO (5UL << 56) /* Legacy I/O base */
36 #define GPFN_GFW (6UL << 56) /* Guest Firmware */
37 #define GPFN_HIGH_MMIO (7UL << 56) /* High MMIO range */
39 #define GPFN_IO_MASK (7UL << 56) /* Guest pfn is I/O type */
40 #define GPFN_INV_MASK (31UL << 59) /* Guest pfn is invalid */
42 #define INVALID_MFN (~0UL)
44 /*
45 * NB. This may become a 64-bit count with no shift. If this happens then the
46 * structure size will still be 8 bytes, so no other alignments will change.
47 */
48 typedef struct {
49 unsigned int tsc_bits; /* 0: 32 bits read from the CPU's TSC. */
50 unsigned int tsc_bitshift; /* 4: 'tsc_bits' uses N:N+31 of TSC. */
51 } tsc_timestamp_t; /* 8 bytes */
53 struct pt_fpreg {
54 union {
55 unsigned long bits[2];
56 long double __dummy; /* force 16-byte alignment */
57 } u;
58 };
60 struct pt_regs {
61 /* The following registers are saved by SAVE_MIN: */
62 unsigned long b6; /* scratch */
63 unsigned long b7; /* scratch */
65 unsigned long ar_csd; /* used by cmp8xchg16 (scratch) */
66 unsigned long ar_ssd; /* reserved for future use (scratch) */
68 unsigned long r8; /* scratch (return value register 0) */
69 unsigned long r9; /* scratch (return value register 1) */
70 unsigned long r10; /* scratch (return value register 2) */
71 unsigned long r11; /* scratch (return value register 3) */
73 unsigned long cr_ipsr; /* interrupted task's psr */
74 unsigned long cr_iip; /* interrupted task's instruction pointer */
75 unsigned long cr_ifs; /* interrupted task's function state */
77 unsigned long ar_unat; /* interrupted task's NaT register (preserved) */
78 unsigned long ar_pfs; /* prev function state */
79 unsigned long ar_rsc; /* RSE configuration */
80 /* The following two are valid only if cr_ipsr.cpl > 0: */
81 unsigned long ar_rnat; /* RSE NaT */
82 unsigned long ar_bspstore; /* RSE bspstore */
84 unsigned long pr; /* 64 predicate registers (1 bit each) */
85 unsigned long b0; /* return pointer (bp) */
86 unsigned long loadrs; /* size of dirty partition << 16 */
88 unsigned long r1; /* the gp pointer */
89 unsigned long r12; /* interrupted task's memory stack pointer */
90 unsigned long r13; /* thread pointer */
92 unsigned long ar_fpsr; /* floating point status (preserved) */
93 unsigned long r15; /* scratch */
95 /* The remaining registers are NOT saved for system calls. */
97 unsigned long r14; /* scratch */
98 unsigned long r2; /* scratch */
99 unsigned long r3; /* scratch */
101 #ifdef CONFIG_VTI
102 unsigned long r4; /* preserved */
103 unsigned long r5; /* preserved */
104 unsigned long r6; /* preserved */
105 unsigned long r7; /* preserved */
106 unsigned long cr_iipa; /* for emulation */
107 unsigned long cr_isr; /* for emulation */
108 unsigned long eml_unat; /* used for emulating instruction */
109 unsigned long rfi_pfs; /* used for elulating rfi */
110 #endif
112 /* The following registers are saved by SAVE_REST: */
113 unsigned long r16; /* scratch */
114 unsigned long r17; /* scratch */
115 unsigned long r18; /* scratch */
116 unsigned long r19; /* scratch */
117 unsigned long r20; /* scratch */
118 unsigned long r21; /* scratch */
119 unsigned long r22; /* scratch */
120 unsigned long r23; /* scratch */
121 unsigned long r24; /* scratch */
122 unsigned long r25; /* scratch */
123 unsigned long r26; /* scratch */
124 unsigned long r27; /* scratch */
125 unsigned long r28; /* scratch */
126 unsigned long r29; /* scratch */
127 unsigned long r30; /* scratch */
128 unsigned long r31; /* scratch */
130 unsigned long ar_ccv; /* compare/exchange value (scratch) */
132 /*
133 * Floating point registers that the kernel considers scratch:
134 */
135 struct pt_fpreg f6; /* scratch */
136 struct pt_fpreg f7; /* scratch */
137 struct pt_fpreg f8; /* scratch */
138 struct pt_fpreg f9; /* scratch */
139 struct pt_fpreg f10; /* scratch */
140 struct pt_fpreg f11; /* scratch */
141 };
143 typedef struct {
144 unsigned long ipsr;
145 unsigned long iip;
146 unsigned long ifs;
147 unsigned long precover_ifs;
148 unsigned long isr;
149 unsigned long ifa;
150 unsigned long iipa;
151 unsigned long iim;
152 unsigned long unat; // not sure if this is needed until NaT arch is done
153 unsigned long tpr;
154 unsigned long iha;
155 unsigned long itir;
156 unsigned long itv;
157 unsigned long pmv;
158 unsigned long cmcv;
159 unsigned long pta;
160 int interrupt_collection_enabled; // virtual psr.ic
161 int interrupt_delivery_enabled; // virtual psr.i
162 int pending_interruption;
163 int incomplete_regframe; // see SDM vol2 6.8
164 unsigned long delivery_mask[4];
165 int metaphysical_mode; // 1 = use metaphys mapping, 0 = use virtual
166 int banknum; // 0 or 1, which virtual register bank is active
167 unsigned long bank0_regs[16]; // bank0 regs (r16-r31) when bank1 active
168 unsigned long bank1_regs[16]; // bank1 regs (r16-r31) when bank0 active
169 unsigned long rrs[8]; // region registers
170 unsigned long krs[8]; // kernel registers
171 unsigned long pkrs[8]; // protection key registers
172 unsigned long tmp[8]; // temp registers (e.g. for hyperprivops)
173 int evtchn_vector;
174 } arch_vcpu_info_t;
175 #define __ARCH_HAS_VCPU_INFO
177 typedef struct {
178 int domain_controller_evtchn;
179 unsigned int flags;
180 //} arch_shared_info_t;
181 } arch_shared_info_t; // DON'T PACK
183 typedef struct vcpu_guest_context {
184 #define VGCF_FPU_VALID (1<<0)
185 #define VGCF_VMX_GUEST (1<<1)
186 #define VGCF_IN_KERNEL (1<<2)
187 unsigned long flags; /* VGCF_* flags */
188 unsigned long pt_base; /* PMT table base */
189 unsigned long pt_max_pfn; /* Max pfn including holes */
190 unsigned long share_io_pg; /* Shared page for I/O emulation */
191 unsigned long vm_assist; /* VMASST_TYPE_* bitmap, now none on IPF */
192 unsigned long guest_iip; /* Guest entry point */
194 struct pt_regs regs;
195 arch_vcpu_info_t vcpu;
196 arch_shared_info_t shared;
197 } vcpu_guest_context_t;
199 #endif /* !__ASSEMBLY__ */
201 #define XEN_HYPER_RFI 0x1
202 #define XEN_HYPER_RSM_DT 0x2
203 #define XEN_HYPER_SSM_DT 0x3
204 #define XEN_HYPER_COVER 0x4
205 #define XEN_HYPER_ITC_D 0x5
206 #define XEN_HYPER_ITC_I 0x6
207 #define XEN_HYPER_SSM_I 0x7
208 #define XEN_HYPER_GET_IVR 0x8
209 #define XEN_HYPER_GET_TPR 0x9
210 #define XEN_HYPER_SET_TPR 0xa
211 #define XEN_HYPER_EOI 0xb
212 #define XEN_HYPER_SET_ITM 0xc
213 #define XEN_HYPER_THASH 0xd
214 #define XEN_HYPER_PTC_GA 0xe
215 #define XEN_HYPER_ITR_D 0xf
216 #define XEN_HYPER_GET_RR 0x10
217 #define XEN_HYPER_SET_RR 0x11
219 #endif /* __HYPERVISOR_IF_IA64_H__ */