ia64/xen-unstable

view xen/include/asm-ia64/xenprocessor.h @ 5797:ca44d2dbb273

Intel's pre-bk->hg transition patches
Signed-off-by Eddie Dong <Eddie.dong@intel.com>
Signed-off-by Anthony Xu <Anthony.xu@intel.com>
Signed-off-by Kevin Tian <Kevin.tian@intel.com>
author djm@kirby.fc.hp.com
date Sat Jul 09 07:58:56 2005 -0700 (2005-07-09)
parents c91f74efda05
children a83ac0806d6b
line source
1 #ifndef _ASM_IA64_XENPROCESSOR_H
2 #define _ASM_IA64_XENPROCESSOR_H
3 /*
4 * xen specific processor definition
5 *
6 * Copyright (C) 2005 Hewlett-Packard Co.
7 * Dan Magenheimer (dan.magenheimer@hp.com)
8 *
9 * Copyright (C) 2005 Intel Co.
10 * Kun Tian (Kevin Tian) <kevin.tian@intel.com>
11 *
12 */
15 #define ia64_is_local_fpu_owner(t) 0
17 /* like above but expressed as bitfields for more efficient access: */
18 struct ia64_psr {
19 __u64 reserved0 : 1;
20 __u64 be : 1;
21 __u64 up : 1;
22 __u64 ac : 1;
23 __u64 mfl : 1;
24 __u64 mfh : 1;
25 __u64 reserved1 : 7;
26 __u64 ic : 1;
27 __u64 i : 1;
28 __u64 pk : 1;
29 __u64 reserved2 : 1;
30 __u64 dt : 1;
31 __u64 dfl : 1;
32 __u64 dfh : 1;
33 __u64 sp : 1;
34 __u64 pp : 1;
35 __u64 di : 1;
36 __u64 si : 1;
37 __u64 db : 1;
38 __u64 lp : 1;
39 __u64 tb : 1;
40 __u64 rt : 1;
41 __u64 reserved3 : 4;
42 __u64 cpl : 2;
43 __u64 is : 1;
44 __u64 mc : 1;
45 __u64 it : 1;
46 __u64 id : 1;
47 __u64 da : 1;
48 __u64 dd : 1;
49 __u64 ss : 1;
50 __u64 ri : 2;
51 __u64 ed : 1;
52 __u64 bn : 1;
53 #ifdef CONFIG_VTI
54 __u64 ia : 1;
55 __u64 vm : 1;
56 __u64 reserved5 : 17;
57 #else // CONFIG_VTI
58 __u64 reserved4 : 19;
59 #endif // CONFIG_VTI
60 };
62 #ifdef CONFIG_VTI
63 /* vmx like above but expressed as bitfields for more efficient access: */
64 typedef union{
65 __u64 val;
66 struct{
67 __u64 reserved0 : 1;
68 __u64 be : 1;
69 __u64 up : 1;
70 __u64 ac : 1;
71 __u64 mfl : 1;
72 __u64 mfh : 1;
73 __u64 reserved1 : 7;
74 __u64 ic : 1;
75 __u64 i : 1;
76 __u64 pk : 1;
77 __u64 reserved2 : 1;
78 __u64 dt : 1;
79 __u64 dfl : 1;
80 __u64 dfh : 1;
81 __u64 sp : 1;
82 __u64 pp : 1;
83 __u64 di : 1;
84 __u64 si : 1;
85 __u64 db : 1;
86 __u64 lp : 1;
87 __u64 tb : 1;
88 __u64 rt : 1;
89 __u64 reserved3 : 4;
90 __u64 cpl : 2;
91 __u64 is : 1;
92 __u64 mc : 1;
93 __u64 it : 1;
94 __u64 id : 1;
95 __u64 da : 1;
96 __u64 dd : 1;
97 __u64 ss : 1;
98 __u64 ri : 2;
99 __u64 ed : 1;
100 __u64 bn : 1;
101 __u64 reserved4 : 19;
102 };
103 } IA64_PSR;
105 typedef union {
106 __u64 val;
107 struct {
108 __u64 code : 16;
109 __u64 vector : 8;
110 __u64 reserved1 : 8;
111 __u64 x : 1;
112 __u64 w : 1;
113 __u64 r : 1;
114 __u64 na : 1;
115 __u64 sp : 1;
116 __u64 rs : 1;
117 __u64 ir : 1;
118 __u64 ni : 1;
119 __u64 so : 1;
120 __u64 ei : 2;
121 __u64 ed : 1;
122 __u64 reserved2 : 20;
123 };
124 } ISR;
127 typedef union {
128 __u64 val;
129 struct {
130 __u64 ve : 1;
131 __u64 reserved0 : 1;
132 __u64 size : 6;
133 __u64 vf : 1;
134 __u64 reserved1 : 6;
135 __u64 base : 49;
136 };
137 } PTA;
139 typedef union {
140 __u64 val;
141 struct {
142 __u64 rv : 16;
143 __u64 eid : 8;
144 __u64 id : 8;
145 __u64 ig : 32;
146 };
147 } LID;
149 typedef union{
150 __u64 val;
151 struct {
152 __u64 rv : 3;
153 __u64 ir : 1;
154 __u64 eid : 8;
155 __u64 id : 8;
156 __u64 ib_base : 44;
157 };
158 } ipi_a_t;
160 typedef union{
161 __u64 val;
162 struct {
163 __u64 vector : 8;
164 __u64 dm : 3;
165 __u64 ig : 53;
166 };
167 } ipi_d_t;
169 typedef union {
170 __u64 val;
171 struct {
172 __u64 ig0 : 4;
173 __u64 mic : 4;
174 __u64 rsv : 8;
175 __u64 mmi : 1;
176 __u64 ig1 : 47;
177 };
178 } tpr_t;
180 #define IA64_ISR_CODE_MASK0 0xf
181 #define IA64_UNIMPL_DADDR_FAULT 0x30
182 #define IA64_UNIMPL_IADDR_TRAP 0x10
183 #define IA64_RESERVED_REG_FAULT 0x30
184 #define IA64_REG_NAT_CONSUMPTION_FAULT 0x10
185 #define IA64_NAT_CONSUMPTION_FAULT 0x20
186 #define IA64_PRIV_OP_FAULT 0x10
188 /* indirect register type */
189 enum {
190 IA64_CPUID, /* cpuid */
191 IA64_DBR, /* dbr */
192 IA64_IBR, /* ibr */
193 IA64_PKR, /* pkr */
194 IA64_PMC, /* pmc */
195 IA64_PMD, /* pmd */
196 IA64_RR /* rr */
197 };
199 /* instruction type */
200 enum {
201 IA64_INST_TPA=1,
202 IA64_INST_TAK
203 };
205 /* Generate Mask
206 * Parameter:
207 * bit -- starting bit
208 * len -- how many bits
209 */
210 #define MASK(bit,len) \
211 ({ \
212 __u64 ret; \
213 \
214 __asm __volatile("dep %0=-1, r0, %1, %2" \
215 : "=r" (ret): \
216 "M" (bit), \
217 "M" (len) ); \
218 ret; \
219 })
221 #endif // CONFIG_VTI
223 #endif // _ASM_IA64_XENPROCESSOR_H