ia64/xen-unstable

view xen/arch/ia64/xen/vcpu.c @ 10704:c8bc76d877e0

[IA64] Fix fetch code method when FP fault occurs @VTi side

This patch intends to use __vmx_get_domain_bundle to fetch code
when FP fault @VTi side.

Singed-off-by: Zhang xiantao <xiantao.zhang@intel.com>
author awilliam@xenbuild.aw
date Mon Jul 24 13:48:12 2006 -0600 (2006-07-24)
parents 000789c36d28
children 2db50529223e
line source
1 /*
2 * Virtualized CPU functions
3 *
4 * Copyright (C) 2004-2005 Hewlett-Packard Co.
5 * Dan Magenheimer (dan.magenheimer@hp.com)
6 *
7 */
9 #include <linux/sched.h>
10 #include <public/arch-ia64.h>
11 #include <asm/ia64_int.h>
12 #include <asm/vcpu.h>
13 #include <asm/regionreg.h>
14 #include <asm/tlb.h>
15 #include <asm/processor.h>
16 #include <asm/delay.h>
17 #include <asm/vmx_vcpu.h>
18 #include <asm/vhpt.h>
19 #include <asm/tlbflush.h>
20 #include <asm/privop.h>
21 #include <xen/event.h>
22 #include <asm/vmx_phy_mode.h>
23 #include <asm/bundle.h>
24 #include <asm/privop_stat.h>
26 /* FIXME: where these declarations should be there ? */
27 extern void getreg(unsigned long regnum, unsigned long *val, int *nat, struct pt_regs *regs);
28 extern void setreg(unsigned long regnum, unsigned long val, int nat, struct pt_regs *regs);
29 extern void getfpreg (unsigned long regnum, struct ia64_fpreg *fpval, struct pt_regs *regs);
31 extern void setfpreg (unsigned long regnum, struct ia64_fpreg *fpval, struct pt_regs *regs);
33 extern void panic_domain(struct pt_regs *, const char *, ...);
35 typedef union {
36 struct ia64_psr ia64_psr;
37 unsigned long i64;
38 } PSR;
40 // this def for vcpu_regs won't work if kernel stack is present
41 //#define vcpu_regs(vcpu) ((struct pt_regs *) vcpu->arch.regs
43 #define TRUE 1
44 #define FALSE 0
45 #define IA64_PTA_SZ_BIT 2
46 #define IA64_PTA_VF_BIT 8
47 #define IA64_PTA_BASE_BIT 15
48 #define IA64_PTA_LFMT (1UL << IA64_PTA_VF_BIT)
49 #define IA64_PTA_SZ(x) (x##UL << IA64_PTA_SZ_BIT)
51 unsigned long vcpu_verbose = 0;
53 /**************************************************************************
54 VCPU general register access routines
55 **************************************************************************/
56 #ifdef XEN
57 UINT64
58 vcpu_get_gr(VCPU *vcpu, unsigned long reg)
59 {
60 REGS *regs = vcpu_regs(vcpu);
61 UINT64 val;
63 if (!reg) return 0;
64 getreg(reg,&val,0,regs); // FIXME: handle NATs later
65 return val;
66 }
67 IA64FAULT
68 vcpu_get_gr_nat(VCPU *vcpu, unsigned long reg, UINT64 *val)
69 {
70 REGS *regs = vcpu_regs(vcpu);
71 int nat;
73 getreg(reg,val,&nat,regs); // FIXME: handle NATs later
74 if (nat)
75 return IA64_NAT_CONSUMPTION_VECTOR;
76 return 0;
77 }
79 // returns:
80 // IA64_ILLOP_FAULT if the register would cause an Illegal Operation fault
81 // IA64_NO_FAULT otherwise
82 IA64FAULT
83 vcpu_set_gr(VCPU *vcpu, unsigned long reg, UINT64 value, int nat)
84 {
85 REGS *regs = vcpu_regs(vcpu);
86 long sof = (regs->cr_ifs) & 0x7f;
88 if (!reg) return IA64_ILLOP_FAULT;
89 if (reg >= sof + 32) return IA64_ILLOP_FAULT;
90 setreg(reg,value,nat,regs); // FIXME: handle NATs later
91 return IA64_NO_FAULT;
92 }
94 IA64FAULT
95 vcpu_get_fpreg(VCPU *vcpu, unsigned long reg, struct ia64_fpreg *val)
96 {
97 REGS *regs = vcpu_regs(vcpu);
98 getfpreg(reg,val,regs); // FIXME: handle NATs later
99 return IA64_NO_FAULT;
100 }
102 IA64FAULT
103 vcpu_set_fpreg(VCPU *vcpu, unsigned long reg, struct ia64_fpreg *val)
104 {
105 REGS *regs = vcpu_regs(vcpu);
106 if(reg > 1)
107 setfpreg(reg,val,regs); // FIXME: handle NATs later
108 return IA64_NO_FAULT;
109 }
111 #else
112 // returns:
113 // IA64_ILLOP_FAULT if the register would cause an Illegal Operation fault
114 // IA64_NO_FAULT otherwise
115 IA64FAULT
116 vcpu_set_gr(VCPU *vcpu, unsigned long reg, UINT64 value)
117 {
118 REGS *regs = vcpu_regs(vcpu);
119 long sof = (regs->cr_ifs) & 0x7f;
121 if (!reg) return IA64_ILLOP_FAULT;
122 if (reg >= sof + 32) return IA64_ILLOP_FAULT;
123 setreg(reg,value,0,regs); // FIXME: handle NATs later
124 return IA64_NO_FAULT;
125 }
127 #endif
129 void vcpu_init_regs (struct vcpu *v)
130 {
131 struct pt_regs *regs;
133 regs = vcpu_regs (v);
134 if (VMX_DOMAIN(v)) {
135 /* dt/rt/it:1;i/ic:1, si:1, vm/bn:1, ac:1 */
136 /* Need to be expanded as macro */
137 regs->cr_ipsr = 0x501008826008;
138 } else {
139 regs->cr_ipsr = ia64_getreg(_IA64_REG_PSR)
140 | IA64_PSR_BITS_TO_SET | IA64_PSR_BN;
141 regs->cr_ipsr &= ~(IA64_PSR_BITS_TO_CLEAR
142 | IA64_PSR_RI | IA64_PSR_IS);
143 // domain runs at PL2
144 regs->cr_ipsr |= 2UL << IA64_PSR_CPL0_BIT;
145 }
146 regs->cr_ifs = 1UL << 63; /* or clear? */
147 regs->ar_fpsr = FPSR_DEFAULT;
149 if (VMX_DOMAIN(v)) {
150 vmx_init_all_rr(v);
151 /* Virtual processor context setup */
152 VCPU(v, vpsr) = IA64_PSR_BN;
153 VCPU(v, dcr) = 0;
154 } else {
155 init_all_rr(v);
156 regs->ar_rsc |= (2 << 2); /* force PL2/3 */
157 VCPU(v, banknum) = 1;
158 VCPU(v, metaphysical_mode) = 1;
159 VCPU(v, interrupt_mask_addr) =
160 (unsigned char *)v->domain->arch.shared_info_va +
161 INT_ENABLE_OFFSET(v);
162 VCPU(v, itv) = (1 << 16); /* timer vector masked */
163 }
165 v->arch.domain_itm_last = -1L;
166 }
168 /**************************************************************************
169 VCPU privileged application register access routines
170 **************************************************************************/
172 void vcpu_load_kernel_regs(VCPU *vcpu)
173 {
174 ia64_set_kr(0, VCPU(vcpu, krs[0]));
175 ia64_set_kr(1, VCPU(vcpu, krs[1]));
176 ia64_set_kr(2, VCPU(vcpu, krs[2]));
177 ia64_set_kr(3, VCPU(vcpu, krs[3]));
178 ia64_set_kr(4, VCPU(vcpu, krs[4]));
179 ia64_set_kr(5, VCPU(vcpu, krs[5]));
180 ia64_set_kr(6, VCPU(vcpu, krs[6]));
181 ia64_set_kr(7, VCPU(vcpu, krs[7]));
182 }
184 /* GCC 4.0.2 seems not to be able to suppress this call!. */
185 #define ia64_setreg_unknown_kr() return IA64_ILLOP_FAULT
187 IA64FAULT vcpu_set_ar(VCPU *vcpu, UINT64 reg, UINT64 val)
188 {
189 if (reg == 44) return (vcpu_set_itc(vcpu,val));
190 else if (reg == 27) return (IA64_ILLOP_FAULT);
191 else if (reg == 24)
192 printf("warning: setting ar.eflg is a no-op; no IA-32 support\n");
193 else if (reg > 7) return (IA64_ILLOP_FAULT);
194 else {
195 PSCB(vcpu,krs[reg]) = val;
196 ia64_set_kr(reg,val);
197 }
198 return IA64_NO_FAULT;
199 }
201 IA64FAULT vcpu_get_ar(VCPU *vcpu, UINT64 reg, UINT64 *val)
202 {
203 if (reg == 24)
204 printf("warning: getting ar.eflg is a no-op; no IA-32 support\n");
205 else if (reg > 7) return (IA64_ILLOP_FAULT);
206 else *val = PSCB(vcpu,krs[reg]);
207 return IA64_NO_FAULT;
208 }
210 /**************************************************************************
211 VCPU processor status register access routines
212 **************************************************************************/
214 void vcpu_set_metaphysical_mode(VCPU *vcpu, BOOLEAN newmode)
215 {
216 /* only do something if mode changes */
217 if (!!newmode ^ !!PSCB(vcpu,metaphysical_mode)) {
218 PSCB(vcpu,metaphysical_mode) = newmode;
219 if (newmode) set_metaphysical_rr0();
220 else if (PSCB(vcpu,rrs[0]) != -1)
221 set_one_rr(0, PSCB(vcpu,rrs[0]));
222 }
223 }
225 IA64FAULT vcpu_reset_psr_dt(VCPU *vcpu)
226 {
227 vcpu_set_metaphysical_mode(vcpu,TRUE);
228 return IA64_NO_FAULT;
229 }
231 IA64FAULT vcpu_reset_psr_sm(VCPU *vcpu, UINT64 imm24)
232 {
233 struct ia64_psr psr, imm, *ipsr;
234 REGS *regs = vcpu_regs(vcpu);
236 //PRIVOP_COUNT_ADDR(regs,_RSM);
237 // TODO: All of these bits need to be virtualized
238 // TODO: Only allowed for current vcpu
239 __asm__ __volatile ("mov %0=psr;;" : "=r"(psr) :: "memory");
240 ipsr = (struct ia64_psr *)&regs->cr_ipsr;
241 imm = *(struct ia64_psr *)&imm24;
242 // interrupt flag
243 if (imm.i)
244 vcpu->vcpu_info->evtchn_upcall_mask = 1;
245 if (imm.ic) PSCB(vcpu,interrupt_collection_enabled) = 0;
246 // interrupt collection flag
247 //if (imm.ic) PSCB(vcpu,interrupt_delivery_enabled) = 0;
248 // just handle psr.up and psr.pp for now
249 if (imm24 & ~(IA64_PSR_BE | IA64_PSR_PP | IA64_PSR_UP | IA64_PSR_SP
250 | IA64_PSR_I | IA64_PSR_IC | IA64_PSR_DT
251 | IA64_PSR_DFL | IA64_PSR_DFH))
252 return (IA64_ILLOP_FAULT);
253 if (imm.dfh) ipsr->dfh = 0;
254 if (imm.dfl) ipsr->dfl = 0;
255 if (imm.pp) {
256 ipsr->pp = 1;
257 psr.pp = 1; // priv perf ctrs always enabled
258 PSCB(vcpu,vpsr_pp) = 0; // but fool the domain if it gets psr
259 }
260 if (imm.up) { ipsr->up = 0; psr.up = 0; }
261 if (imm.sp) { ipsr->sp = 0; psr.sp = 0; }
262 if (imm.be) ipsr->be = 0;
263 if (imm.dt) vcpu_set_metaphysical_mode(vcpu,TRUE);
264 __asm__ __volatile (";; mov psr.l=%0;; srlz.d"::"r"(psr):"memory");
265 return IA64_NO_FAULT;
266 }
269 IA64FAULT vcpu_set_psr_dt(VCPU *vcpu)
270 {
271 vcpu_set_metaphysical_mode(vcpu,FALSE);
272 return IA64_NO_FAULT;
273 }
275 IA64FAULT vcpu_set_psr_i(VCPU *vcpu)
276 {
277 vcpu->vcpu_info->evtchn_upcall_mask = 0;
278 PSCB(vcpu,interrupt_collection_enabled) = 1;
279 return IA64_NO_FAULT;
280 }
282 IA64FAULT vcpu_set_psr_sm(VCPU *vcpu, UINT64 imm24)
283 {
284 struct ia64_psr psr, imm, *ipsr;
285 REGS *regs = vcpu_regs(vcpu);
286 UINT64 mask, enabling_interrupts = 0;
288 //PRIVOP_COUNT_ADDR(regs,_SSM);
289 // TODO: All of these bits need to be virtualized
290 __asm__ __volatile ("mov %0=psr;;" : "=r"(psr) :: "memory");
291 imm = *(struct ia64_psr *)&imm24;
292 ipsr = (struct ia64_psr *)&regs->cr_ipsr;
293 // just handle psr.sp,pp and psr.i,ic (and user mask) for now
294 mask = IA64_PSR_PP|IA64_PSR_SP|IA64_PSR_I|IA64_PSR_IC|IA64_PSR_UM |
295 IA64_PSR_DT|IA64_PSR_DFL|IA64_PSR_DFH;
296 if (imm24 & ~mask) return (IA64_ILLOP_FAULT);
297 if (imm.dfh) ipsr->dfh = 1;
298 if (imm.dfl) ipsr->dfl = 1;
299 if (imm.pp) {
300 ipsr->pp = 1;
301 psr.pp = 1;
302 PSCB(vcpu,vpsr_pp) = 1;
303 }
304 if (imm.sp) { ipsr->sp = 1; psr.sp = 1; }
305 if (imm.i) {
306 if (vcpu->vcpu_info->evtchn_upcall_mask) {
307 //printf("vcpu_set_psr_sm: psr.ic 0->1\n");
308 enabling_interrupts = 1;
309 }
310 vcpu->vcpu_info->evtchn_upcall_mask = 0;
311 }
312 if (imm.ic) PSCB(vcpu,interrupt_collection_enabled) = 1;
313 // TODO: do this faster
314 if (imm.mfl) { ipsr->mfl = 1; psr.mfl = 1; }
315 if (imm.mfh) { ipsr->mfh = 1; psr.mfh = 1; }
316 if (imm.ac) { ipsr->ac = 1; psr.ac = 1; }
317 if (imm.up) { ipsr->up = 1; psr.up = 1; }
318 if (imm.be) {
319 printf("*** DOMAIN TRYING TO TURN ON BIG-ENDIAN!!!\n");
320 return (IA64_ILLOP_FAULT);
321 }
322 if (imm.dt) vcpu_set_metaphysical_mode(vcpu,FALSE);
323 __asm__ __volatile (";; mov psr.l=%0;; srlz.d"::"r"(psr):"memory");
324 if (enabling_interrupts &&
325 vcpu_check_pending_interrupts(vcpu) != SPURIOUS_VECTOR)
326 PSCB(vcpu,pending_interruption) = 1;
327 return IA64_NO_FAULT;
328 }
330 IA64FAULT vcpu_set_psr_l(VCPU *vcpu, UINT64 val)
331 {
332 struct ia64_psr psr, newpsr, *ipsr;
333 REGS *regs = vcpu_regs(vcpu);
334 UINT64 enabling_interrupts = 0;
336 // TODO: All of these bits need to be virtualized
337 __asm__ __volatile ("mov %0=psr;;" : "=r"(psr) :: "memory");
338 newpsr = *(struct ia64_psr *)&val;
339 ipsr = (struct ia64_psr *)&regs->cr_ipsr;
340 // just handle psr.up and psr.pp for now
341 //if (val & ~(IA64_PSR_PP | IA64_PSR_UP | IA64_PSR_SP)) return (IA64_ILLOP_FAULT);
342 // however trying to set other bits can't be an error as it is in ssm
343 if (newpsr.dfh) ipsr->dfh = 1;
344 if (newpsr.dfl) ipsr->dfl = 1;
345 if (newpsr.pp) {
346 ipsr->pp = 1; psr.pp = 1;
347 PSCB(vcpu,vpsr_pp) = 1;
348 }
349 else {
350 ipsr->pp = 1; psr.pp = 1;
351 PSCB(vcpu,vpsr_pp) = 0;
352 }
353 if (newpsr.up) { ipsr->up = 1; psr.up = 1; }
354 if (newpsr.sp) { ipsr->sp = 1; psr.sp = 1; }
355 if (newpsr.i) {
356 if (vcpu->vcpu_info->evtchn_upcall_mask)
357 enabling_interrupts = 1;
358 vcpu->vcpu_info->evtchn_upcall_mask = 0;
359 }
360 if (newpsr.ic) PSCB(vcpu,interrupt_collection_enabled) = 1;
361 if (newpsr.mfl) { ipsr->mfl = 1; psr.mfl = 1; }
362 if (newpsr.mfh) { ipsr->mfh = 1; psr.mfh = 1; }
363 if (newpsr.ac) { ipsr->ac = 1; psr.ac = 1; }
364 if (newpsr.up) { ipsr->up = 1; psr.up = 1; }
365 if (newpsr.dt && newpsr.rt) vcpu_set_metaphysical_mode(vcpu,FALSE);
366 else vcpu_set_metaphysical_mode(vcpu,TRUE);
367 if (newpsr.be) {
368 printf("*** DOMAIN TRYING TO TURN ON BIG-ENDIAN!!!\n");
369 return (IA64_ILLOP_FAULT);
370 }
371 if (enabling_interrupts &&
372 vcpu_check_pending_interrupts(vcpu) != SPURIOUS_VECTOR)
373 PSCB(vcpu,pending_interruption) = 1;
374 return IA64_NO_FAULT;
375 }
377 IA64FAULT vcpu_get_psr(VCPU *vcpu, UINT64 *pval)
378 {
379 REGS *regs = vcpu_regs(vcpu);
380 struct ia64_psr newpsr;
382 newpsr = *(struct ia64_psr *)&regs->cr_ipsr;
383 if (newpsr.cpl == 2) newpsr.cpl = 0;
384 if (!vcpu->vcpu_info->evtchn_upcall_mask) newpsr.i = 1;
385 else newpsr.i = 0;
386 if (PSCB(vcpu,interrupt_collection_enabled)) newpsr.ic = 1;
387 else newpsr.ic = 0;
388 if (PSCB(vcpu,metaphysical_mode)) newpsr.dt = 0;
389 else newpsr.dt = 1;
390 if (PSCB(vcpu,vpsr_pp)) newpsr.pp = 1;
391 else newpsr.pp = 0;
392 *pval = *(unsigned long *)&newpsr;
393 return IA64_NO_FAULT;
394 }
396 BOOLEAN vcpu_get_psr_ic(VCPU *vcpu)
397 {
398 return !!PSCB(vcpu,interrupt_collection_enabled);
399 }
401 BOOLEAN vcpu_get_psr_i(VCPU *vcpu)
402 {
403 return !vcpu->vcpu_info->evtchn_upcall_mask;
404 }
406 UINT64 vcpu_get_ipsr_int_state(VCPU *vcpu,UINT64 prevpsr)
407 {
408 UINT64 dcr = PSCBX(vcpu,dcr);
409 PSR psr;
411 //printf("*** vcpu_get_ipsr_int_state (0x%016lx)...\n",prevpsr);
412 psr.i64 = prevpsr;
413 psr.ia64_psr.be = 0; if (dcr & IA64_DCR_BE) psr.ia64_psr.be = 1;
414 psr.ia64_psr.pp = 0; if (dcr & IA64_DCR_PP) psr.ia64_psr.pp = 1;
415 psr.ia64_psr.ic = PSCB(vcpu,interrupt_collection_enabled);
416 psr.ia64_psr.i = !vcpu->vcpu_info->evtchn_upcall_mask;
417 psr.ia64_psr.bn = PSCB(vcpu,banknum);
418 psr.ia64_psr.dt = 1; psr.ia64_psr.it = 1; psr.ia64_psr.rt = 1;
419 if (psr.ia64_psr.cpl == 2) psr.ia64_psr.cpl = 0; // !!!! fool domain
420 // psr.pk = 1;
421 //printf("returns 0x%016lx...\n",psr.i64);
422 return psr.i64;
423 }
425 /**************************************************************************
426 VCPU control register access routines
427 **************************************************************************/
429 IA64FAULT vcpu_get_dcr(VCPU *vcpu, UINT64 *pval)
430 {
431 //verbose("vcpu_get_dcr: called @%p\n",PSCB(vcpu,iip));
432 // Reads of cr.dcr on Xen always have the sign bit set, so
433 // a domain can differentiate whether it is running on SP or not
434 *pval = PSCBX(vcpu,dcr) | 0x8000000000000000L;
435 return (IA64_NO_FAULT);
436 }
438 IA64FAULT vcpu_get_iva(VCPU *vcpu, UINT64 *pval)
439 {
440 if(VMX_DOMAIN(vcpu)){
441 *pval = PSCB(vcpu,iva) & ~0x7fffL;
442 }else{
443 *pval = PSCBX(vcpu,iva) & ~0x7fffL;
444 }
445 return (IA64_NO_FAULT);
446 }
448 IA64FAULT vcpu_get_pta(VCPU *vcpu, UINT64 *pval)
449 {
450 *pval = PSCB(vcpu,pta);
451 return (IA64_NO_FAULT);
452 }
454 IA64FAULT vcpu_get_ipsr(VCPU *vcpu, UINT64 *pval)
455 {
456 //REGS *regs = vcpu_regs(vcpu);
457 //*pval = regs->cr_ipsr;
458 *pval = PSCB(vcpu,ipsr);
459 return (IA64_NO_FAULT);
460 }
462 IA64FAULT vcpu_get_isr(VCPU *vcpu, UINT64 *pval)
463 {
464 *pval = PSCB(vcpu,isr);
465 return (IA64_NO_FAULT);
466 }
468 IA64FAULT vcpu_get_iip(VCPU *vcpu, UINT64 *pval)
469 {
470 //REGS *regs = vcpu_regs(vcpu);
471 //*pval = regs->cr_iip;
472 *pval = PSCB(vcpu,iip);
473 return (IA64_NO_FAULT);
474 }
476 IA64FAULT vcpu_get_ifa(VCPU *vcpu, UINT64 *pval)
477 {
478 PRIVOP_COUNT_ADDR(vcpu_regs(vcpu),_GET_IFA);
479 *pval = PSCB(vcpu,ifa);
480 return (IA64_NO_FAULT);
481 }
483 unsigned long vcpu_get_rr_ps(VCPU *vcpu,UINT64 vadr)
484 {
485 ia64_rr rr;
487 rr.rrval = PSCB(vcpu,rrs)[vadr>>61];
488 return(rr.ps);
489 }
491 unsigned long vcpu_get_rr_rid(VCPU *vcpu,UINT64 vadr)
492 {
493 ia64_rr rr;
495 rr.rrval = PSCB(vcpu,rrs)[vadr>>61];
496 return(rr.rid);
497 }
499 unsigned long vcpu_get_itir_on_fault(VCPU *vcpu, UINT64 ifa)
500 {
501 ia64_rr rr;
503 rr.rrval = 0;
504 rr.ps = vcpu_get_rr_ps(vcpu,ifa);
505 rr.rid = vcpu_get_rr_rid(vcpu,ifa);
506 return (rr.rrval);
507 }
510 IA64FAULT vcpu_get_itir(VCPU *vcpu, UINT64 *pval)
511 {
512 UINT64 val = PSCB(vcpu,itir);
513 *pval = val;
514 return (IA64_NO_FAULT);
515 }
517 IA64FAULT vcpu_get_iipa(VCPU *vcpu, UINT64 *pval)
518 {
519 UINT64 val = PSCB(vcpu,iipa);
520 // SP entry code does not save iipa yet nor does it get
521 // properly delivered in the pscb
522 // printf("*** vcpu_get_iipa: cr.iipa not fully implemented yet!!\n");
523 *pval = val;
524 return (IA64_NO_FAULT);
525 }
527 IA64FAULT vcpu_get_ifs(VCPU *vcpu, UINT64 *pval)
528 {
529 //PSCB(vcpu,ifs) = PSCB(vcpu)->regs.cr_ifs;
530 //*pval = PSCB(vcpu,regs).cr_ifs;
531 *pval = PSCB(vcpu,ifs);
532 PSCB(vcpu,incomplete_regframe) = 0;
533 return (IA64_NO_FAULT);
534 }
536 IA64FAULT vcpu_get_iim(VCPU *vcpu, UINT64 *pval)
537 {
538 UINT64 val = PSCB(vcpu,iim);
539 *pval = val;
540 return (IA64_NO_FAULT);
541 }
543 IA64FAULT vcpu_get_iha(VCPU *vcpu, UINT64 *pval)
544 {
545 PRIVOP_COUNT_ADDR(vcpu_regs(vcpu),_THASH);
546 *pval = PSCB(vcpu,iha);
547 return (IA64_NO_FAULT);
548 }
550 IA64FAULT vcpu_set_dcr(VCPU *vcpu, UINT64 val)
551 {
552 // Reads of cr.dcr on SP always have the sign bit set, so
553 // a domain can differentiate whether it is running on SP or not
554 // Thus, writes of DCR should ignore the sign bit
555 //verbose("vcpu_set_dcr: called\n");
556 PSCBX(vcpu,dcr) = val & ~0x8000000000000000L;
557 return (IA64_NO_FAULT);
558 }
560 IA64FAULT vcpu_set_iva(VCPU *vcpu, UINT64 val)
561 {
562 if(VMX_DOMAIN(vcpu)){
563 PSCB(vcpu,iva) = val & ~0x7fffL;
564 }else{
565 PSCBX(vcpu,iva) = val & ~0x7fffL;
566 }
567 return (IA64_NO_FAULT);
568 }
570 IA64FAULT vcpu_set_pta(VCPU *vcpu, UINT64 val)
571 {
572 if (val & IA64_PTA_LFMT) {
573 printf("*** No support for VHPT long format yet!!\n");
574 return (IA64_ILLOP_FAULT);
575 }
576 if (val & (0x3f<<9)) /* reserved fields */ return IA64_RSVDREG_FAULT;
577 if (val & 2) /* reserved fields */ return IA64_RSVDREG_FAULT;
578 PSCB(vcpu,pta) = val;
579 return IA64_NO_FAULT;
580 }
582 IA64FAULT vcpu_set_ipsr(VCPU *vcpu, UINT64 val)
583 {
584 PSCB(vcpu,ipsr) = val;
585 return IA64_NO_FAULT;
586 }
588 IA64FAULT vcpu_set_isr(VCPU *vcpu, UINT64 val)
589 {
590 PSCB(vcpu,isr) = val;
591 return IA64_NO_FAULT;
592 }
594 IA64FAULT vcpu_set_iip(VCPU *vcpu, UINT64 val)
595 {
596 PSCB(vcpu,iip) = val;
597 return IA64_NO_FAULT;
598 }
600 IA64FAULT vcpu_increment_iip(VCPU *vcpu)
601 {
602 REGS *regs = vcpu_regs(vcpu);
603 struct ia64_psr *ipsr = (struct ia64_psr *)&regs->cr_ipsr;
604 if (ipsr->ri == 2) { ipsr->ri=0; regs->cr_iip += 16; }
605 else ipsr->ri++;
606 return (IA64_NO_FAULT);
607 }
609 IA64FAULT vcpu_set_ifa(VCPU *vcpu, UINT64 val)
610 {
611 PSCB(vcpu,ifa) = val;
612 return IA64_NO_FAULT;
613 }
615 IA64FAULT vcpu_set_itir(VCPU *vcpu, UINT64 val)
616 {
617 PSCB(vcpu,itir) = val;
618 return IA64_NO_FAULT;
619 }
621 IA64FAULT vcpu_set_iipa(VCPU *vcpu, UINT64 val)
622 {
623 // SP entry code does not save iipa yet nor does it get
624 // properly delivered in the pscb
625 // printf("*** vcpu_set_iipa: cr.iipa not fully implemented yet!!\n");
626 PSCB(vcpu,iipa) = val;
627 return IA64_NO_FAULT;
628 }
630 IA64FAULT vcpu_set_ifs(VCPU *vcpu, UINT64 val)
631 {
632 //REGS *regs = vcpu_regs(vcpu);
633 PSCB(vcpu,ifs) = val;
634 return IA64_NO_FAULT;
635 }
637 IA64FAULT vcpu_set_iim(VCPU *vcpu, UINT64 val)
638 {
639 PSCB(vcpu,iim) = val;
640 return IA64_NO_FAULT;
641 }
643 IA64FAULT vcpu_set_iha(VCPU *vcpu, UINT64 val)
644 {
645 PSCB(vcpu,iha) = val;
646 return IA64_NO_FAULT;
647 }
649 /**************************************************************************
650 VCPU interrupt control register access routines
651 **************************************************************************/
653 void vcpu_pend_unspecified_interrupt(VCPU *vcpu)
654 {
655 PSCB(vcpu,pending_interruption) = 1;
656 }
658 void vcpu_pend_interrupt(VCPU *vcpu, UINT64 vector)
659 {
660 if (vector & ~0xff) {
661 printf("vcpu_pend_interrupt: bad vector\n");
662 return;
663 }
665 if (vcpu->arch.event_callback_ip) {
666 printf("Deprecated interface. Move to new event based solution\n");
667 return;
668 }
670 if ( VMX_DOMAIN(vcpu) ) {
671 set_bit(vector,VCPU(vcpu,irr));
672 } else {
673 set_bit(vector,PSCBX(vcpu,irr));
674 PSCB(vcpu,pending_interruption) = 1;
675 }
676 }
678 #define IA64_TPR_MMI 0x10000
679 #define IA64_TPR_MIC 0x000f0
681 /* checks to see if a VCPU has any unmasked pending interrupts
682 * if so, returns the highest, else returns SPURIOUS_VECTOR */
683 /* NOTE: Since this gets called from vcpu_get_ivr() and the
684 * semantics of "mov rx=cr.ivr" ignore the setting of the psr.i bit,
685 * this routine also ignores pscb.interrupt_delivery_enabled
686 * and this must be checked independently; see vcpu_deliverable interrupts() */
687 UINT64 vcpu_check_pending_interrupts(VCPU *vcpu)
688 {
689 UINT64 *p, *r, bits, bitnum, mask, i, vector;
691 if (vcpu->arch.event_callback_ip)
692 return SPURIOUS_VECTOR;
694 /* Always check pending event, since guest may just ack the
695 * event injection without handle. Later guest may throw out
696 * the event itself.
697 */
698 check_start:
699 if (event_pending(vcpu) &&
700 !test_bit(vcpu->domain->shared_info->arch.evtchn_vector,
701 &PSCBX(vcpu, insvc[0])))
702 vcpu_pend_interrupt(vcpu, vcpu->domain->shared_info->arch.evtchn_vector);
704 p = &PSCBX(vcpu,irr[3]);
705 r = &PSCBX(vcpu,insvc[3]);
706 for (i = 3; ; p--, r--, i--) {
707 bits = *p ;
708 if (bits) break; // got a potential interrupt
709 if (*r) {
710 // nothing in this word which is pending+inservice
711 // but there is one inservice which masks lower
712 return SPURIOUS_VECTOR;
713 }
714 if (i == 0) {
715 // checked all bits... nothing pending+inservice
716 return SPURIOUS_VECTOR;
717 }
718 }
719 // have a pending,deliverable interrupt... see if it is masked
720 bitnum = ia64_fls(bits);
721 //printf("XXXXXXX vcpu_check_pending_interrupts: got bitnum=%p...\n",bitnum);
722 vector = bitnum+(i*64);
723 mask = 1L << bitnum;
724 /* sanity check for guest timer interrupt */
725 if (vector == (PSCB(vcpu,itv) & 0xff)) {
726 uint64_t now = ia64_get_itc();
727 if (now < PSCBX(vcpu,domain_itm)) {
728 // printk("Ooops, pending guest timer before its due\n");
729 PSCBX(vcpu,irr[i]) &= ~mask;
730 goto check_start;
731 }
732 }
733 //printf("XXXXXXX vcpu_check_pending_interrupts: got vector=%p...\n",vector);
734 if (*r >= mask) {
735 // masked by equal inservice
736 //printf("but masked by equal inservice\n");
737 return SPURIOUS_VECTOR;
738 }
739 if (PSCB(vcpu,tpr) & IA64_TPR_MMI) {
740 // tpr.mmi is set
741 //printf("but masked by tpr.mmi\n");
742 return SPURIOUS_VECTOR;
743 }
744 if (((PSCB(vcpu,tpr) & IA64_TPR_MIC) + 15) >= vector) {
745 //tpr.mic masks class
746 //printf("but masked by tpr.mic\n");
747 return SPURIOUS_VECTOR;
748 }
750 //printf("returned to caller\n");
751 return vector;
752 }
754 UINT64 vcpu_deliverable_interrupts(VCPU *vcpu)
755 {
756 return (vcpu_get_psr_i(vcpu) &&
757 vcpu_check_pending_interrupts(vcpu) != SPURIOUS_VECTOR);
758 }
760 UINT64 vcpu_deliverable_timer(VCPU *vcpu)
761 {
762 return (vcpu_get_psr_i(vcpu) &&
763 vcpu_check_pending_interrupts(vcpu) == PSCB(vcpu,itv));
764 }
766 IA64FAULT vcpu_get_lid(VCPU *vcpu, UINT64 *pval)
767 {
768 /* Use real LID for domain0 until vIOSAPIC is present.
769 Use EID=0, ID=vcpu_id for domU. */
770 if (vcpu->domain == dom0)
771 *pval = ia64_getreg(_IA64_REG_CR_LID);
772 else
773 *pval = vcpu->vcpu_id << 24;
774 return IA64_NO_FAULT;
775 }
777 IA64FAULT vcpu_get_ivr(VCPU *vcpu, UINT64 *pval)
778 {
779 int i;
780 UINT64 vector, mask;
782 #define HEARTBEAT_FREQ 16 // period in seconds
783 #ifdef HEARTBEAT_FREQ
784 #define N_DOMS 16 // period in seconds
785 #if 0
786 static long count[N_DOMS] = { 0 };
787 #endif
788 static long nonclockcount[N_DOMS] = { 0 };
789 unsigned domid = vcpu->domain->domain_id;
790 #endif
791 #ifdef IRQ_DEBUG
792 static char firstivr = 1;
793 static char firsttime[256];
794 if (firstivr) {
795 int i;
796 for (i=0;i<256;i++) firsttime[i]=1;
797 firstivr=0;
798 }
799 #endif
801 vector = vcpu_check_pending_interrupts(vcpu);
802 if (vector == SPURIOUS_VECTOR) {
803 PSCB(vcpu,pending_interruption) = 0;
804 *pval = vector;
805 return IA64_NO_FAULT;
806 }
807 #ifdef HEARTBEAT_FREQ
808 if (domid >= N_DOMS) domid = N_DOMS-1;
809 #if 0
810 if (vector == (PSCB(vcpu,itv) & 0xff)) {
811 if (!(++count[domid] & ((HEARTBEAT_FREQ*1024)-1))) {
812 printf("Dom%d heartbeat... ticks=%lx,nonticks=%lx\n",
813 domid, count[domid], nonclockcount[domid]);
814 //count[domid] = 0;
815 //dump_runq();
816 }
817 }
818 #endif
819 else nonclockcount[domid]++;
820 #endif
821 // now have an unmasked, pending, deliverable vector!
822 // getting ivr has "side effects"
823 #ifdef IRQ_DEBUG
824 if (firsttime[vector]) {
825 printf("*** First get_ivr on vector=%lu,itc=%lx\n",
826 vector,ia64_get_itc());
827 firsttime[vector]=0;
828 }
829 #endif
830 /* if delivering a timer interrupt, remember domain_itm, which
831 * needs to be done before clearing irr
832 */
833 if (vector == (PSCB(vcpu,itv) & 0xff)) {
834 PSCBX(vcpu,domain_itm_last) = PSCBX(vcpu,domain_itm);
835 }
837 i = vector >> 6;
838 mask = 1L << (vector & 0x3f);
839 //printf("ZZZZZZ vcpu_get_ivr: setting insvc mask for vector %lu\n",vector);
840 PSCBX(vcpu,insvc[i]) |= mask;
841 PSCBX(vcpu,irr[i]) &= ~mask;
842 //PSCB(vcpu,pending_interruption)--;
843 *pval = vector;
844 return IA64_NO_FAULT;
845 }
847 IA64FAULT vcpu_get_tpr(VCPU *vcpu, UINT64 *pval)
848 {
849 *pval = PSCB(vcpu,tpr);
850 return (IA64_NO_FAULT);
851 }
853 IA64FAULT vcpu_get_eoi(VCPU *vcpu, UINT64 *pval)
854 {
855 *pval = 0L; // reads of eoi always return 0
856 return (IA64_NO_FAULT);
857 }
859 IA64FAULT vcpu_get_irr0(VCPU *vcpu, UINT64 *pval)
860 {
861 *pval = PSCBX(vcpu, irr[0]);
862 return (IA64_NO_FAULT);
863 }
865 IA64FAULT vcpu_get_irr1(VCPU *vcpu, UINT64 *pval)
866 {
867 *pval = PSCBX(vcpu, irr[1]);
868 return (IA64_NO_FAULT);
869 }
871 IA64FAULT vcpu_get_irr2(VCPU *vcpu, UINT64 *pval)
872 {
873 *pval = PSCBX(vcpu, irr[2]);
874 return (IA64_NO_FAULT);
875 }
877 IA64FAULT vcpu_get_irr3(VCPU *vcpu, UINT64 *pval)
878 {
879 *pval = PSCBX(vcpu, irr[3]);
880 return (IA64_NO_FAULT);
881 }
883 IA64FAULT vcpu_get_itv(VCPU *vcpu, UINT64 *pval)
884 {
885 *pval = PSCB(vcpu,itv);
886 return (IA64_NO_FAULT);
887 }
889 IA64FAULT vcpu_get_pmv(VCPU *vcpu, UINT64 *pval)
890 {
891 *pval = PSCB(vcpu,pmv);
892 return (IA64_NO_FAULT);
893 }
895 IA64FAULT vcpu_get_cmcv(VCPU *vcpu, UINT64 *pval)
896 {
897 *pval = PSCB(vcpu,cmcv);
898 return (IA64_NO_FAULT);
899 }
901 IA64FAULT vcpu_get_lrr0(VCPU *vcpu, UINT64 *pval)
902 {
903 // fix this when setting values other than m-bit is supported
904 printf("vcpu_get_lrr0: Unmasked interrupts unsupported\n");
905 *pval = (1L << 16);
906 return (IA64_NO_FAULT);
907 }
909 IA64FAULT vcpu_get_lrr1(VCPU *vcpu, UINT64 *pval)
910 {
911 // fix this when setting values other than m-bit is supported
912 printf("vcpu_get_lrr1: Unmasked interrupts unsupported\n");
913 *pval = (1L << 16);
914 return (IA64_NO_FAULT);
915 }
917 IA64FAULT vcpu_set_lid(VCPU *vcpu, UINT64 val)
918 {
919 printf("vcpu_set_lid: Setting cr.lid is unsupported\n");
920 return (IA64_ILLOP_FAULT);
921 }
923 IA64FAULT vcpu_set_tpr(VCPU *vcpu, UINT64 val)
924 {
925 if (val & 0xff00) return IA64_RSVDREG_FAULT;
926 PSCB(vcpu,tpr) = val;
927 /* This can unmask interrupts. */
928 if (vcpu_check_pending_interrupts(vcpu) != SPURIOUS_VECTOR)
929 PSCB(vcpu,pending_interruption) = 1;
930 return (IA64_NO_FAULT);
931 }
933 IA64FAULT vcpu_set_eoi(VCPU *vcpu, UINT64 val)
934 {
935 UINT64 *p, bits, vec, bitnum;
936 int i;
938 p = &PSCBX(vcpu,insvc[3]);
939 for (i = 3; (i >= 0) && !(bits = *p); i--, p--);
940 if (i < 0) {
941 printf("Trying to EOI interrupt when none are in-service.\n");
942 return IA64_NO_FAULT;
943 }
944 bitnum = ia64_fls(bits);
945 vec = bitnum + (i*64);
946 /* clear the correct bit */
947 bits &= ~(1L << bitnum);
948 *p = bits;
949 /* clearing an eoi bit may unmask another pending interrupt... */
950 if (!vcpu->vcpu_info->evtchn_upcall_mask) { // but only if enabled...
951 // worry about this later... Linux only calls eoi
952 // with interrupts disabled
953 printf("Trying to EOI interrupt with interrupts enabled\n");
954 }
955 if (vcpu_check_pending_interrupts(vcpu) != SPURIOUS_VECTOR)
956 PSCB(vcpu,pending_interruption) = 1;
957 //printf("YYYYY vcpu_set_eoi: Successful\n");
958 return (IA64_NO_FAULT);
959 }
961 IA64FAULT vcpu_set_lrr0(VCPU *vcpu, UINT64 val)
962 {
963 if (!(val & (1L << 16))) {
964 printf("vcpu_set_lrr0: Unmasked interrupts unsupported\n");
965 return (IA64_ILLOP_FAULT);
966 }
967 // no place to save this state but nothing to do anyway
968 return (IA64_NO_FAULT);
969 }
971 IA64FAULT vcpu_set_lrr1(VCPU *vcpu, UINT64 val)
972 {
973 if (!(val & (1L << 16))) {
974 printf("vcpu_set_lrr0: Unmasked interrupts unsupported\n");
975 return (IA64_ILLOP_FAULT);
976 }
977 // no place to save this state but nothing to do anyway
978 return (IA64_NO_FAULT);
979 }
981 IA64FAULT vcpu_set_itv(VCPU *vcpu, UINT64 val)
982 {
983 /* Check reserved fields. */
984 if (val & 0xef00)
985 return (IA64_ILLOP_FAULT);
986 PSCB(vcpu,itv) = val;
987 if (val & 0x10000) {
988 /* Disable itm. */
989 PSCBX(vcpu,domain_itm) = 0;
990 }
991 else vcpu_set_next_timer(vcpu);
992 return (IA64_NO_FAULT);
993 }
995 IA64FAULT vcpu_set_pmv(VCPU *vcpu, UINT64 val)
996 {
997 if (val & 0xef00) /* reserved fields */ return IA64_RSVDREG_FAULT;
998 PSCB(vcpu,pmv) = val;
999 return (IA64_NO_FAULT);
1002 IA64FAULT vcpu_set_cmcv(VCPU *vcpu, UINT64 val)
1004 if (val & 0xef00) /* reserved fields */ return IA64_RSVDREG_FAULT;
1005 PSCB(vcpu,cmcv) = val;
1006 return (IA64_NO_FAULT);
1009 /**************************************************************************
1010 VCPU temporary register access routines
1011 **************************************************************************/
1012 UINT64 vcpu_get_tmp(VCPU *vcpu, UINT64 index)
1014 if (index > 7) return 0;
1015 return PSCB(vcpu,tmp[index]);
1018 void vcpu_set_tmp(VCPU *vcpu, UINT64 index, UINT64 val)
1020 if (index <= 7) PSCB(vcpu,tmp[index]) = val;
1023 /**************************************************************************
1024 Interval timer routines
1025 **************************************************************************/
1027 BOOLEAN vcpu_timer_disabled(VCPU *vcpu)
1029 UINT64 itv = PSCB(vcpu,itv);
1030 return(!itv || !!(itv & 0x10000));
1033 BOOLEAN vcpu_timer_inservice(VCPU *vcpu)
1035 UINT64 itv = PSCB(vcpu,itv);
1036 return (test_bit(itv, PSCBX(vcpu,insvc)));
1039 BOOLEAN vcpu_timer_expired(VCPU *vcpu)
1041 unsigned long domain_itm = PSCBX(vcpu,domain_itm);
1042 unsigned long now = ia64_get_itc();
1044 if (!domain_itm) return FALSE;
1045 if (now < domain_itm) return FALSE;
1046 if (vcpu_timer_disabled(vcpu)) return FALSE;
1047 return TRUE;
1050 void vcpu_safe_set_itm(unsigned long val)
1052 unsigned long epsilon = 100;
1053 unsigned long flags;
1054 UINT64 now = ia64_get_itc();
1056 local_irq_save(flags);
1057 while (1) {
1058 //printf("*** vcpu_safe_set_itm: Setting itm to %lx, itc=%lx\n",val,now);
1059 ia64_set_itm(val);
1060 if (val > (now = ia64_get_itc())) break;
1061 val = now + epsilon;
1062 epsilon <<= 1;
1064 local_irq_restore(flags);
1067 void vcpu_set_next_timer(VCPU *vcpu)
1069 UINT64 d = PSCBX(vcpu,domain_itm);
1070 //UINT64 s = PSCBX(vcpu,xen_itm);
1071 UINT64 s = local_cpu_data->itm_next;
1072 UINT64 now = ia64_get_itc();
1074 /* gloss over the wraparound problem for now... we know it exists
1075 * but it doesn't matter right now */
1077 if (is_idle_domain(vcpu->domain)) {
1078 // printf("****** vcpu_set_next_timer called during idle!!\n");
1079 vcpu_safe_set_itm(s);
1080 return;
1082 //s = PSCBX(vcpu,xen_itm);
1083 if (d && (d > now) && (d < s)) {
1084 vcpu_safe_set_itm(d);
1085 //using_domain_as_itm++;
1087 else {
1088 vcpu_safe_set_itm(s);
1089 //using_xen_as_itm++;
1093 IA64FAULT vcpu_set_itm(VCPU *vcpu, UINT64 val)
1095 //UINT now = ia64_get_itc();
1097 //if (val < now) val = now + 1000;
1098 //printf("*** vcpu_set_itm: called with %lx\n",val);
1099 PSCBX(vcpu,domain_itm) = val;
1100 vcpu_set_next_timer(vcpu);
1101 return (IA64_NO_FAULT);
1104 IA64FAULT vcpu_set_itc(VCPU *vcpu, UINT64 val)
1106 #define DISALLOW_SETTING_ITC_FOR_NOW
1107 #ifdef DISALLOW_SETTING_ITC_FOR_NOW
1108 static int did_print;
1109 if (!did_print) {
1110 printf("vcpu_set_itc: Setting ar.itc is currently disabled\n");
1111 printf("(this message is only displayed one)\n");
1112 did_print = 1;
1114 #else
1115 UINT64 oldnow = ia64_get_itc();
1116 UINT64 olditm = PSCBX(vcpu,domain_itm);
1117 unsigned long d = olditm - oldnow;
1118 unsigned long x = local_cpu_data->itm_next - oldnow;
1120 UINT64 newnow = val, min_delta;
1122 local_irq_disable();
1123 if (olditm) {
1124 printf("**** vcpu_set_itc(%lx): vitm changed to %lx\n",val,newnow+d);
1125 PSCBX(vcpu,domain_itm) = newnow + d;
1127 local_cpu_data->itm_next = newnow + x;
1128 d = PSCBX(vcpu,domain_itm);
1129 x = local_cpu_data->itm_next;
1131 ia64_set_itc(newnow);
1132 if (d && (d > newnow) && (d < x)) {
1133 vcpu_safe_set_itm(d);
1134 //using_domain_as_itm++;
1136 else {
1137 vcpu_safe_set_itm(x);
1138 //using_xen_as_itm++;
1140 local_irq_enable();
1141 #endif
1142 return (IA64_NO_FAULT);
1145 IA64FAULT vcpu_get_itm(VCPU *vcpu, UINT64 *pval)
1147 //FIXME: Implement this
1148 printf("vcpu_get_itm: Getting cr.itm is unsupported... continuing\n");
1149 return (IA64_NO_FAULT);
1150 //return (IA64_ILLOP_FAULT);
1153 IA64FAULT vcpu_get_itc(VCPU *vcpu, UINT64 *pval)
1155 //TODO: Implement this
1156 printf("vcpu_get_itc: Getting ar.itc is unsupported\n");
1157 return (IA64_ILLOP_FAULT);
1160 void vcpu_pend_timer(VCPU *vcpu)
1162 UINT64 itv = PSCB(vcpu,itv) & 0xff;
1164 if (vcpu_timer_disabled(vcpu)) return;
1165 //if (vcpu_timer_inservice(vcpu)) return;
1166 if (PSCBX(vcpu,domain_itm_last) == PSCBX(vcpu,domain_itm)) {
1167 // already delivered an interrupt for this so
1168 // don't deliver another
1169 return;
1171 if (vcpu->arch.event_callback_ip) {
1172 /* A small window may occur when injecting vIRQ while related
1173 * handler has not been registered. Don't fire in such case.
1174 */
1175 if (vcpu->virq_to_evtchn[VIRQ_ITC]) {
1176 send_guest_vcpu_virq(vcpu, VIRQ_ITC);
1177 PSCBX(vcpu, domain_itm_last) = PSCBX(vcpu, domain_itm);
1179 } else
1180 vcpu_pend_interrupt(vcpu, itv);
1183 // returns true if ready to deliver a timer interrupt too early
1184 UINT64 vcpu_timer_pending_early(VCPU *vcpu)
1186 UINT64 now = ia64_get_itc();
1187 UINT64 itm = PSCBX(vcpu,domain_itm);
1189 if (vcpu_timer_disabled(vcpu)) return 0;
1190 if (!itm) return 0;
1191 return (vcpu_deliverable_timer(vcpu) && (now < itm));
1194 /**************************************************************************
1195 Privileged operation emulation routines
1196 **************************************************************************/
1198 static void
1199 vcpu_force_tlb_miss(VCPU* vcpu, UINT64 ifa)
1201 PSCB(vcpu, ifa) = ifa;
1202 PSCB(vcpu, itir) = vcpu_get_itir_on_fault(vcpu, ifa);
1203 vcpu_thash(current, ifa, &PSCB(current, iha));
1206 IA64FAULT vcpu_force_inst_miss(VCPU *vcpu, UINT64 ifa)
1208 vcpu_force_tlb_miss(vcpu, ifa);
1209 return (vcpu_get_rr_ve(vcpu, ifa)? IA64_INST_TLB_VECTOR: IA64_ALT_INST_TLB_VECTOR);
1212 IA64FAULT vcpu_force_data_miss(VCPU *vcpu, UINT64 ifa)
1214 vcpu_force_tlb_miss(vcpu, ifa);
1215 return (vcpu_get_rr_ve(vcpu, ifa)? IA64_DATA_TLB_VECTOR: IA64_ALT_DATA_TLB_VECTOR);
1218 IA64FAULT vcpu_rfi(VCPU *vcpu)
1220 // TODO: Only allowed for current vcpu
1221 PSR psr;
1222 UINT64 int_enable, regspsr = 0;
1223 UINT64 ifs;
1224 REGS *regs = vcpu_regs(vcpu);
1225 extern void dorfirfi(void);
1227 psr.i64 = PSCB(vcpu,ipsr);
1228 if (psr.ia64_psr.cpl < 3) psr.ia64_psr.cpl = 2;
1229 int_enable = psr.ia64_psr.i;
1230 if (psr.ia64_psr.ic) PSCB(vcpu,interrupt_collection_enabled) = 1;
1231 if (psr.ia64_psr.dt && psr.ia64_psr.rt && psr.ia64_psr.it) vcpu_set_metaphysical_mode(vcpu,FALSE);
1232 else vcpu_set_metaphysical_mode(vcpu,TRUE);
1233 psr.ia64_psr.ic = 1; psr.ia64_psr.i = 1;
1234 psr.ia64_psr.dt = 1; psr.ia64_psr.rt = 1; psr.ia64_psr.it = 1;
1235 psr.ia64_psr.bn = 1;
1236 //psr.pk = 1; // checking pkeys shouldn't be a problem but seems broken
1237 if (psr.ia64_psr.be) {
1238 printf("*** DOMAIN TRYING TO TURN ON BIG-ENDIAN!!!\n");
1239 return (IA64_ILLOP_FAULT);
1241 PSCB(vcpu,incomplete_regframe) = 0; // is this necessary?
1242 ifs = PSCB(vcpu,ifs);
1243 //if ((ifs & regs->cr_ifs & 0x8000000000000000L) && ifs != regs->cr_ifs) {
1244 //if ((ifs & 0x8000000000000000L) && ifs != regs->cr_ifs) {
1245 if (ifs & regs->cr_ifs & 0x8000000000000000L) {
1246 // TODO: validate PSCB(vcpu,iip)
1247 // TODO: PSCB(vcpu,ipsr) = psr;
1248 PSCB(vcpu,ipsr) = psr.i64;
1249 // now set up the trampoline
1250 regs->cr_iip = *(unsigned long *)dorfirfi; // function pointer!!
1251 __asm__ __volatile ("mov %0=psr;;":"=r"(regspsr)::"memory");
1252 regs->cr_ipsr = regspsr & ~(IA64_PSR_I | IA64_PSR_IC | IA64_PSR_BN);
1254 else {
1255 regs->cr_ipsr = psr.i64;
1256 regs->cr_iip = PSCB(vcpu,iip);
1258 PSCB(vcpu,interrupt_collection_enabled) = 1;
1259 vcpu_bsw1(vcpu);
1260 vcpu->vcpu_info->evtchn_upcall_mask = !int_enable;
1261 return (IA64_NO_FAULT);
1264 IA64FAULT vcpu_cover(VCPU *vcpu)
1266 // TODO: Only allowed for current vcpu
1267 REGS *regs = vcpu_regs(vcpu);
1269 if (!PSCB(vcpu,interrupt_collection_enabled)) {
1270 if (!PSCB(vcpu,incomplete_regframe))
1271 PSCB(vcpu,ifs) = regs->cr_ifs;
1272 else PSCB(vcpu,incomplete_regframe) = 0;
1274 regs->cr_ifs = 0;
1275 return (IA64_NO_FAULT);
1278 IA64FAULT vcpu_thash(VCPU *vcpu, UINT64 vadr, UINT64 *pval)
1280 UINT64 pta = PSCB(vcpu,pta);
1281 UINT64 pta_sz = (pta & IA64_PTA_SZ(0x3f)) >> IA64_PTA_SZ_BIT;
1282 UINT64 pta_base = pta & ~((1UL << IA64_PTA_BASE_BIT)-1);
1283 UINT64 Mask = (1L << pta_sz) - 1;
1284 UINT64 Mask_60_15 = (Mask >> 15) & 0x3fffffffffff;
1285 UINT64 compMask_60_15 = ~Mask_60_15;
1286 UINT64 rr_ps = vcpu_get_rr_ps(vcpu,vadr);
1287 UINT64 VHPT_offset = (vadr >> rr_ps) << 3;
1288 UINT64 VHPT_addr1 = vadr & 0xe000000000000000L;
1289 UINT64 VHPT_addr2a =
1290 ((pta_base >> 15) & 0x3fffffffffff) & compMask_60_15;
1291 UINT64 VHPT_addr2b =
1292 ((VHPT_offset >> 15) & 0x3fffffffffff) & Mask_60_15;
1293 UINT64 VHPT_addr3 = VHPT_offset & 0x7fff;
1294 UINT64 VHPT_addr = VHPT_addr1 | ((VHPT_addr2a | VHPT_addr2b) << 15) |
1295 VHPT_addr3;
1297 //verbose("vcpu_thash: vadr=%p, VHPT_addr=%p\n",vadr,VHPT_addr);
1298 *pval = VHPT_addr;
1299 return (IA64_NO_FAULT);
1302 IA64FAULT vcpu_ttag(VCPU *vcpu, UINT64 vadr, UINT64 *padr)
1304 printf("vcpu_ttag: ttag instruction unsupported\n");
1305 return (IA64_ILLOP_FAULT);
1308 int warn_region0_address = 0; // FIXME later: tie to a boot parameter?
1310 /* Return TRUE iff [b1,e1] and [b2,e2] partially or fully overlaps. */
1311 static inline int range_overlap (u64 b1, u64 e1, u64 b2, u64 e2)
1313 return (b1 <= e2) && (e1 >= b2);
1316 /* Crash domain if [base, base + page_size] and Xen virtual space overlaps.
1317 Note: LSBs of base inside page_size are ignored. */
1318 static inline void
1319 check_xen_space_overlap (const char *func, u64 base, u64 page_size)
1321 /* Mask LSBs of base. */
1322 base &= ~(page_size - 1);
1324 /* FIXME: ideally an MCA should be generated... */
1325 if (range_overlap (HYPERVISOR_VIRT_START, HYPERVISOR_VIRT_END,
1326 base, base + page_size))
1327 panic_domain (NULL, "%s on Xen virtual space (%lx)\n",
1328 func, base);
1331 // FIXME: also need to check && (!trp->key || vcpu_pkr_match(trp->key))
1332 static inline int vcpu_match_tr_entry_no_p(TR_ENTRY *trp, UINT64 ifa, UINT64 rid)
1334 return trp->rid == rid
1335 && ifa >= trp->vadr
1336 && ifa <= (trp->vadr + (1L << trp->ps) - 1);
1339 static inline int vcpu_match_tr_entry(TR_ENTRY *trp, UINT64 ifa, UINT64 rid)
1341 return trp->pte.p && vcpu_match_tr_entry_no_p(trp, ifa, rid);
1344 static inline int
1345 vcpu_match_tr_entry_range(TR_ENTRY *trp, UINT64 rid, u64 b, u64 e)
1347 return trp->rid == rid
1348 && trp->pte.p
1349 && range_overlap (b, e,
1350 trp->vadr, trp->vadr + (1L << trp->ps) - 1);
1354 static TR_ENTRY*
1355 vcpu_tr_lookup(VCPU* vcpu, unsigned long va, UINT64 rid, BOOLEAN is_data)
1357 unsigned char* regions;
1358 TR_ENTRY *trp;
1359 int tr_max;
1360 int i;
1362 if (is_data) {
1363 // data
1364 regions = &vcpu->arch.dtr_regions;
1365 trp = vcpu->arch.dtrs;
1366 tr_max = sizeof(vcpu->arch.dtrs)/sizeof(vcpu->arch.dtrs[0]);
1367 } else {
1368 // instruction
1369 regions = &vcpu->arch.itr_regions;
1370 trp = vcpu->arch.itrs;
1371 tr_max = sizeof(vcpu->arch.itrs)/sizeof(vcpu->arch.itrs[0]);
1374 if (!vcpu_quick_region_check(*regions, va)) {
1375 return NULL;
1377 for (i = 0; i < tr_max; i++, trp++) {
1378 if (vcpu_match_tr_entry(trp, va, rid)) {
1379 return trp;
1382 return NULL;
1385 // return value
1386 // 0: failure
1387 // 1: success
1388 int
1389 vcpu_get_domain_bundle(VCPU* vcpu, REGS* regs, UINT64 gip, IA64_BUNDLE* bundle)
1391 UINT64 gpip;// guest pseudo phyiscal ip
1392 unsigned long vaddr;
1393 struct page_info* page;
1395 again:
1396 #if 0
1397 // Currently xen doesn't track psr.it bits.
1398 // it assumes always psr.it = 1.
1399 if (!(VCPU(vcpu, vpsr) & IA64_PSR_IT)) {
1400 gpip = gip;
1401 } else
1402 #endif
1404 unsigned long region = REGION_NUMBER(gip);
1405 unsigned long rr = PSCB(vcpu, rrs)[region];
1406 unsigned long rid = rr & RR_RID_MASK;
1407 BOOLEAN swap_rr0;
1408 TR_ENTRY* trp;
1410 // vcpu->arch.{i, d}tlb are volatile,
1411 // copy its value to the variable, tr, before use.
1412 TR_ENTRY tr;
1414 trp = vcpu_tr_lookup(vcpu, gip, rid, 0);
1415 if (trp != NULL) {
1416 tr = *trp;
1417 goto found;
1419 // When it failed to get a bundle, itlb miss is reflected.
1420 // Last itc.i value is cached to PSCBX(vcpu, itlb).
1421 tr = PSCBX(vcpu, itlb);
1422 if (vcpu_match_tr_entry(&tr, gip, rid)) {
1423 //DPRINTK("%s gip 0x%lx gpip 0x%lx\n", __func__, gip, gpip);
1424 goto found;
1426 trp = vcpu_tr_lookup(vcpu, gip, rid, 1);
1427 if (trp != NULL) {
1428 tr = *trp;
1429 goto found;
1431 #if 0
1432 tr = PSCBX(vcpu, dtlb);
1433 if (vcpu_match_tr_entry(&tr, gip, rid)) {
1434 goto found;
1436 #endif
1438 // try to access gip with guest virtual address
1439 // This may cause tlb miss. see vcpu_translate(). Be careful!
1440 swap_rr0 = (!region && PSCB(vcpu, metaphysical_mode));
1441 if (swap_rr0) {
1442 set_one_rr(0x0, PSCB(vcpu, rrs[0]));
1444 *bundle = __get_domain_bundle(gip);
1445 if (swap_rr0) {
1446 set_metaphysical_rr0();
1448 if (bundle->i64[0] == 0 && bundle->i64[1] == 0) {
1449 DPRINTK("%s gip 0x%lx\n", __func__, gip);
1450 return 0;
1452 return 1;
1454 found:
1455 gpip = ((tr.pte.ppn >> (tr.ps - 12)) << tr.ps) |
1456 (gip & ((1 << tr.ps) - 1));
1459 vaddr = (unsigned long)domain_mpa_to_imva(vcpu->domain, gpip);
1460 page = virt_to_page(vaddr);
1461 if (get_page(page, vcpu->domain) == 0) {
1462 if (page_get_owner(page) != vcpu->domain) {
1463 // This page might be a page granted by another
1464 // domain.
1465 panic_domain(regs,
1466 "domain tries to execute foreign domain "
1467 "page which might be mapped by grant "
1468 "table.\n");
1470 goto again;
1472 *bundle = *((IA64_BUNDLE*)vaddr);
1473 put_page(page);
1474 return 1;
1477 IA64FAULT vcpu_translate(VCPU *vcpu, UINT64 address, BOOLEAN is_data, UINT64 *pteval, UINT64 *itir, UINT64 *iha)
1479 unsigned long region = address >> 61;
1480 unsigned long pta, rid, rr;
1481 union pte_flags pte;
1482 TR_ENTRY *trp;
1484 if (PSCB(vcpu,metaphysical_mode) && !(!is_data && region)) {
1485 // dom0 may generate an uncacheable physical address (msb=1)
1486 if (region && ((region != 4) || (vcpu->domain != dom0))) {
1487 // FIXME: This seems to happen even though it shouldn't. Need to track
1488 // this down, but since it has been apparently harmless, just flag it for now
1489 // panic_domain(vcpu_regs(vcpu),
1491 /*
1492 * Guest may execute itc.d and rfi with psr.dt=0
1493 * When VMM try to fetch opcode, tlb miss may happen,
1494 * At this time PSCB(vcpu,metaphysical_mode)=1,
1495 * region=5,VMM need to handle this tlb miss as if
1496 * PSCB(vcpu,metaphysical_mode)=0
1497 */
1498 printk("vcpu_translate: bad physical address: 0x%lx at %lx\n",
1499 address, vcpu_regs (vcpu)->cr_iip);
1501 } else {
1502 *pteval = (address & _PAGE_PPN_MASK) | __DIRTY_BITS |
1503 _PAGE_PL_2 | _PAGE_AR_RWX;
1504 *itir = PAGE_SHIFT << 2;
1505 phys_translate_count++;
1506 return IA64_NO_FAULT;
1509 else if (!region && warn_region0_address) {
1510 REGS *regs = vcpu_regs(vcpu);
1511 unsigned long viip = PSCB(vcpu,iip);
1512 unsigned long vipsr = PSCB(vcpu,ipsr);
1513 unsigned long iip = regs->cr_iip;
1514 unsigned long ipsr = regs->cr_ipsr;
1515 printk("vcpu_translate: bad address 0x%lx, viip=0x%lx, vipsr=0x%lx, iip=0x%lx, ipsr=0x%lx continuing\n",
1516 address, viip, vipsr, iip, ipsr);
1519 rr = PSCB(vcpu,rrs)[region];
1520 rid = rr & RR_RID_MASK;
1521 if (is_data) {
1522 trp = vcpu_tr_lookup(vcpu, address, rid, 1);
1523 if (trp != NULL) {
1524 *pteval = trp->pte.val;
1525 *itir = trp->itir;
1526 tr_translate_count++;
1527 return IA64_NO_FAULT;
1530 // FIXME?: check itr's for data accesses too, else bad things happen?
1531 /* else */ {
1532 trp = vcpu_tr_lookup(vcpu, address, rid, 0);
1533 if (trp != NULL) {
1534 *pteval = trp->pte.val;
1535 *itir = trp->itir;
1536 tr_translate_count++;
1537 return IA64_NO_FAULT;
1541 /* check 1-entry TLB */
1542 // FIXME?: check dtlb for inst accesses too, else bad things happen?
1543 trp = &vcpu->arch.dtlb;
1544 pte = trp->pte;
1545 if (/* is_data && */ pte.p
1546 && vcpu_match_tr_entry_no_p(trp,address,rid)) {
1547 *pteval = pte.val;
1548 *itir = trp->itir;
1549 dtlb_translate_count++;
1550 return IA64_USE_TLB;
1553 /* check guest VHPT */
1554 pta = PSCB(vcpu,pta);
1555 if (pta & IA64_PTA_VF) { /* long format VHPT - not implemented */
1556 panic_domain(vcpu_regs(vcpu),"can't do long format VHPT\n");
1557 //return (is_data ? IA64_DATA_TLB_VECTOR:IA64_INST_TLB_VECTOR);
1560 *itir = rr & (RR_RID_MASK | RR_PS_MASK);
1561 // note: architecturally, iha is optionally set for alt faults but
1562 // xenlinux depends on it so should document it as part of PV interface
1563 vcpu_thash(vcpu, address, iha);
1564 if (!(rr & RR_VE_MASK) || !(pta & IA64_PTA_VE))
1565 return (is_data ? IA64_ALT_DATA_TLB_VECTOR : IA64_ALT_INST_TLB_VECTOR);
1567 /* avoid recursively walking (short format) VHPT */
1568 if (((address ^ pta) & ((itir_mask(pta) << 3) >> 3)) == 0)
1569 return (is_data ? IA64_DATA_TLB_VECTOR : IA64_INST_TLB_VECTOR);
1571 if (!__access_ok (*iha)
1572 || __copy_from_user(&pte, (void *)(*iha), sizeof(pte)) != 0)
1573 // virtual VHPT walker "missed" in TLB
1574 return IA64_VHPT_FAULT;
1576 /*
1577 * Optimisation: this VHPT walker aborts on not-present pages
1578 * instead of inserting a not-present translation, this allows
1579 * vectoring directly to the miss handler.
1580 */
1581 if (!pte.p)
1582 return (is_data ? IA64_DATA_TLB_VECTOR : IA64_INST_TLB_VECTOR);
1584 /* found mapping in guest VHPT! */
1585 *itir = rr & RR_PS_MASK;
1586 *pteval = pte.val;
1587 vhpt_translate_count++;
1588 return IA64_NO_FAULT;
1591 IA64FAULT vcpu_tpa(VCPU *vcpu, UINT64 vadr, UINT64 *padr)
1593 UINT64 pteval, itir, mask, iha;
1594 IA64FAULT fault;
1596 fault = vcpu_translate(vcpu, vadr, TRUE, &pteval, &itir, &iha);
1597 if (fault == IA64_NO_FAULT || fault == IA64_USE_TLB)
1599 mask = itir_mask(itir);
1600 *padr = (pteval & _PAGE_PPN_MASK & mask) | (vadr & ~mask);
1601 return (IA64_NO_FAULT);
1603 return vcpu_force_data_miss(vcpu,vadr);
1606 IA64FAULT vcpu_tak(VCPU *vcpu, UINT64 vadr, UINT64 *key)
1608 printf("vcpu_tak: tak instruction unsupported\n");
1609 return (IA64_ILLOP_FAULT);
1610 // HACK ALERT: tak does a thash for now
1611 //return vcpu_thash(vcpu,vadr,key);
1614 /**************************************************************************
1615 VCPU debug breakpoint register access routines
1616 **************************************************************************/
1618 IA64FAULT vcpu_set_dbr(VCPU *vcpu, UINT64 reg, UINT64 val)
1620 // TODO: unimplemented DBRs return a reserved register fault
1621 // TODO: Should set Logical CPU state, not just physical
1622 ia64_set_dbr(reg,val);
1623 return (IA64_NO_FAULT);
1626 IA64FAULT vcpu_set_ibr(VCPU *vcpu, UINT64 reg, UINT64 val)
1628 // TODO: unimplemented IBRs return a reserved register fault
1629 // TODO: Should set Logical CPU state, not just physical
1630 ia64_set_ibr(reg,val);
1631 return (IA64_NO_FAULT);
1634 IA64FAULT vcpu_get_dbr(VCPU *vcpu, UINT64 reg, UINT64 *pval)
1636 // TODO: unimplemented DBRs return a reserved register fault
1637 UINT64 val = ia64_get_dbr(reg);
1638 *pval = val;
1639 return (IA64_NO_FAULT);
1642 IA64FAULT vcpu_get_ibr(VCPU *vcpu, UINT64 reg, UINT64 *pval)
1644 // TODO: unimplemented IBRs return a reserved register fault
1645 UINT64 val = ia64_get_ibr(reg);
1646 *pval = val;
1647 return (IA64_NO_FAULT);
1650 /**************************************************************************
1651 VCPU performance monitor register access routines
1652 **************************************************************************/
1654 IA64FAULT vcpu_set_pmc(VCPU *vcpu, UINT64 reg, UINT64 val)
1656 // TODO: Should set Logical CPU state, not just physical
1657 // NOTE: Writes to unimplemented PMC registers are discarded
1658 #ifdef DEBUG_PFMON
1659 printf("vcpu_set_pmc(%x,%lx)\n",reg,val);
1660 #endif
1661 ia64_set_pmc(reg,val);
1662 return (IA64_NO_FAULT);
1665 IA64FAULT vcpu_set_pmd(VCPU *vcpu, UINT64 reg, UINT64 val)
1667 // TODO: Should set Logical CPU state, not just physical
1668 // NOTE: Writes to unimplemented PMD registers are discarded
1669 #ifdef DEBUG_PFMON
1670 printf("vcpu_set_pmd(%x,%lx)\n",reg,val);
1671 #endif
1672 ia64_set_pmd(reg,val);
1673 return (IA64_NO_FAULT);
1676 IA64FAULT vcpu_get_pmc(VCPU *vcpu, UINT64 reg, UINT64 *pval)
1678 // NOTE: Reads from unimplemented PMC registers return zero
1679 UINT64 val = (UINT64)ia64_get_pmc(reg);
1680 #ifdef DEBUG_PFMON
1681 printf("%lx=vcpu_get_pmc(%x)\n",val,reg);
1682 #endif
1683 *pval = val;
1684 return (IA64_NO_FAULT);
1687 IA64FAULT vcpu_get_pmd(VCPU *vcpu, UINT64 reg, UINT64 *pval)
1689 // NOTE: Reads from unimplemented PMD registers return zero
1690 UINT64 val = (UINT64)ia64_get_pmd(reg);
1691 #ifdef DEBUG_PFMON
1692 printf("%lx=vcpu_get_pmd(%x)\n",val,reg);
1693 #endif
1694 *pval = val;
1695 return (IA64_NO_FAULT);
1698 /**************************************************************************
1699 VCPU banked general register access routines
1700 **************************************************************************/
1701 #define vcpu_bsw0_unat(i,b0unat,b1unat,runat,IA64_PT_REGS_R16_SLOT) \
1702 do{ \
1703 __asm__ __volatile__ ( \
1704 ";;extr.u %0 = %3,%6,16;;\n" \
1705 "dep %1 = %0, %1, 0, 16;;\n" \
1706 "st8 [%4] = %1\n" \
1707 "extr.u %0 = %2, 16, 16;;\n" \
1708 "dep %3 = %0, %3, %6, 16;;\n" \
1709 "st8 [%5] = %3\n" \
1710 ::"r"(i),"r"(*b1unat),"r"(*b0unat),"r"(*runat),"r"(b1unat), \
1711 "r"(runat),"i"(IA64_PT_REGS_R16_SLOT):"memory"); \
1712 }while(0)
1714 IA64FAULT vcpu_bsw0(VCPU *vcpu)
1716 // TODO: Only allowed for current vcpu
1717 REGS *regs = vcpu_regs(vcpu);
1718 unsigned long *r = &regs->r16;
1719 unsigned long *b0 = &PSCB(vcpu,bank0_regs[0]);
1720 unsigned long *b1 = &PSCB(vcpu,bank1_regs[0]);
1721 unsigned long *runat = &regs->eml_unat;
1722 unsigned long *b0unat = &PSCB(vcpu,vbnat);
1723 unsigned long *b1unat = &PSCB(vcpu,vnat);
1725 unsigned long i;
1727 if(VMX_DOMAIN(vcpu)){
1728 if(VCPU(vcpu,vpsr)&IA64_PSR_BN){
1729 for (i = 0; i < 16; i++) { *b1++ = *r; *r++ = *b0++; }
1730 vcpu_bsw0_unat(i,b0unat,b1unat,runat,IA64_PT_REGS_R16_SLOT);
1731 VCPU(vcpu,vpsr) &= ~IA64_PSR_BN;
1733 }else{
1734 if (PSCB(vcpu,banknum)) {
1735 for (i = 0; i < 16; i++) { *b1++ = *r; *r++ = *b0++; }
1736 vcpu_bsw0_unat(i,b0unat,b1unat,runat,IA64_PT_REGS_R16_SLOT);
1737 PSCB(vcpu,banknum) = 0;
1740 return (IA64_NO_FAULT);
1743 #define vcpu_bsw1_unat(i,b0unat,b1unat,runat,IA64_PT_REGS_R16_SLOT) \
1744 do{ \
1745 __asm__ __volatile__ ( \
1746 ";;extr.u %0 = %3,%6,16;;\n" \
1747 "dep %1 = %0, %1, 16, 16;;\n" \
1748 "st8 [%4] = %1\n" \
1749 "extr.u %0 = %2, 0, 16;;\n" \
1750 "dep %3 = %0, %3, %6, 16;;\n" \
1751 "st8 [%5] = %3\n" \
1752 ::"r"(i),"r"(*b0unat),"r"(*b1unat),"r"(*runat),"r"(b0unat), \
1753 "r"(runat),"i"(IA64_PT_REGS_R16_SLOT):"memory"); \
1754 }while(0)
1756 IA64FAULT vcpu_bsw1(VCPU *vcpu)
1758 // TODO: Only allowed for current vcpu
1759 REGS *regs = vcpu_regs(vcpu);
1760 unsigned long *r = &regs->r16;
1761 unsigned long *b0 = &PSCB(vcpu,bank0_regs[0]);
1762 unsigned long *b1 = &PSCB(vcpu,bank1_regs[0]);
1763 unsigned long *runat = &regs->eml_unat;
1764 unsigned long *b0unat = &PSCB(vcpu,vbnat);
1765 unsigned long *b1unat = &PSCB(vcpu,vnat);
1767 unsigned long i;
1769 if(VMX_DOMAIN(vcpu)){
1770 if(!(VCPU(vcpu,vpsr)&IA64_PSR_BN)){
1771 for (i = 0; i < 16; i++) { *b0++ = *r; *r++ = *b1++; }
1772 vcpu_bsw1_unat(i,b0unat,b1unat,runat,IA64_PT_REGS_R16_SLOT);
1773 VCPU(vcpu,vpsr) |= IA64_PSR_BN;
1775 }else{
1776 if (!PSCB(vcpu,banknum)) {
1777 for (i = 0; i < 16; i++) { *b0++ = *r; *r++ = *b1++; }
1778 vcpu_bsw1_unat(i,b0unat,b1unat,runat,IA64_PT_REGS_R16_SLOT);
1779 PSCB(vcpu,banknum) = 1;
1782 return (IA64_NO_FAULT);
1785 /**************************************************************************
1786 VCPU cpuid access routines
1787 **************************************************************************/
1790 IA64FAULT vcpu_get_cpuid(VCPU *vcpu, UINT64 reg, UINT64 *pval)
1792 // FIXME: This could get called as a result of a rsvd-reg fault
1793 // if reg > 3
1794 switch(reg) {
1795 case 0:
1796 memcpy(pval,"Xen/ia64",8);
1797 break;
1798 case 1:
1799 *pval = 0;
1800 break;
1801 case 2:
1802 *pval = 0;
1803 break;
1804 case 3:
1805 *pval = ia64_get_cpuid(3);
1806 break;
1807 case 4:
1808 *pval = ia64_get_cpuid(4);
1809 break;
1810 default:
1811 if (reg > (ia64_get_cpuid(3) & 0xff))
1812 return IA64_RSVDREG_FAULT;
1813 *pval = ia64_get_cpuid(reg);
1814 break;
1816 return (IA64_NO_FAULT);
1819 /**************************************************************************
1820 VCPU region register access routines
1821 **************************************************************************/
1823 unsigned long vcpu_get_rr_ve(VCPU *vcpu,UINT64 vadr)
1825 ia64_rr rr;
1827 rr.rrval = PSCB(vcpu,rrs)[vadr>>61];
1828 return(rr.ve);
1831 IA64FAULT vcpu_set_rr(VCPU *vcpu, UINT64 reg, UINT64 val)
1833 PSCB(vcpu,rrs)[reg>>61] = val;
1834 // warning: set_one_rr() does it "live"
1835 set_one_rr(reg,val);
1836 return (IA64_NO_FAULT);
1839 IA64FAULT vcpu_get_rr(VCPU *vcpu, UINT64 reg, UINT64 *pval)
1841 if(VMX_DOMAIN(vcpu)){
1842 *pval = VMX(vcpu,vrr[reg>>61]);
1843 }else{
1844 *pval = PSCB(vcpu,rrs)[reg>>61];
1846 return (IA64_NO_FAULT);
1849 /**************************************************************************
1850 VCPU protection key register access routines
1851 **************************************************************************/
1853 IA64FAULT vcpu_get_pkr(VCPU *vcpu, UINT64 reg, UINT64 *pval)
1855 #ifndef PKR_USE_FIXED
1856 printk("vcpu_get_pkr: called, not implemented yet\n");
1857 return IA64_ILLOP_FAULT;
1858 #else
1859 UINT64 val = (UINT64)ia64_get_pkr(reg);
1860 *pval = val;
1861 return (IA64_NO_FAULT);
1862 #endif
1865 IA64FAULT vcpu_set_pkr(VCPU *vcpu, UINT64 reg, UINT64 val)
1867 #ifndef PKR_USE_FIXED
1868 printk("vcpu_set_pkr: called, not implemented yet\n");
1869 return IA64_ILLOP_FAULT;
1870 #else
1871 // if (reg >= NPKRS) return (IA64_ILLOP_FAULT);
1872 vcpu->pkrs[reg] = val;
1873 ia64_set_pkr(reg,val);
1874 return (IA64_NO_FAULT);
1875 #endif
1878 /**************************************************************************
1879 VCPU translation register access routines
1880 **************************************************************************/
1882 static void
1883 vcpu_set_tr_entry_rid(TR_ENTRY *trp, UINT64 pte,
1884 UINT64 itir, UINT64 ifa, UINT64 rid)
1886 UINT64 ps;
1887 union pte_flags new_pte;
1889 trp->itir = itir;
1890 trp->rid = rid;
1891 ps = trp->ps;
1892 new_pte.val = pte;
1893 if (new_pte.pl < 2) new_pte.pl = 2;
1894 trp->vadr = ifa & ~0xfff;
1895 if (ps > 12) { // "ignore" relevant low-order bits
1896 new_pte.ppn &= ~((1UL<<(ps-12))-1);
1897 trp->vadr &= ~((1UL<<ps)-1);
1900 /* Atomic write. */
1901 trp->pte.val = new_pte.val;
1904 static inline void
1905 vcpu_set_tr_entry(TR_ENTRY *trp, UINT64 pte, UINT64 itir, UINT64 ifa)
1907 vcpu_set_tr_entry_rid(trp, pte, itir, ifa,
1908 VCPU(current, rrs[ifa>>61]) & RR_RID_MASK);
1911 IA64FAULT vcpu_itr_d(VCPU *vcpu, UINT64 slot, UINT64 pte,
1912 UINT64 itir, UINT64 ifa)
1914 TR_ENTRY *trp;
1916 if (slot >= NDTRS) return IA64_RSVDREG_FAULT;
1918 vcpu_purge_tr_entry(&PSCBX(vcpu, dtlb));
1920 trp = &PSCBX(vcpu,dtrs[slot]);
1921 //printf("***** itr.d: setting slot %d: ifa=%p\n",slot,ifa);
1922 vcpu_set_tr_entry(trp,pte,itir,ifa);
1923 vcpu_quick_region_set(PSCBX(vcpu,dtr_regions),ifa);
1925 /*
1926 * FIXME According to spec, vhpt should be purged, but this
1927 * incurs considerable performance loss, since it is safe for
1928 * linux not to purge vhpt, vhpt purge is disabled until a
1929 * feasible way is found.
1931 * vcpu_flush_tlb_vhpt_range(ifa & itir_mask(itir), itir_ps(itir));
1932 */
1934 return IA64_NO_FAULT;
1937 IA64FAULT vcpu_itr_i(VCPU *vcpu, UINT64 slot, UINT64 pte,
1938 UINT64 itir, UINT64 ifa)
1940 TR_ENTRY *trp;
1942 if (slot >= NITRS) return IA64_RSVDREG_FAULT;
1944 vcpu_purge_tr_entry(&PSCBX(vcpu, itlb));
1946 trp = &PSCBX(vcpu,itrs[slot]);
1947 //printf("***** itr.i: setting slot %d: ifa=%p\n",slot,ifa);
1948 vcpu_set_tr_entry(trp,pte,itir,ifa);
1949 vcpu_quick_region_set(PSCBX(vcpu,itr_regions),ifa);
1951 /*
1952 * FIXME According to spec, vhpt should be purged, but this
1953 * incurs considerable performance loss, since it is safe for
1954 * linux not to purge vhpt, vhpt purge is disabled until a
1955 * feasible way is found.
1957 * vcpu_flush_tlb_vhpt_range(ifa & itir_mask(itir), itir_ps(itir));
1958 */
1960 return IA64_NO_FAULT;
1963 IA64FAULT vcpu_set_itr(VCPU *vcpu, u64 slot, u64 pte,
1964 u64 itir, u64 ifa, u64 rid)
1966 TR_ENTRY *trp;
1968 if (slot >= NITRS)
1969 return IA64_RSVDREG_FAULT;
1970 trp = &PSCBX(vcpu, itrs[slot]);
1971 vcpu_set_tr_entry_rid(trp, pte, itir, ifa, rid);
1973 /* Recompute the itr_region. */
1974 vcpu->arch.itr_regions = 0;
1975 for (trp = vcpu->arch.itrs; trp < &vcpu->arch.itrs[NITRS]; trp++)
1976 if (trp->pte.p)
1977 vcpu_quick_region_set(vcpu->arch.itr_regions,
1978 trp->vadr);
1979 return IA64_NO_FAULT;
1982 IA64FAULT vcpu_set_dtr(VCPU *vcpu, u64 slot, u64 pte,
1983 u64 itir, u64 ifa, u64 rid)
1985 TR_ENTRY *trp;
1987 if (slot >= NDTRS)
1988 return IA64_RSVDREG_FAULT;
1989 trp = &PSCBX(vcpu, dtrs[slot]);
1990 vcpu_set_tr_entry_rid(trp, pte, itir, ifa, rid);
1992 /* Recompute the dtr_region. */
1993 vcpu->arch.dtr_regions = 0;
1994 for (trp = vcpu->arch.dtrs; trp < &vcpu->arch.dtrs[NDTRS]; trp++)
1995 if (trp->pte.p)
1996 vcpu_quick_region_set(vcpu->arch.dtr_regions,
1997 trp->vadr);
1998 return IA64_NO_FAULT;
2001 /**************************************************************************
2002 VCPU translation cache access routines
2003 **************************************************************************/
2005 void vcpu_itc_no_srlz(VCPU *vcpu, UINT64 IorD, UINT64 vaddr, UINT64 pte, UINT64 mp_pte, UINT64 logps)
2007 unsigned long psr;
2008 unsigned long ps = (vcpu->domain==dom0) ? logps : PAGE_SHIFT;
2010 check_xen_space_overlap ("itc", vaddr, 1UL << logps);
2012 // FIXME, must be inlined or potential for nested fault here!
2013 if ((vcpu->domain==dom0) && (logps < PAGE_SHIFT))
2014 panic_domain (NULL, "vcpu_itc_no_srlz: domain trying to use "
2015 "smaller page size!\n");
2017 #ifdef CONFIG_XEN_IA64_DOM0_VP
2018 BUG_ON(logps > PAGE_SHIFT);
2019 #endif
2020 psr = ia64_clear_ic();
2021 ia64_itc(IorD,vaddr,pte,ps); // FIXME: look for bigger mappings
2022 ia64_set_psr(psr);
2023 // ia64_srlz_i(); // no srls req'd, will rfi later
2024 #ifdef VHPT_GLOBAL
2025 if (vcpu->domain==dom0 && ((vaddr >> 61) == 7)) {
2026 // FIXME: this is dangerous... vhpt_flush_address ensures these
2027 // addresses never get flushed. More work needed if this
2028 // ever happens.
2029 //printf("vhpt_insert(%p,%p,%p)\n",vaddr,pte,1L<<logps);
2030 if (logps > PAGE_SHIFT) vhpt_multiple_insert(vaddr,pte,logps);
2031 else vhpt_insert(vaddr,pte,logps<<2);
2033 // even if domain pagesize is larger than PAGE_SIZE, just put
2034 // PAGE_SIZE mapping in the vhpt for now, else purging is complicated
2035 else vhpt_insert(vaddr,pte,PAGE_SHIFT<<2);
2036 #endif
2037 if ((mp_pte == -1UL) || (IorD & 0x4)) // don't place in 1-entry TLB
2038 return;
2039 if (IorD & 0x1) {
2040 vcpu_set_tr_entry(&PSCBX(vcpu,itlb),mp_pte,ps<<2,vaddr);
2042 if (IorD & 0x2) {
2043 vcpu_set_tr_entry(&PSCBX(vcpu,dtlb),mp_pte,ps<<2,vaddr);
2047 IA64FAULT vcpu_itc_d(VCPU *vcpu, UINT64 pte, UINT64 itir, UINT64 ifa)
2049 unsigned long pteval, logps = itir_ps(itir);
2050 BOOLEAN swap_rr0 = (!(ifa>>61) && PSCB(vcpu,metaphysical_mode));
2051 struct p2m_entry entry;
2053 if (logps < PAGE_SHIFT)
2054 panic_domain (NULL, "vcpu_itc_d: domain trying to use "
2055 "smaller page size!\n");
2057 again:
2058 //itir = (itir & ~0xfc) | (PAGE_SHIFT<<2); // ignore domain's pagesize
2059 pteval = translate_domain_pte(pte, ifa, itir, &logps, &entry);
2060 if (!pteval) return IA64_ILLOP_FAULT;
2061 if (swap_rr0) set_one_rr(0x0,PSCB(vcpu,rrs[0]));
2062 vcpu_itc_no_srlz(vcpu,2,ifa,pteval,pte,logps);
2063 if (swap_rr0) set_metaphysical_rr0();
2064 if (p2m_entry_retry(&entry)) {
2065 vcpu_flush_tlb_vhpt_range(ifa, logps);
2066 goto again;
2068 return IA64_NO_FAULT;
2071 IA64FAULT vcpu_itc_i(VCPU *vcpu, UINT64 pte, UINT64 itir, UINT64 ifa)
2073 unsigned long pteval, logps = itir_ps(itir);
2074 BOOLEAN swap_rr0 = (!(ifa>>61) && PSCB(vcpu,metaphysical_mode));
2075 struct p2m_entry entry;
2077 if (logps < PAGE_SHIFT)
2078 panic_domain (NULL, "vcpu_itc_i: domain trying to use "
2079 "smaller page size!\n");
2080 again:
2081 //itir = (itir & ~0xfc) | (PAGE_SHIFT<<2); // ignore domain's pagesize
2082 pteval = translate_domain_pte(pte, ifa, itir, &logps, &entry);
2083 if (!pteval) return IA64_ILLOP_FAULT;
2084 if (swap_rr0) set_one_rr(0x0,PSCB(vcpu,rrs[0]));
2085 vcpu_itc_no_srlz(vcpu, 1,ifa,pteval,pte,logps);
2086 if (swap_rr0) set_metaphysical_rr0();
2087 if (p2m_entry_retry(&entry)) {
2088 vcpu_flush_tlb_vhpt_range(ifa, logps);
2089 goto again;
2091 return IA64_NO_FAULT;
2094 IA64FAULT vcpu_ptc_l(VCPU *vcpu, UINT64 vadr, UINT64 log_range)
2096 BUG_ON(vcpu != current);
2098 check_xen_space_overlap ("ptc_l", vadr, 1UL << log_range);
2100 /* Purge TC */
2101 vcpu_purge_tr_entry(&PSCBX(vcpu,dtlb));
2102 vcpu_purge_tr_entry(&PSCBX(vcpu,itlb));
2104 /* Purge all tlb and vhpt */
2105 vcpu_flush_tlb_vhpt_range (vadr, log_range);
2107 return IA64_NO_FAULT;
2110 // At privlvl=0, fc performs no access rights or protection key checks, while
2111 // at privlvl!=0, fc performs access rights checks as if it were a 1-byte
2112 // read but no protection key check. Thus in order to avoid an unexpected
2113 // access rights fault, we have to translate the virtual address to a
2114 // physical address (possibly via a metaphysical address) and do the fc
2115 // on the physical address, which is guaranteed to flush the same cache line
2116 IA64FAULT vcpu_fc(VCPU *vcpu, UINT64 vadr)
2118 // TODO: Only allowed for current vcpu
2119 UINT64 mpaddr, paddr;
2120 IA64FAULT fault;
2122 again:
2123 fault = vcpu_tpa(vcpu, vadr, &mpaddr);
2124 if (fault == IA64_NO_FAULT) {
2125 struct p2m_entry entry;
2126 paddr = translate_domain_mpaddr(mpaddr, &entry);
2127 ia64_fc(__va(paddr));
2128 if (p2m_entry_retry(&entry))
2129 goto again;
2131 return fault;
2134 IA64FAULT vcpu_ptc_e(VCPU *vcpu, UINT64 vadr)
2136 // Note that this only needs to be called once, i.e. the
2137 // architected loop to purge the entire TLB, should use
2138 // base = stride1 = stride2 = 0, count0 = count 1 = 1
2140 vcpu_flush_vtlb_all(current);
2142 return IA64_NO_FAULT;
2145 IA64FAULT vcpu_ptc_g(VCPU *vcpu, UINT64 vadr, UINT64 addr_range)
2147 printk("vcpu_ptc_g: called, not implemented yet\n");
2148 return IA64_ILLOP_FAULT;
2151 IA64FAULT vcpu_ptc_ga(VCPU *vcpu,UINT64 vadr,UINT64 addr_range)
2153 // FIXME: validate not flushing Xen addresses
2154 // if (Xen address) return(IA64_ILLOP_FAULT);
2155 // FIXME: ??breaks if domain PAGE_SIZE < Xen PAGE_SIZE
2156 //printf("######## vcpu_ptc_ga(%p,%p) ##############\n",vadr,addr_range);
2158 check_xen_space_overlap ("ptc_ga", vadr, addr_range);
2160 domain_flush_vtlb_range (vcpu->domain, vadr, addr_range);
2162 return IA64_NO_FAULT;
2165 IA64FAULT vcpu_ptr_d(VCPU *vcpu,UINT64 vadr,UINT64 log_range)
2167 unsigned long region = vadr >> 61;
2168 u64 addr_range = 1UL << log_range;
2169 unsigned long rid, rr;
2170 int i;
2171 TR_ENTRY *trp;
2173 BUG_ON(vcpu != current);
2174 check_xen_space_overlap ("ptr_d", vadr, 1UL << log_range);
2176 rr = PSCB(vcpu,rrs)[region];
2177 rid = rr & RR_RID_MASK;
2179 /* Purge TC */
2180 vcpu_purge_tr_entry(&PSCBX(vcpu,dtlb));
2182 /* Purge tr and recompute dtr_regions. */
2183 vcpu->arch.dtr_regions = 0;
2184 for (trp = vcpu->arch.dtrs, i = NDTRS; i; i--, trp++)
2185 if (vcpu_match_tr_entry_range (trp,rid, vadr, vadr+addr_range))
2186 vcpu_purge_tr_entry(trp);
2187 else if (trp->pte.p)
2188 vcpu_quick_region_set(vcpu->arch.dtr_regions,
2189 trp->vadr);
2191 vcpu_flush_tlb_vhpt_range (vadr, log_range);
2193 return IA64_NO_FAULT;
2196 IA64FAULT vcpu_ptr_i(VCPU *vcpu,UINT64 vadr,UINT64 log_range)
2198 unsigned long region = vadr >> 61;
2199 u64 addr_range = 1UL << log_range;
2200 unsigned long rid, rr;
2201 int i;
2202 TR_ENTRY *trp;
2204 BUG_ON(vcpu != current);
2205 check_xen_space_overlap ("ptr_i", vadr, 1UL << log_range);
2207 rr = PSCB(vcpu,rrs)[region];
2208 rid = rr & RR_RID_MASK;
2210 /* Purge TC */
2211 vcpu_purge_tr_entry(&PSCBX(vcpu,itlb));
2213 /* Purge tr and recompute itr_regions. */
2214 vcpu->arch.itr_regions = 0;
2215 for (trp = vcpu->arch.itrs, i = NITRS; i; i--, trp++)
2216 if (vcpu_match_tr_entry_range (trp,rid, vadr, vadr+addr_range))
2217 vcpu_purge_tr_entry(trp);
2218 else if (trp->pte.p)
2219 vcpu_quick_region_set(vcpu->arch.itr_regions,
2220 trp->vadr);
2222 vcpu_flush_tlb_vhpt_range (vadr, log_range);
2224 return IA64_NO_FAULT;