ia64/xen-unstable

view tools/ioemu/target-i386-dm/piix_pci-dm.c @ 15841:c5f735271e22

[IA64] Foreign p2m: Fix vti domain builder.

It should set arch_domain::convmem_end.

Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
author Alex Williamson <alex.williamson@hp.com>
date Thu Sep 06 13:48:43 2007 -0600 (2007-09-06)
parents 00618037d37d
children
line source
1 /*
2 * QEMU i440FX/PIIX3 PCI Bridge Emulation
3 *
4 * Copyright (c) 2006 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
25 #include "vl.h"
26 typedef uint32_t pci_addr_t;
27 #include "hw/pci_host.h"
29 typedef PCIHostState I440FXState;
31 static void i440fx_addr_writel(void* opaque, uint32_t addr, uint32_t val)
32 {
33 I440FXState *s = opaque;
34 s->config_reg = val;
35 }
37 static uint32_t i440fx_addr_readl(void* opaque, uint32_t addr)
38 {
39 I440FXState *s = opaque;
40 return s->config_reg;
41 }
43 /* return the global irq number corresponding to a given device irq
44 pin. We could also use the bus number to have a more precise
45 mapping. */
46 static int pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num)
47 {
48 #ifndef CONFIG_DM
49 int slot_addend;
50 slot_addend = (pci_dev->devfn >> 3) - 1;
51 return (irq_num + slot_addend) & 3;
52 #else /* !CONFIG_DM */
53 return irq_num + ((pci_dev->devfn >> 3) << 2);
54 #endif /* !CONFIG_DM */
55 }
57 static void i440fx_set_irq(void *pic, int irq_num, int level)
58 {
59 xc_hvm_set_pci_intx_level(xc_handle, domid, 0, 0, irq_num >> 2,
60 irq_num & 3, level);
61 }
63 static void i440fx_save(QEMUFile* f, void *opaque)
64 {
65 PCIDevice *d = opaque;
66 pci_device_save(d, f);
67 #ifndef CONFIG_DM
68 qemu_put_8s(f, &smm_enabled);
69 #endif /* !CONFIG_DM */
70 }
72 static int i440fx_load(QEMUFile* f, void *opaque, int version_id)
73 {
74 PCIDevice *d = opaque;
75 int ret;
77 if (version_id != 1)
78 return -EINVAL;
79 ret = pci_device_load(d, f);
80 if (ret < 0)
81 return ret;
82 #ifndef CONFIG_DM
83 i440fx_update_memory_mappings(d);
84 qemu_get_8s(f, &smm_enabled);
85 #endif /* !CONFIG_DM */
86 return 0;
87 }
89 PCIBus *i440fx_init(PCIDevice **pi440fx_state)
90 {
91 PCIBus *b;
92 PCIDevice *d;
93 I440FXState *s;
95 s = qemu_mallocz(sizeof(I440FXState));
96 b = pci_register_bus(i440fx_set_irq, pci_slot_get_pirq, NULL, 0, 128);
97 s->bus = b;
99 register_ioport_write(0xcf8, 4, 4, i440fx_addr_writel, s);
100 register_ioport_read(0xcf8, 4, 4, i440fx_addr_readl, s);
102 register_ioport_write(0xcfc, 4, 1, pci_host_data_writeb, s);
103 register_ioport_write(0xcfc, 4, 2, pci_host_data_writew, s);
104 register_ioport_write(0xcfc, 4, 4, pci_host_data_writel, s);
105 register_ioport_read(0xcfc, 4, 1, pci_host_data_readb, s);
106 register_ioport_read(0xcfc, 4, 2, pci_host_data_readw, s);
107 register_ioport_read(0xcfc, 4, 4, pci_host_data_readl, s);
109 d = pci_register_device(b, "i440FX", sizeof(PCIDevice), 0,
110 NULL, NULL);
112 d->config[0x00] = 0x86; // vendor_id
113 d->config[0x01] = 0x80;
114 d->config[0x02] = 0x37; // device_id
115 d->config[0x03] = 0x12;
116 d->config[0x08] = 0x02; // revision
117 d->config[0x0a] = 0x00; // class_sub = host2pci
118 d->config[0x0b] = 0x06; // class_base = PCI_bridge
119 d->config[0x0e] = 0x00; // header_type
121 register_savevm("I440FX", 0, 1, i440fx_save, i440fx_load, d);
122 *pi440fx_state = d;
123 return b;
124 }
126 /* PIIX3 PCI to ISA bridge */
128 static PCIDevice *piix3_dev;
130 static void piix3_write_config(PCIDevice *d,
131 uint32_t address, uint32_t val, int len)
132 {
133 int i;
135 /* Scan for updates to PCI link routes (0x60-0x63). */
136 for (i = 0; i < len; i++) {
137 uint8_t v = (val >> (8*i)) & 0xff;
138 if (v & 0x80)
139 v = 0;
140 v &= 0xf;
141 if (((address+i) >= 0x60) && ((address+i) <= 0x63))
142 xc_hvm_set_pci_link_route(xc_handle, domid, address + i - 0x60, v);
143 }
145 /* Hand off to default logic. */
146 pci_default_write_config(d, address, val, len);
147 }
149 static void piix3_reset(PCIDevice *d)
150 {
151 uint8_t *pci_conf = d->config;
153 pci_conf[0x04] = 0x07; // master, memory and I/O
154 pci_conf[0x05] = 0x00;
155 pci_conf[0x06] = 0x00;
156 pci_conf[0x07] = 0x02; // PCI_status_devsel_medium
157 pci_conf[0x4c] = 0x4d;
158 pci_conf[0x4e] = 0x03;
159 pci_conf[0x4f] = 0x00;
160 pci_conf[0x60] = 0x80;
161 pci_conf[0x61] = 0x80;
162 pci_conf[0x62] = 0x80;
163 pci_conf[0x63] = 0x80;
164 pci_conf[0x69] = 0x02;
165 pci_conf[0x70] = 0x80;
166 pci_conf[0x76] = 0x0c;
167 pci_conf[0x77] = 0x0c;
168 pci_conf[0x78] = 0x02;
169 pci_conf[0x79] = 0x00;
170 pci_conf[0x80] = 0x00;
171 pci_conf[0x82] = 0x00;
172 pci_conf[0xa0] = 0x08;
173 pci_conf[0xa2] = 0x00;
174 pci_conf[0xa3] = 0x00;
175 pci_conf[0xa4] = 0x00;
176 pci_conf[0xa5] = 0x00;
177 pci_conf[0xa6] = 0x00;
178 pci_conf[0xa7] = 0x00;
179 pci_conf[0xa8] = 0x0f;
180 pci_conf[0xaa] = 0x00;
181 pci_conf[0xab] = 0x00;
182 pci_conf[0xac] = 0x00;
183 pci_conf[0xae] = 0x00;
184 }
186 static void piix_save(QEMUFile* f, void *opaque)
187 {
188 PCIDevice *d = opaque;
189 pci_device_save(d, f);
190 }
192 static int piix_load(QEMUFile* f, void *opaque, int version_id)
193 {
194 PCIDevice *d = opaque;
195 if (version_id != 2)
196 return -EINVAL;
197 return pci_device_load(d, f);
198 }
200 int piix3_init(PCIBus *bus, int devfn)
201 {
202 PCIDevice *d;
203 uint8_t *pci_conf;
205 d = pci_register_device(bus, "PIIX3", sizeof(PCIDevice),
206 devfn, NULL, piix3_write_config);
207 register_savevm("PIIX3", 0, 2, piix_save, piix_load, d);
209 piix3_dev = d;
210 pci_conf = d->config;
212 pci_conf[0x00] = 0x86; // Intel
213 pci_conf[0x01] = 0x80;
214 pci_conf[0x02] = 0x00; // 82371SB PIIX3 PCI-to-ISA bridge (Step A1)
215 pci_conf[0x03] = 0x70;
216 pci_conf[0x0a] = 0x01; // class_sub = PCI_ISA
217 pci_conf[0x0b] = 0x06; // class_base = PCI_bridge
218 pci_conf[0x0e] = 0x80; // header_type = PCI_multifunction, generic
220 piix3_reset(d);
221 return d->devfn;
222 }