ia64/xen-unstable

view xen/include/asm-ia64/xenkregs.h @ 16217:c17bfb091790

[IA64] Make Xen relocatable

1. Put xenheap at 0xf400000004000000, then xenheap doesn't
overlap with identity mapping.
2. Xen itself can be relocated by OS loader if there is no
low memory in platform.
3. Use another DTR for mapping xenheap

Signed-off-by: Anthony Xu <anthony.xu@intel.com>
author Alex Williamson <alex.williamson@hp.com>
date Tue Oct 30 11:33:55 2007 -0600 (2007-10-30)
parents eae7b887e5ac
children ac296153ea64
line source
1 #ifndef _ASM_IA64_XENKREGS_H
2 #define _ASM_IA64_XENKREGS_H
4 /*
5 * Translation registers:
6 */
7 #define IA64_TR_SHARED_INFO 3 /* dtr3: page shared with domain */
8 #define IA64_TR_VHPT 4 /* dtr4: vhpt */
9 #define IA64_TR_MAPPED_REGS 5 /* dtr5: vcpu mapped regs */
10 #define IA64_TR_XEN_HEAP_REGS 6 /* dtr6: xen heap identity mapped regs */
11 #define IA64_DTR_GUEST_KERNEL 7
12 #define IA64_ITR_GUEST_KERNEL 2
13 /* Processor status register bits: */
14 #define IA64_PSR_VM_BIT 46
15 #define IA64_PSR_VM (__IA64_UL(1) << IA64_PSR_VM_BIT)
17 #define IA64_DEFAULT_DCR_BITS (IA64_DCR_PP | IA64_DCR_LC | IA64_DCR_DM | \
18 IA64_DCR_DP | IA64_DCR_DK | IA64_DCR_DX | \
19 IA64_DCR_DR | IA64_DCR_DA | IA64_DCR_DD)
21 // note IA64_PSR_PK removed from following, why is this necessary?
22 #define DELIVER_PSR_SET (IA64_PSR_IC | IA64_PSR_I | \
23 IA64_PSR_DT | IA64_PSR_RT | \
24 IA64_PSR_IT | IA64_PSR_BN)
26 #define DELIVER_PSR_CLR (IA64_PSR_AC | IA64_PSR_DFL| IA64_PSR_DFH| \
27 IA64_PSR_SP | IA64_PSR_DI | IA64_PSR_SI | \
28 IA64_PSR_DB | IA64_PSR_LP | IA64_PSR_TB | \
29 IA64_PSR_CPL| IA64_PSR_MC | IA64_PSR_IS | \
30 IA64_PSR_ID | IA64_PSR_DA | IA64_PSR_DD | \
31 IA64_PSR_SS | IA64_PSR_RI | IA64_PSR_ED | IA64_PSR_IA)
33 // NO PSR_CLR IS DIFFERENT! (CPL)
34 #define IA64_PSR_CPL1 (__IA64_UL(1) << IA64_PSR_CPL1_BIT)
35 #define IA64_PSR_CPL0 (__IA64_UL(1) << IA64_PSR_CPL0_BIT)
37 /* Interruption Function State */
38 #define IA64_IFS_V_BIT 63
39 #define IA64_IFS_V (__IA64_UL(1) << IA64_IFS_V_BIT)
41 /* Interruption Status Register. */
42 #define IA64_ISR_NI_BIT 39 /* Nested interrupt. */
44 /* Page Table Address */
45 #define IA64_PTA_VE_BIT 0
46 #define IA64_PTA_SIZE_BIT 2
47 #define IA64_PTA_SIZE_LEN 6
48 #define IA64_PTA_VF_BIT 8
49 #define IA64_PTA_BASE_BIT 15
51 #define IA64_PTA_VE (__IA64_UL(1) << IA64_PTA_VE_BIT)
52 #define IA64_PTA_SIZE (__IA64_UL((1 << IA64_PTA_SIZE_LEN) - 1) << \
53 IA64_PTA_SIZE_BIT)
54 #define IA64_PTA_VF (__IA64_UL(1) << IA64_PTA_VF_BIT)
55 #define IA64_PTA_BASE (__IA64_UL(0) - ((__IA64_UL(1) << IA64_PTA_BASE_BIT)))
57 /* Some cr.itir declarations. */
58 #define IA64_ITIR_PS 2
59 #define IA64_ITIR_PS_LEN 6
60 #define IA64_ITIR_PS_MASK (((__IA64_UL(1) << IA64_ITIR_PS_LEN) - 1) \
61 << IA64_ITIR_PS)
62 #define IA64_ITIR_KEY 8
63 #define IA64_ITIR_KEY_LEN 24
64 #define IA64_ITIR_KEY_MASK (((__IA64_UL(1) << IA64_ITIR_KEY_LEN) - 1) \
65 << IA64_ITIR_KEY)
66 #define IA64_ITIR_PS_KEY(_ps, _key) (((_ps) << IA64_ITIR_PS) | \
67 (((_key) << IA64_ITIR_KEY)))
69 /* Region Register Bits */
70 #define IA64_RR_PS 2
71 #define IA64_RR_PS_LEN 6
72 #define IA64_RR_RID 8
73 #define IA64_RR_RID_LEN 24
74 #define IA64_RR_RID_MASK (((__IA64_UL(1) << IA64_RR_RID_LEN) - 1) << \
75 IA64_RR_RID
77 /* Define Protection Key Register (PKR) */
78 #define IA64_PKR_V 0
79 #define IA64_PKR_WD 1
80 #define IA64_PKR_RD 2
81 #define IA64_PKR_XD 3
82 #define IA64_PKR_MBZ0 4
83 #define IA64_PKR_KEY 8
84 #define IA64_PKR_KEY_LEN 24
85 #define IA64_PKR_MBZ1 32
87 #define IA64_PKR_VALID (1 << IA64_PKR_V)
88 #define IA64_PKR_KEY_MASK (((__IA64_UL(1) << IA64_PKR_KEY_LEN) - 1) \
89 << IA64_PKR_KEY)
91 #define XEN_IA64_NPKRS 15 /* Number of pkr's in PV */
93 /* A pkr val for the hypervisor: key = 0, valid = 1. */
94 #define XEN_IA64_PKR_VAL ((0 << IA64_PKR_KEY) | IA64_PKR_VALID)
96 #endif /* _ASM_IA64_XENKREGS_H */