ia64/xen-unstable

view xen/include/asm-ia64/linux-xen/asm/spinlock.h @ 18666:c003e5a23a4e

Clean up spinlock operations and compile as first-class functions.

This follows modern Linux, since apparently outlining spinlock
operations does not slow down execution. The cleanups will also allow
more convenient addition of diagnostic code.

Signed-off-by: Keir Fraser <keir.fraser@citrix.com>
author Keir Fraser <keir.fraser@citrix.com>
date Mon Oct 20 16:48:17 2008 +0100 (2008-10-20)
parents 7ac9bfbc24e2
children d2f7243fc571
line source
1 #ifndef _ASM_IA64_SPINLOCK_H
2 #define _ASM_IA64_SPINLOCK_H
4 /*
5 * Copyright (C) 1998-2003 Hewlett-Packard Co
6 * David Mosberger-Tang <davidm@hpl.hp.com>
7 * Copyright (C) 1999 Walt Drummond <drummond@valinux.com>
8 *
9 * This file is used for SMP configurations only.
10 */
12 #include <linux/compiler.h>
13 #include <linux/kernel.h>
15 #include <asm/atomic.h>
16 #include <asm/bitops.h>
17 #include <asm/intrinsics.h>
18 #include <asm/system.h>
20 #define DEBUG_SPINLOCK
22 typedef struct {
23 volatile unsigned int lock;
24 #ifdef CONFIG_PREEMPT
25 unsigned int break_lock;
26 #endif
27 #ifdef DEBUG_SPINLOCK
28 void *locker;
29 #endif
30 } raw_spinlock_t;
32 #ifdef XEN
33 #ifdef DEBUG_SPINLOCK
34 #define _RAW_SPIN_LOCK_UNLOCKED /*(raw_spinlock_t)*/ { 0, NULL }
35 #else
36 #define _RAW_SPIN_LOCK_UNLOCKED /*(raw_spinlock_t)*/ { 0 }
37 #endif
38 #else
39 #define _RAW_SPIN_LOCK_UNLOCKED /*(raw_spinlock_t)*/ { 0 }
40 #endif
42 #ifdef ASM_SUPPORTED
43 /*
44 * Try to get the lock. If we fail to get the lock, make a non-standard call to
45 * ia64_spinlock_contention(). We do not use a normal call because that would force all
46 * callers of spin_lock() to be non-leaf routines. Instead, ia64_spinlock_contention() is
47 * carefully coded to touch only those registers that spin_lock() marks "clobbered".
48 */
50 #define IA64_SPINLOCK_CLOBBERS "ar.ccv", "ar.pfs", "p14", "p15", "r27", "r28", "r29", "r30", "b6", "memory"
52 static inline void
53 _raw_spin_lock_flags (raw_spinlock_t *lock, unsigned long flags)
54 {
55 register volatile unsigned int *ptr asm ("r31") = &lock->lock;
57 #if __GNUC__ < 3 || (__GNUC__ == 3 && __GNUC_MINOR__ < 3)
58 # ifdef CONFIG_ITANIUM
59 /* don't use brl on Itanium... */
60 asm volatile ("{\n\t"
61 " mov ar.ccv = r0\n\t"
62 " mov r28 = ip\n\t"
63 " mov r30 = 1;;\n\t"
64 "}\n\t"
65 "cmpxchg4.acq r30 = [%1], r30, ar.ccv\n\t"
66 "movl r29 = ia64_spinlock_contention_pre3_4;;\n\t"
67 "cmp4.ne p14, p0 = r30, r0\n\t"
68 "mov b6 = r29;;\n\t"
69 "mov r27=%2\n\t"
70 "(p14) br.cond.spnt.many b6"
71 : "=r"(ptr) : "r"(ptr), "r" (flags) : IA64_SPINLOCK_CLOBBERS);
72 # else
73 asm volatile ("{\n\t"
74 " mov ar.ccv = r0\n\t"
75 " mov r28 = ip\n\t"
76 " mov r30 = 1;;\n\t"
77 "}\n\t"
78 "cmpxchg4.acq r30 = [%1], r30, ar.ccv;;\n\t"
79 "cmp4.ne p14, p0 = r30, r0\n\t"
80 "mov r27=%2\n\t"
81 "(p14) brl.cond.spnt.many ia64_spinlock_contention_pre3_4;;"
82 : "=r"(ptr) : "r"(ptr), "r" (flags) : IA64_SPINLOCK_CLOBBERS);
83 # endif /* CONFIG_MCKINLEY */
84 #else
85 # ifdef CONFIG_ITANIUM
86 /* don't use brl on Itanium... */
87 /* mis-declare, so we get the entry-point, not it's function descriptor: */
88 asm volatile ("mov r30 = 1\n\t"
89 "mov r27=%2\n\t"
90 "mov ar.ccv = r0;;\n\t"
91 "cmpxchg4.acq r30 = [%0], r30, ar.ccv\n\t"
92 "movl r29 = ia64_spinlock_contention;;\n\t"
93 "cmp4.ne p14, p0 = r30, r0\n\t"
94 "mov b6 = r29;;\n\t"
95 "(p14) br.call.spnt.many b6 = b6"
96 : "=r"(ptr) : "r"(ptr), "r" (flags) : IA64_SPINLOCK_CLOBBERS);
97 # else
98 asm volatile ("mov r30 = 1\n\t"
99 "mov r27=%2\n\t"
100 "mov ar.ccv = r0;;\n\t"
101 "cmpxchg4.acq r30 = [%0], r30, ar.ccv;;\n\t"
102 "cmp4.ne p14, p0 = r30, r0\n\t"
103 "(p14) brl.call.spnt.many b6=ia64_spinlock_contention;;"
104 : "=r"(ptr) : "r"(ptr), "r" (flags) : IA64_SPINLOCK_CLOBBERS);
105 # endif /* CONFIG_MCKINLEY */
106 #endif
108 #ifdef DEBUG_SPINLOCK
109 asm volatile ("mov %0=ip" : "=r" (lock->locker));
110 #endif
111 }
112 #define _raw_spin_lock(lock) _raw_spin_lock_flags(lock, 0)
113 #else /* !ASM_SUPPORTED */
114 #define _raw_spin_lock_flags(lock, flags) _raw_spin_lock(lock)
115 # define _raw_spin_lock(x) \
116 do { \
117 __u32 *ia64_spinlock_ptr = (__u32 *) (x); \
118 __u64 ia64_spinlock_val; \
119 ia64_spinlock_val = ia64_cmpxchg4_acq(ia64_spinlock_ptr, 1, 0); \
120 if (unlikely(ia64_spinlock_val)) { \
121 do { \
122 while (*ia64_spinlock_ptr) \
123 ia64_barrier(); \
124 ia64_spinlock_val = ia64_cmpxchg4_acq(ia64_spinlock_ptr, 1, 0); \
125 } while (ia64_spinlock_val); \
126 } \
127 } while (0)
128 #endif /* !ASM_SUPPORTED */
130 #define _raw_spin_is_locked(x) ((x)->lock != 0)
131 #define _raw_spin_unlock(x) do { barrier(); (x)->lock = 0; } while (0)
132 #define _raw_spin_trylock(x) (cmpxchg_acq(&(x)->lock, 0, 1) == 0)
133 #define spin_unlock_wait(x) do { barrier(); } while ((x)->lock)
135 typedef struct {
136 volatile unsigned int read_counter : 31;
137 volatile unsigned int write_lock : 1;
138 #ifdef CONFIG_PREEMPT
139 unsigned int break_lock;
140 #endif
141 } raw_rwlock_t;
142 #define _RAW_RW_LOCK_UNLOCKED /*(raw_rwlock_t)*/ { 0, 0 }
144 #define read_can_lock(rw) (*(volatile int *)(rw) >= 0)
145 #define write_can_lock(rw) (*(volatile int *)(rw) == 0)
147 #define _raw_read_lock(rw) \
148 do { \
149 raw_rwlock_t *__read_lock_ptr = (rw); \
150 \
151 while (unlikely(ia64_fetchadd(1, (int *) __read_lock_ptr, acq) < 0)) { \
152 ia64_fetchadd(-1, (int *) __read_lock_ptr, rel); \
153 while (*(volatile int *)__read_lock_ptr < 0) \
154 cpu_relax(); \
155 } \
156 } while (0)
158 #define _raw_read_unlock(rw) \
159 do { \
160 raw_rwlock_t *__read_lock_ptr = (rw); \
161 ia64_fetchadd(-1, (int *) __read_lock_ptr, rel); \
162 } while (0)
164 #ifdef ASM_SUPPORTED
165 #define _raw_write_lock(rw) \
166 do { \
167 __asm__ __volatile__ ( \
168 "mov ar.ccv = r0\n" \
169 "dep r29 = -1, r0, 31, 1;;\n" \
170 "1:\n" \
171 "ld4 r2 = [%0];;\n" \
172 "cmp4.eq p0,p7 = r0,r2\n" \
173 "(p7) br.cond.spnt.few 1b \n" \
174 "cmpxchg4.acq r2 = [%0], r29, ar.ccv;;\n" \
175 "cmp4.eq p0,p7 = r0, r2\n" \
176 "(p7) br.cond.spnt.few 1b;;\n" \
177 :: "r"(rw) : "ar.ccv", "p7", "r2", "r29", "memory"); \
178 } while(0)
180 #define _raw_write_trylock(rw) \
181 ({ \
182 register long result; \
183 \
184 __asm__ __volatile__ ( \
185 "mov ar.ccv = r0\n" \
186 "dep r29 = -1, r0, 31, 1;;\n" \
187 "cmpxchg4.acq %0 = [%1], r29, ar.ccv\n" \
188 : "=r"(result) : "r"(rw) : "ar.ccv", "r29", "memory"); \
189 (result == 0); \
190 })
192 #else /* !ASM_SUPPORTED */
194 #define _raw_write_lock(l) \
195 ({ \
196 __u64 ia64_val, ia64_set_val = ia64_dep_mi(-1, 0, 31, 1); \
197 __u32 *ia64_write_lock_ptr = (__u32 *) (l); \
198 do { \
199 while (*ia64_write_lock_ptr) \
200 ia64_barrier(); \
201 ia64_val = ia64_cmpxchg4_acq(ia64_write_lock_ptr, ia64_set_val, 0); \
202 } while (ia64_val); \
203 })
205 #define _raw_write_trylock(rw) \
206 ({ \
207 __u64 ia64_val; \
208 __u64 ia64_set_val = ia64_dep_mi(-1, 0, 31,1); \
209 ia64_val = ia64_cmpxchg4_acq((__u32 *)(rw), ia64_set_val, 0); \
210 (ia64_val == 0); \
211 })
213 #endif /* !ASM_SUPPORTED */
215 #define _raw_read_trylock(lock) generic_raw_read_trylock(lock)
217 #define _raw_write_unlock(x) \
218 ({ \
219 smp_mb__before_clear_bit(); /* need barrier before releasing lock... */ \
220 clear_bit(31, (x)); \
221 })
223 #endif /* _ASM_IA64_SPINLOCK_H */