ia64/xen-unstable

view xen/arch/x86/x86_emulate.c @ 16990:bf4a24c172d2

x86_emulate: fix side-effect macro call.
Signed-off-by: Samuel Thibault <samuel.thibault@eu.citrix.com>
author Keir Fraser <keir.fraser@citrix.com>
date Tue Feb 05 15:50:59 2008 +0000 (2008-02-05)
parents 92734271810a
children 445edf4089a3
line source
1 /******************************************************************************
2 * x86_emulate.c
3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005-2007 Keir Fraser
7 * Copyright (c) 2005-2007 XenSource Inc.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 */
24 #ifndef __XEN__
25 #include <stddef.h>
26 #include <stdint.h>
27 #include <public/xen.h>
28 #else
29 #include <xen/config.h>
30 #include <xen/types.h>
31 #include <xen/lib.h>
32 #include <asm/regs.h>
33 #undef cmpxchg
34 #endif
35 #include <asm-x86/x86_emulate.h>
37 /* Operand sizes: 8-bit operands or specified/overridden size. */
38 #define ByteOp (1<<0) /* 8-bit operands. */
39 /* Destination operand type. */
40 #define DstBitBase (0<<1) /* Memory operand, bit string. */
41 #define ImplicitOps (1<<1) /* Implicit in opcode. No generic decode. */
42 #define DstReg (2<<1) /* Register operand. */
43 #define DstMem (3<<1) /* Memory operand. */
44 #define DstMask (3<<1)
45 /* Source operand type. */
46 #define SrcNone (0<<3) /* No source operand. */
47 #define SrcImplicit (0<<3) /* Source operand is implicit in the opcode. */
48 #define SrcReg (1<<3) /* Register operand. */
49 #define SrcMem (2<<3) /* Memory operand. */
50 #define SrcMem16 (3<<3) /* Memory operand (16-bit). */
51 #define SrcImm (4<<3) /* Immediate operand. */
52 #define SrcImmByte (5<<3) /* 8-bit sign-extended immediate operand. */
53 #define SrcMask (7<<3)
54 /* Generic ModRM decode. */
55 #define ModRM (1<<6)
56 /* Destination is only written; never read. */
57 #define Mov (1<<7)
59 static uint8_t opcode_table[256] = {
60 /* 0x00 - 0x07 */
61 ByteOp|DstMem|SrcReg|ModRM, DstMem|SrcReg|ModRM,
62 ByteOp|DstReg|SrcMem|ModRM, DstReg|SrcMem|ModRM,
63 ByteOp|DstReg|SrcImm, DstReg|SrcImm, ImplicitOps, ImplicitOps,
64 /* 0x08 - 0x0F */
65 ByteOp|DstMem|SrcReg|ModRM, DstMem|SrcReg|ModRM,
66 ByteOp|DstReg|SrcMem|ModRM, DstReg|SrcMem|ModRM,
67 ByteOp|DstReg|SrcImm, DstReg|SrcImm, ImplicitOps, 0,
68 /* 0x10 - 0x17 */
69 ByteOp|DstMem|SrcReg|ModRM, DstMem|SrcReg|ModRM,
70 ByteOp|DstReg|SrcMem|ModRM, DstReg|SrcMem|ModRM,
71 ByteOp|DstReg|SrcImm, DstReg|SrcImm, ImplicitOps, ImplicitOps,
72 /* 0x18 - 0x1F */
73 ByteOp|DstMem|SrcReg|ModRM, DstMem|SrcReg|ModRM,
74 ByteOp|DstReg|SrcMem|ModRM, DstReg|SrcMem|ModRM,
75 ByteOp|DstReg|SrcImm, DstReg|SrcImm, ImplicitOps, ImplicitOps,
76 /* 0x20 - 0x27 */
77 ByteOp|DstMem|SrcReg|ModRM, DstMem|SrcReg|ModRM,
78 ByteOp|DstReg|SrcMem|ModRM, DstReg|SrcMem|ModRM,
79 ByteOp|DstReg|SrcImm, DstReg|SrcImm, 0, ImplicitOps,
80 /* 0x28 - 0x2F */
81 ByteOp|DstMem|SrcReg|ModRM, DstMem|SrcReg|ModRM,
82 ByteOp|DstReg|SrcMem|ModRM, DstReg|SrcMem|ModRM,
83 ByteOp|DstReg|SrcImm, DstReg|SrcImm, 0, ImplicitOps,
84 /* 0x30 - 0x37 */
85 ByteOp|DstMem|SrcReg|ModRM, DstMem|SrcReg|ModRM,
86 ByteOp|DstReg|SrcMem|ModRM, DstReg|SrcMem|ModRM,
87 ByteOp|DstReg|SrcImm, DstReg|SrcImm, 0, ImplicitOps,
88 /* 0x38 - 0x3F */
89 ByteOp|DstMem|SrcReg|ModRM, DstMem|SrcReg|ModRM,
90 ByteOp|DstReg|SrcMem|ModRM, DstReg|SrcMem|ModRM,
91 ByteOp|DstReg|SrcImm, DstReg|SrcImm, 0, ImplicitOps,
92 /* 0x40 - 0x4F */
93 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
94 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
95 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
96 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
97 /* 0x50 - 0x5F */
98 ImplicitOps|Mov, ImplicitOps|Mov, ImplicitOps|Mov, ImplicitOps|Mov,
99 ImplicitOps|Mov, ImplicitOps|Mov, ImplicitOps|Mov, ImplicitOps|Mov,
100 ImplicitOps|Mov, ImplicitOps|Mov, ImplicitOps|Mov, ImplicitOps|Mov,
101 ImplicitOps|Mov, ImplicitOps|Mov, ImplicitOps|Mov, ImplicitOps|Mov,
102 /* 0x60 - 0x67 */
103 ImplicitOps, ImplicitOps, DstReg|SrcMem|ModRM, DstReg|SrcMem16|ModRM|Mov,
104 0, 0, 0, 0,
105 /* 0x68 - 0x6F */
106 ImplicitOps|Mov, DstReg|SrcImm|ModRM|Mov,
107 ImplicitOps|Mov, DstReg|SrcImmByte|ModRM|Mov,
108 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
109 /* 0x70 - 0x77 */
110 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
111 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
112 /* 0x78 - 0x7F */
113 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
114 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
115 /* 0x80 - 0x87 */
116 ByteOp|DstMem|SrcImm|ModRM, DstMem|SrcImm|ModRM,
117 ByteOp|DstMem|SrcImm|ModRM, DstMem|SrcImmByte|ModRM,
118 ByteOp|DstMem|SrcReg|ModRM, DstMem|SrcReg|ModRM,
119 ByteOp|DstMem|SrcReg|ModRM, DstMem|SrcReg|ModRM,
120 /* 0x88 - 0x8F */
121 ByteOp|DstMem|SrcReg|ModRM|Mov, DstMem|SrcReg|ModRM|Mov,
122 ByteOp|DstReg|SrcMem|ModRM|Mov, DstReg|SrcMem|ModRM|Mov,
123 DstMem|SrcReg|ModRM|Mov, DstReg|SrcNone|ModRM,
124 DstReg|SrcMem|ModRM|Mov, DstMem|SrcNone|ModRM|Mov,
125 /* 0x90 - 0x97 */
126 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
127 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
128 /* 0x98 - 0x9F */
129 ImplicitOps, ImplicitOps, ImplicitOps, 0,
130 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
131 /* 0xA0 - 0xA7 */
132 ByteOp|ImplicitOps|Mov, ImplicitOps|Mov,
133 ByteOp|ImplicitOps|Mov, ImplicitOps|Mov,
134 ByteOp|ImplicitOps|Mov, ImplicitOps|Mov,
135 ByteOp|ImplicitOps, ImplicitOps,
136 /* 0xA8 - 0xAF */
137 ByteOp|DstReg|SrcImm, DstReg|SrcImm,
138 ByteOp|ImplicitOps|Mov, ImplicitOps|Mov,
139 ByteOp|ImplicitOps|Mov, ImplicitOps|Mov,
140 ByteOp|ImplicitOps, ImplicitOps,
141 /* 0xB0 - 0xB7 */
142 ByteOp|DstReg|SrcImm|Mov, ByteOp|DstReg|SrcImm|Mov,
143 ByteOp|DstReg|SrcImm|Mov, ByteOp|DstReg|SrcImm|Mov,
144 ByteOp|DstReg|SrcImm|Mov, ByteOp|DstReg|SrcImm|Mov,
145 ByteOp|DstReg|SrcImm|Mov, ByteOp|DstReg|SrcImm|Mov,
146 /* 0xB8 - 0xBF */
147 DstReg|SrcImm|Mov, DstReg|SrcImm|Mov, DstReg|SrcImm|Mov, DstReg|SrcImm|Mov,
148 DstReg|SrcImm|Mov, DstReg|SrcImm|Mov, DstReg|SrcImm|Mov, DstReg|SrcImm|Mov,
149 /* 0xC0 - 0xC7 */
150 ByteOp|DstMem|SrcImm|ModRM, DstMem|SrcImmByte|ModRM,
151 ImplicitOps, ImplicitOps,
152 DstReg|SrcMem|ModRM|Mov, DstReg|SrcMem|ModRM|Mov,
153 ByteOp|DstMem|SrcImm|ModRM|Mov, DstMem|SrcImm|ModRM|Mov,
154 /* 0xC8 - 0xCF */
155 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
156 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
157 /* 0xD0 - 0xD7 */
158 ByteOp|DstMem|SrcImplicit|ModRM, DstMem|SrcImplicit|ModRM,
159 ByteOp|DstMem|SrcImplicit|ModRM, DstMem|SrcImplicit|ModRM,
160 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
161 /* 0xD8 - 0xDF */
162 0, ImplicitOps|ModRM, 0, ImplicitOps|ModRM, 0, ImplicitOps|ModRM, 0, 0,
163 /* 0xE0 - 0xE7 */
164 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
165 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
166 /* 0xE8 - 0xEF */
167 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
168 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
169 /* 0xF0 - 0xF7 */
170 0, ImplicitOps, 0, 0,
171 ImplicitOps, ImplicitOps,
172 ByteOp|DstMem|SrcNone|ModRM, DstMem|SrcNone|ModRM,
173 /* 0xF8 - 0xFF */
174 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
175 ImplicitOps, ImplicitOps, ByteOp|DstMem|SrcNone|ModRM, DstMem|SrcNone|ModRM
176 };
178 static uint8_t twobyte_table[256] = {
179 /* 0x00 - 0x07 */
180 0, ImplicitOps|ModRM, 0, 0, 0, 0, ImplicitOps, 0,
181 /* 0x08 - 0x0F */
182 ImplicitOps, ImplicitOps, 0, 0, 0, ImplicitOps|ModRM, 0, 0,
183 /* 0x10 - 0x17 */
184 0, 0, 0, 0, 0, 0, 0, 0,
185 /* 0x18 - 0x1F */
186 ImplicitOps|ModRM, ImplicitOps|ModRM, ImplicitOps|ModRM, ImplicitOps|ModRM,
187 ImplicitOps|ModRM, ImplicitOps|ModRM, ImplicitOps|ModRM, ImplicitOps|ModRM,
188 /* 0x20 - 0x27 */
189 ImplicitOps|ModRM, ImplicitOps|ModRM, ImplicitOps|ModRM, ImplicitOps|ModRM,
190 0, 0, 0, 0,
191 /* 0x28 - 0x2F */
192 0, 0, 0, 0, 0, 0, 0, 0,
193 /* 0x30 - 0x37 */
194 ImplicitOps, ImplicitOps, ImplicitOps, 0, 0, 0, 0, 0,
195 /* 0x38 - 0x3F */
196 0, 0, 0, 0, 0, 0, 0, 0,
197 /* 0x40 - 0x47 */
198 DstReg|SrcMem|ModRM|Mov, DstReg|SrcMem|ModRM|Mov,
199 DstReg|SrcMem|ModRM|Mov, DstReg|SrcMem|ModRM|Mov,
200 DstReg|SrcMem|ModRM|Mov, DstReg|SrcMem|ModRM|Mov,
201 DstReg|SrcMem|ModRM|Mov, DstReg|SrcMem|ModRM|Mov,
202 /* 0x48 - 0x4F */
203 DstReg|SrcMem|ModRM|Mov, DstReg|SrcMem|ModRM|Mov,
204 DstReg|SrcMem|ModRM|Mov, DstReg|SrcMem|ModRM|Mov,
205 DstReg|SrcMem|ModRM|Mov, DstReg|SrcMem|ModRM|Mov,
206 DstReg|SrcMem|ModRM|Mov, DstReg|SrcMem|ModRM|Mov,
207 /* 0x50 - 0x5F */
208 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
209 /* 0x60 - 0x6F */
210 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
211 /* 0x70 - 0x7F */
212 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
213 /* 0x80 - 0x87 */
214 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
215 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
216 /* 0x88 - 0x8F */
217 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
218 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
219 /* 0x90 - 0x97 */
220 ByteOp|DstMem|SrcNone|ModRM|Mov, ByteOp|DstMem|SrcNone|ModRM|Mov,
221 ByteOp|DstMem|SrcNone|ModRM|Mov, ByteOp|DstMem|SrcNone|ModRM|Mov,
222 ByteOp|DstMem|SrcNone|ModRM|Mov, ByteOp|DstMem|SrcNone|ModRM|Mov,
223 ByteOp|DstMem|SrcNone|ModRM|Mov, ByteOp|DstMem|SrcNone|ModRM|Mov,
224 /* 0x98 - 0x9F */
225 ByteOp|DstMem|SrcNone|ModRM|Mov, ByteOp|DstMem|SrcNone|ModRM|Mov,
226 ByteOp|DstMem|SrcNone|ModRM|Mov, ByteOp|DstMem|SrcNone|ModRM|Mov,
227 ByteOp|DstMem|SrcNone|ModRM|Mov, ByteOp|DstMem|SrcNone|ModRM|Mov,
228 ByteOp|DstMem|SrcNone|ModRM|Mov, ByteOp|DstMem|SrcNone|ModRM|Mov,
229 /* 0xA0 - 0xA7 */
230 ImplicitOps, ImplicitOps, ImplicitOps, DstBitBase|SrcReg|ModRM,
231 DstMem|SrcReg|ModRM, DstMem|SrcReg|ModRM, 0, 0,
232 /* 0xA8 - 0xAF */
233 ImplicitOps, ImplicitOps, 0, DstBitBase|SrcReg|ModRM,
234 DstMem|SrcReg|ModRM, DstMem|SrcReg|ModRM, 0, DstReg|SrcMem|ModRM,
235 /* 0xB0 - 0xB7 */
236 ByteOp|DstMem|SrcReg|ModRM, DstMem|SrcReg|ModRM,
237 DstReg|SrcMem|ModRM|Mov, DstBitBase|SrcReg|ModRM,
238 DstReg|SrcMem|ModRM|Mov, DstReg|SrcMem|ModRM|Mov,
239 ByteOp|DstReg|SrcMem|ModRM|Mov, DstReg|SrcMem16|ModRM|Mov,
240 /* 0xB8 - 0xBF */
241 0, 0, DstBitBase|SrcImmByte|ModRM, DstBitBase|SrcReg|ModRM,
242 DstReg|SrcMem|ModRM, DstReg|SrcMem|ModRM,
243 ByteOp|DstReg|SrcMem|ModRM|Mov, DstReg|SrcMem16|ModRM|Mov,
244 /* 0xC0 - 0xC7 */
245 ByteOp|DstMem|SrcReg|ModRM, DstMem|SrcReg|ModRM, 0, 0,
246 0, 0, 0, ImplicitOps|ModRM,
247 /* 0xC8 - 0xCF */
248 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
249 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
250 /* 0xD0 - 0xDF */
251 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
252 /* 0xE0 - 0xEF */
253 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
254 /* 0xF0 - 0xFF */
255 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
256 };
258 /* Type, address-of, and value of an instruction's operand. */
259 struct operand {
260 enum { OP_REG, OP_MEM, OP_IMM, OP_NONE } type;
261 unsigned int bytes;
262 unsigned long val, orig_val;
263 union {
264 /* OP_REG: Pointer to register field. */
265 unsigned long *reg;
266 /* OP_MEM: Segment and offset. */
267 struct {
268 enum x86_segment seg;
269 unsigned long off;
270 } mem;
271 };
272 };
274 /* MSRs. */
275 #define MSR_TSC 0x10
277 /* Control register flags. */
278 #define CR0_PE (1<<0)
279 #define CR4_TSD (1<<2)
281 /* EFLAGS bit definitions. */
282 #define EFLG_VIP (1<<20)
283 #define EFLG_VIF (1<<19)
284 #define EFLG_AC (1<<18)
285 #define EFLG_VM (1<<17)
286 #define EFLG_RF (1<<16)
287 #define EFLG_NT (1<<14)
288 #define EFLG_IOPL (3<<12)
289 #define EFLG_OF (1<<11)
290 #define EFLG_DF (1<<10)
291 #define EFLG_IF (1<<9)
292 #define EFLG_TF (1<<8)
293 #define EFLG_SF (1<<7)
294 #define EFLG_ZF (1<<6)
295 #define EFLG_AF (1<<4)
296 #define EFLG_PF (1<<2)
297 #define EFLG_CF (1<<0)
299 /* Exception definitions. */
300 #define EXC_DE 0
301 #define EXC_DB 1
302 #define EXC_BP 3
303 #define EXC_OF 4
304 #define EXC_BR 5
305 #define EXC_UD 6
306 #define EXC_TS 10
307 #define EXC_NP 11
308 #define EXC_SS 12
309 #define EXC_GP 13
310 #define EXC_PF 14
312 /*
313 * Instruction emulation:
314 * Most instructions are emulated directly via a fragment of inline assembly
315 * code. This allows us to save/restore EFLAGS and thus very easily pick up
316 * any modified flags.
317 */
319 #if defined(__x86_64__)
320 #define _LO32 "k" /* force 32-bit operand */
321 #define _STK "%%rsp" /* stack pointer */
322 #define _BYTES_PER_LONG "8"
323 #elif defined(__i386__)
324 #define _LO32 "" /* force 32-bit operand */
325 #define _STK "%%esp" /* stack pointer */
326 #define _BYTES_PER_LONG "4"
327 #endif
329 /*
330 * These EFLAGS bits are restored from saved value during emulation, and
331 * any changes are written back to the saved value after emulation.
332 */
333 #define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
335 /* Before executing instruction: restore necessary bits in EFLAGS. */
336 #define _PRE_EFLAGS(_sav, _msk, _tmp) \
337 /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \
338 "movl %"_sav",%"_LO32 _tmp"; " \
339 "push %"_tmp"; " \
340 "push %"_tmp"; " \
341 "movl %"_msk",%"_LO32 _tmp"; " \
342 "andl %"_LO32 _tmp",("_STK"); " \
343 "pushf; " \
344 "notl %"_LO32 _tmp"; " \
345 "andl %"_LO32 _tmp",("_STK"); " \
346 "andl %"_LO32 _tmp",2*"_BYTES_PER_LONG"("_STK"); " \
347 "pop %"_tmp"; " \
348 "orl %"_LO32 _tmp",("_STK"); " \
349 "popf; " \
350 "pop %"_sav"; "
352 /* After executing instruction: write-back necessary bits in EFLAGS. */
353 #define _POST_EFLAGS(_sav, _msk, _tmp) \
354 /* _sav |= EFLAGS & _msk; */ \
355 "pushf; " \
356 "pop %"_tmp"; " \
357 "andl %"_msk",%"_LO32 _tmp"; " \
358 "orl %"_LO32 _tmp",%"_sav"; "
360 /* Raw emulation: instruction has two explicit operands. */
361 #define __emulate_2op_nobyte(_op,_src,_dst,_eflags,_wx,_wy,_lx,_ly,_qx,_qy)\
362 do{ unsigned long _tmp; \
363 switch ( (_dst).bytes ) \
364 { \
365 case 2: \
366 asm volatile ( \
367 _PRE_EFLAGS("0","4","2") \
368 _op"w %"_wx"3,%1; " \
369 _POST_EFLAGS("0","4","2") \
370 : "=m" (_eflags), "=m" ((_dst).val), "=&r" (_tmp) \
371 : _wy ((_src).val), "i" (EFLAGS_MASK), \
372 "m" (_eflags), "m" ((_dst).val) ); \
373 break; \
374 case 4: \
375 asm volatile ( \
376 _PRE_EFLAGS("0","4","2") \
377 _op"l %"_lx"3,%1; " \
378 _POST_EFLAGS("0","4","2") \
379 : "=m" (_eflags), "=m" ((_dst).val), "=&r" (_tmp) \
380 : _ly ((_src).val), "i" (EFLAGS_MASK), \
381 "m" (_eflags), "m" ((_dst).val) ); \
382 break; \
383 case 8: \
384 __emulate_2op_8byte(_op, _src, _dst, _eflags, _qx, _qy); \
385 break; \
386 } \
387 } while (0)
388 #define __emulate_2op(_op,_src,_dst,_eflags,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy)\
389 do{ unsigned long _tmp; \
390 switch ( (_dst).bytes ) \
391 { \
392 case 1: \
393 asm volatile ( \
394 _PRE_EFLAGS("0","4","2") \
395 _op"b %"_bx"3,%1; " \
396 _POST_EFLAGS("0","4","2") \
397 : "=m" (_eflags), "=m" ((_dst).val), "=&r" (_tmp) \
398 : _by ((_src).val), "i" (EFLAGS_MASK), \
399 "m" (_eflags), "m" ((_dst).val) ); \
400 break; \
401 default: \
402 __emulate_2op_nobyte(_op,_src,_dst,_eflags,_wx,_wy,_lx,_ly,_qx,_qy);\
403 break; \
404 } \
405 } while (0)
406 /* Source operand is byte-sized and may be restricted to just %cl. */
407 #define emulate_2op_SrcB(_op, _src, _dst, _eflags) \
408 __emulate_2op(_op, _src, _dst, _eflags, \
409 "b", "c", "b", "c", "b", "c", "b", "c")
410 /* Source operand is byte, word, long or quad sized. */
411 #define emulate_2op_SrcV(_op, _src, _dst, _eflags) \
412 __emulate_2op(_op, _src, _dst, _eflags, \
413 "b", "q", "w", "r", _LO32, "r", "", "r")
414 /* Source operand is word, long or quad sized. */
415 #define emulate_2op_SrcV_nobyte(_op, _src, _dst, _eflags) \
416 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
417 "w", "r", _LO32, "r", "", "r")
419 /* Instruction has only one explicit operand (no source operand). */
420 #define emulate_1op(_op,_dst,_eflags) \
421 do{ unsigned long _tmp; \
422 switch ( (_dst).bytes ) \
423 { \
424 case 1: \
425 asm volatile ( \
426 _PRE_EFLAGS("0","3","2") \
427 _op"b %1; " \
428 _POST_EFLAGS("0","3","2") \
429 : "=m" (_eflags), "=m" ((_dst).val), "=&r" (_tmp) \
430 : "i" (EFLAGS_MASK), "m" (_eflags), "m" ((_dst).val) ); \
431 break; \
432 case 2: \
433 asm volatile ( \
434 _PRE_EFLAGS("0","3","2") \
435 _op"w %1; " \
436 _POST_EFLAGS("0","3","2") \
437 : "=m" (_eflags), "=m" ((_dst).val), "=&r" (_tmp) \
438 : "i" (EFLAGS_MASK), "m" (_eflags), "m" ((_dst).val) ); \
439 break; \
440 case 4: \
441 asm volatile ( \
442 _PRE_EFLAGS("0","3","2") \
443 _op"l %1; " \
444 _POST_EFLAGS("0","3","2") \
445 : "=m" (_eflags), "=m" ((_dst).val), "=&r" (_tmp) \
446 : "i" (EFLAGS_MASK), "m" (_eflags), "m" ((_dst).val) ); \
447 break; \
448 case 8: \
449 __emulate_1op_8byte(_op, _dst, _eflags); \
450 break; \
451 } \
452 } while (0)
454 /* Emulate an instruction with quadword operands (x86/64 only). */
455 #if defined(__x86_64__)
456 #define __emulate_2op_8byte(_op, _src, _dst, _eflags, _qx, _qy) \
457 do{ asm volatile ( \
458 _PRE_EFLAGS("0","4","2") \
459 _op"q %"_qx"3,%1; " \
460 _POST_EFLAGS("0","4","2") \
461 : "=m" (_eflags), "=m" ((_dst).val), "=&r" (_tmp) \
462 : _qy ((_src).val), "i" (EFLAGS_MASK), \
463 "m" (_eflags), "m" ((_dst).val) ); \
464 } while (0)
465 #define __emulate_1op_8byte(_op, _dst, _eflags) \
466 do{ asm volatile ( \
467 _PRE_EFLAGS("0","3","2") \
468 _op"q %1; " \
469 _POST_EFLAGS("0","3","2") \
470 : "=m" (_eflags), "=m" ((_dst).val), "=&r" (_tmp) \
471 : "i" (EFLAGS_MASK), "m" (_eflags), "m" ((_dst).val) ); \
472 } while (0)
473 #elif defined(__i386__)
474 #define __emulate_2op_8byte(_op, _src, _dst, _eflags, _qx, _qy)
475 #define __emulate_1op_8byte(_op, _dst, _eflags)
476 #endif /* __i386__ */
478 /* Fetch next part of the instruction being emulated. */
479 #define insn_fetch_bytes(_size) \
480 ({ unsigned long _x, _eip = _regs.eip; \
481 if ( !mode_64bit() ) _eip = (uint32_t)_eip; /* ignore upper dword */ \
482 _regs.eip += (_size); /* real hardware doesn't truncate */ \
483 generate_exception_if((uint8_t)(_regs.eip - ctxt->regs->eip) > 15, \
484 EXC_GP); \
485 rc = ops->insn_fetch(x86_seg_cs, _eip, &_x, (_size), ctxt); \
486 if ( rc ) goto done; \
487 _x; \
488 })
489 #define insn_fetch_type(_type) ((_type)insn_fetch_bytes(sizeof(_type)))
491 #define truncate_word(ea, byte_width) \
492 ({ unsigned long __ea = (ea); \
493 unsigned int _width = (byte_width); \
494 ((_width == sizeof(unsigned long)) ? __ea : \
495 (__ea & ((1UL << (_width << 3)) - 1))); \
496 })
497 #define truncate_ea(ea) truncate_word((ea), ad_bytes)
499 #define mode_64bit() (def_ad_bytes == 8)
501 #define fail_if(p) \
502 do { \
503 rc = (p) ? X86EMUL_UNHANDLEABLE : X86EMUL_OKAY; \
504 if ( rc ) goto done; \
505 } while (0)
507 #define generate_exception_if(p, e) \
508 ({ if ( (p) ) { \
509 fail_if(ops->inject_hw_exception == NULL); \
510 rc = ops->inject_hw_exception(e, 0, ctxt) ? : X86EMUL_EXCEPTION; \
511 goto done; \
512 } \
513 })
515 /*
516 * Given byte has even parity (even number of 1s)? SDM Vol. 1 Sec. 3.4.3.1,
517 * "Status Flags": EFLAGS.PF reflects parity of least-sig. byte of result only.
518 */
519 static int even_parity(uint8_t v)
520 {
521 asm ( "test %b0,%b0; setp %b0" : "=a" (v) : "0" (v) );
522 return v;
523 }
525 /* Update address held in a register, based on addressing mode. */
526 #define _register_address_increment(reg, inc, byte_width) \
527 do { \
528 int _inc = (inc); /* signed type ensures sign extension to long */ \
529 unsigned int _width = (byte_width); \
530 if ( _width == sizeof(unsigned long) ) \
531 (reg) += _inc; \
532 else if ( mode_64bit() ) \
533 (reg) = ((reg) + _inc) & ((1UL << (_width << 3)) - 1); \
534 else \
535 (reg) = ((reg) & ~((1UL << (_width << 3)) - 1)) | \
536 (((reg) + _inc) & ((1UL << (_width << 3)) - 1)); \
537 } while (0)
538 #define register_address_increment(reg, inc) \
539 _register_address_increment((reg), (inc), ad_bytes)
541 #define sp_pre_dec(dec) ({ \
542 _register_address_increment(_regs.esp, -(dec), ctxt->sp_size/8); \
543 truncate_word(_regs.esp, ctxt->sp_size/8); \
544 })
545 #define sp_post_inc(inc) ({ \
546 unsigned long __esp = truncate_word(_regs.esp, ctxt->sp_size/8); \
547 _register_address_increment(_regs.esp, (inc), ctxt->sp_size/8); \
548 __esp; \
549 })
551 #define jmp_rel(rel) \
552 do { \
553 int _rel = (int)(rel); \
554 _regs.eip += _rel; \
555 if ( !mode_64bit() ) \
556 _regs.eip = ((op_bytes == 2) \
557 ? (uint16_t)_regs.eip : (uint32_t)_regs.eip); \
558 } while (0)
560 static unsigned long __get_rep_prefix(
561 struct cpu_user_regs *int_regs,
562 struct cpu_user_regs *ext_regs,
563 int ad_bytes)
564 {
565 unsigned long ecx = ((ad_bytes == 2) ? (uint16_t)int_regs->ecx :
566 (ad_bytes == 4) ? (uint32_t)int_regs->ecx :
567 int_regs->ecx);
569 /* Skip the instruction if no repetitions are required. */
570 if ( ecx == 0 )
571 ext_regs->eip = int_regs->eip;
573 return ecx;
574 }
576 #define get_rep_prefix() ({ \
577 unsigned long max_reps = 1; \
578 if ( rep_prefix ) \
579 max_reps = __get_rep_prefix(&_regs, ctxt->regs, ad_bytes); \
580 if ( max_reps == 0 ) \
581 goto done; \
582 max_reps; \
583 })
585 static void __put_rep_prefix(
586 struct cpu_user_regs *int_regs,
587 struct cpu_user_regs *ext_regs,
588 int ad_bytes,
589 unsigned long reps_completed)
590 {
591 unsigned long ecx = ((ad_bytes == 2) ? (uint16_t)int_regs->ecx :
592 (ad_bytes == 4) ? (uint32_t)int_regs->ecx :
593 int_regs->ecx);
595 /* Reduce counter appropriately, and repeat instruction if non-zero. */
596 ecx -= reps_completed;
597 if ( ecx != 0 )
598 int_regs->eip = ext_regs->eip;
600 if ( ad_bytes == 2 )
601 *(uint16_t *)&int_regs->ecx = ecx;
602 else if ( ad_bytes == 4 )
603 int_regs->ecx = (uint32_t)ecx;
604 else
605 int_regs->ecx = ecx;
606 }
608 #define put_rep_prefix(reps_completed) ({ \
609 if ( rep_prefix ) \
610 __put_rep_prefix(&_regs, ctxt->regs, ad_bytes, reps_completed); \
611 })
613 /*
614 * Unsigned multiplication with double-word result.
615 * IN: Multiplicand=m[0], Multiplier=m[1]
616 * OUT: Return CF/OF (overflow status); Result=m[1]:m[0]
617 */
618 static int mul_dbl(unsigned long m[2])
619 {
620 int rc;
621 asm ( "mul %4; seto %b2"
622 : "=a" (m[0]), "=d" (m[1]), "=q" (rc)
623 : "0" (m[0]), "1" (m[1]), "2" (0) );
624 return rc;
625 }
627 /*
628 * Signed multiplication with double-word result.
629 * IN: Multiplicand=m[0], Multiplier=m[1]
630 * OUT: Return CF/OF (overflow status); Result=m[1]:m[0]
631 */
632 static int imul_dbl(unsigned long m[2])
633 {
634 int rc;
635 asm ( "imul %4; seto %b2"
636 : "=a" (m[0]), "=d" (m[1]), "=q" (rc)
637 : "0" (m[0]), "1" (m[1]), "2" (0) );
638 return rc;
639 }
641 /*
642 * Unsigned division of double-word dividend.
643 * IN: Dividend=u[1]:u[0], Divisor=v
644 * OUT: Return 1: #DE
645 * Return 0: Quotient=u[0], Remainder=u[1]
646 */
647 static int div_dbl(unsigned long u[2], unsigned long v)
648 {
649 if ( (v == 0) || (u[1] >= v) )
650 return 1;
651 asm ( "div %4"
652 : "=a" (u[0]), "=d" (u[1])
653 : "0" (u[0]), "1" (u[1]), "r" (v) );
654 return 0;
655 }
657 /*
658 * Signed division of double-word dividend.
659 * IN: Dividend=u[1]:u[0], Divisor=v
660 * OUT: Return 1: #DE
661 * Return 0: Quotient=u[0], Remainder=u[1]
662 * NB. We don't use idiv directly as it's moderately hard to work out
663 * ahead of time whether it will #DE, which we cannot allow to happen.
664 */
665 static int idiv_dbl(unsigned long u[2], unsigned long v)
666 {
667 int negu = (long)u[1] < 0, negv = (long)v < 0;
669 /* u = abs(u) */
670 if ( negu )
671 {
672 u[1] = ~u[1];
673 if ( (u[0] = -u[0]) == 0 )
674 u[1]++;
675 }
677 /* abs(u) / abs(v) */
678 if ( div_dbl(u, negv ? -v : v) )
679 return 1;
681 /* Remainder has same sign as dividend. It cannot overflow. */
682 if ( negu )
683 u[1] = -u[1];
685 /* Quotient is overflowed if sign bit is set. */
686 if ( negu ^ negv )
687 {
688 if ( (long)u[0] >= 0 )
689 u[0] = -u[0];
690 else if ( (u[0] << 1) != 0 ) /* == 0x80...0 is okay */
691 return 1;
692 }
693 else if ( (long)u[0] < 0 )
694 return 1;
696 return 0;
697 }
699 static int
700 test_cc(
701 unsigned int condition, unsigned int flags)
702 {
703 int rc = 0;
705 switch ( (condition & 15) >> 1 )
706 {
707 case 0: /* o */
708 rc |= (flags & EFLG_OF);
709 break;
710 case 1: /* b/c/nae */
711 rc |= (flags & EFLG_CF);
712 break;
713 case 2: /* z/e */
714 rc |= (flags & EFLG_ZF);
715 break;
716 case 3: /* be/na */
717 rc |= (flags & (EFLG_CF|EFLG_ZF));
718 break;
719 case 4: /* s */
720 rc |= (flags & EFLG_SF);
721 break;
722 case 5: /* p/pe */
723 rc |= (flags & EFLG_PF);
724 break;
725 case 7: /* le/ng */
726 rc |= (flags & EFLG_ZF);
727 /* fall through */
728 case 6: /* l/nge */
729 rc |= (!(flags & EFLG_SF) != !(flags & EFLG_OF));
730 break;
731 }
733 /* Odd condition identifiers (lsb == 1) have inverted sense. */
734 return (!!rc ^ (condition & 1));
735 }
737 static int
738 get_cpl(
739 struct x86_emulate_ctxt *ctxt,
740 struct x86_emulate_ops *ops)
741 {
742 struct segment_register reg;
744 if ( ctxt->regs->eflags & EFLG_VM )
745 return 3;
747 if ( (ops->read_segment == NULL) ||
748 ops->read_segment(x86_seg_ss, &reg, ctxt) )
749 return -1;
751 return reg.attr.fields.dpl;
752 }
754 static int
755 _mode_iopl(
756 struct x86_emulate_ctxt *ctxt,
757 struct x86_emulate_ops *ops)
758 {
759 int cpl = get_cpl(ctxt, ops);
760 return ((cpl >= 0) && (cpl <= ((ctxt->regs->eflags >> 12) & 3)));
761 }
763 #define mode_ring0() (get_cpl(ctxt, ops) == 0)
764 #define mode_iopl() _mode_iopl(ctxt, ops)
766 static int
767 in_realmode(
768 struct x86_emulate_ctxt *ctxt,
769 struct x86_emulate_ops *ops)
770 {
771 unsigned long cr0;
772 int rc;
774 if ( ops->read_cr == NULL )
775 return 0;
777 rc = ops->read_cr(0, &cr0, ctxt);
778 return (!rc && !(cr0 & CR0_PE));
779 }
781 static int
782 realmode_load_seg(
783 enum x86_segment seg,
784 uint16_t sel,
785 struct x86_emulate_ctxt *ctxt,
786 struct x86_emulate_ops *ops)
787 {
788 struct segment_register reg;
789 int rc;
791 if ( (rc = ops->read_segment(seg, &reg, ctxt)) != 0 )
792 return rc;
794 reg.sel = sel;
795 reg.base = (uint32_t)sel << 4;
797 return ops->write_segment(seg, &reg, ctxt);
798 }
800 static int
801 protmode_load_seg(
802 enum x86_segment seg,
803 uint16_t sel,
804 struct x86_emulate_ctxt *ctxt,
805 struct x86_emulate_ops *ops)
806 {
807 struct segment_register desctab, cs, segr;
808 struct { uint32_t a, b; } desc;
809 unsigned long val;
810 uint8_t dpl, rpl, cpl;
811 int rc, fault_type = EXC_TS;
813 /* NULL selector? */
814 if ( (sel & 0xfffc) == 0 )
815 {
816 if ( (seg == x86_seg_cs) || (seg == x86_seg_ss) )
817 goto raise_exn;
818 memset(&segr, 0, sizeof(segr));
819 return ops->write_segment(seg, &segr, ctxt);
820 }
822 /* LDT descriptor must be in the GDT. */
823 if ( (seg == x86_seg_ldtr) && (sel & 4) )
824 goto raise_exn;
826 if ( (rc = ops->read_segment(x86_seg_cs, &cs, ctxt)) ||
827 (rc = ops->read_segment((sel & 4) ? x86_seg_ldtr : x86_seg_gdtr,
828 &desctab, ctxt)) )
829 return rc;
831 /* Check against descriptor table limit. */
832 if ( ((sel & 0xfff8) + 7) > desctab.limit )
833 goto raise_exn;
835 do {
836 if ( (rc = ops->read(x86_seg_none, desctab.base + (sel & 0xfff8),
837 &val, 4, ctxt)) )
838 return rc;
839 desc.a = val;
840 if ( (rc = ops->read(x86_seg_none, desctab.base + (sel & 0xfff8) + 4,
841 &val, 4, ctxt)) )
842 return rc;
843 desc.b = val;
845 /* Segment present in memory? */
846 if ( !(desc.b & (1u<<15)) )
847 {
848 fault_type = EXC_NP;
849 goto raise_exn;
850 }
852 /* LDT descriptor is a system segment. All others are code/data. */
853 if ( (desc.b & (1u<<12)) == ((seg == x86_seg_ldtr) << 12) )
854 goto raise_exn;
856 dpl = (desc.b >> 13) & 3;
857 rpl = sel & 3;
858 cpl = cs.sel & 3;
860 switch ( seg )
861 {
862 case x86_seg_cs:
863 /* Code segment? */
864 if ( !(desc.b & (1u<<11)) )
865 goto raise_exn;
866 /* Non-conforming segment: check DPL against RPL. */
867 if ( ((desc.b & (6u<<9)) != 6) && (dpl != rpl) )
868 goto raise_exn;
869 break;
870 case x86_seg_ss:
871 /* Writable data segment? */
872 if ( (desc.b & (5u<<9)) != (1u<<9) )
873 goto raise_exn;
874 if ( (dpl != cpl) || (dpl != rpl) )
875 goto raise_exn;
876 break;
877 case x86_seg_ldtr:
878 /* LDT system segment? */
879 if ( (desc.b & (15u<<8)) != (2u<<8) )
880 goto raise_exn;
881 goto skip_accessed_flag;
882 default:
883 /* Readable code or data segment? */
884 if ( (desc.b & (5u<<9)) == (4u<<9) )
885 goto raise_exn;
886 /* Non-conforming segment: check DPL against RPL and CPL. */
887 if ( ((desc.b & (6u<<9)) != 6) && ((dpl < cpl) || (dpl < rpl)) )
888 goto raise_exn;
889 break;
890 }
892 /* Ensure Accessed flag is set. */
893 rc = ((desc.b & 0x100) ? X86EMUL_OKAY :
894 ops->cmpxchg(
895 x86_seg_none, desctab.base + (sel & 0xfff8) + 4, desc.b,
896 desc.b | 0x100, 4, ctxt));
897 } while ( rc == X86EMUL_CMPXCHG_FAILED );
899 if ( rc )
900 return rc;
902 /* Force the Accessed flag in our local copy. */
903 desc.b |= 0x100;
905 skip_accessed_flag:
906 segr.base = (((desc.b << 0) & 0xff000000u) |
907 ((desc.b << 16) & 0x00ff0000u) |
908 ((desc.a >> 16) & 0x0000ffffu));
909 segr.attr.bytes = (((desc.b >> 8) & 0x00ffu) |
910 ((desc.b >> 12) & 0x0f00u));
911 segr.limit = (desc.b & 0x000f0000u) | (desc.a & 0x0000ffffu);
912 if ( segr.attr.fields.g )
913 segr.limit = (segr.limit << 12) | 0xfffu;
914 segr.sel = sel;
915 return ops->write_segment(seg, &segr, ctxt);
917 raise_exn:
918 if ( ops->inject_hw_exception == NULL )
919 return X86EMUL_UNHANDLEABLE;
920 if ( (rc = ops->inject_hw_exception(fault_type, sel & 0xfffc, ctxt)) )
921 return rc;
922 return X86EMUL_EXCEPTION;
923 }
925 static int
926 load_seg(
927 enum x86_segment seg,
928 uint16_t sel,
929 struct x86_emulate_ctxt *ctxt,
930 struct x86_emulate_ops *ops)
931 {
932 if ( (ops->read_segment == NULL) ||
933 (ops->write_segment == NULL) )
934 return X86EMUL_UNHANDLEABLE;
936 if ( in_realmode(ctxt, ops) )
937 return realmode_load_seg(seg, sel, ctxt, ops);
939 return protmode_load_seg(seg, sel, ctxt, ops);
940 }
942 void *
943 decode_register(
944 uint8_t modrm_reg, struct cpu_user_regs *regs, int highbyte_regs)
945 {
946 void *p;
948 switch ( modrm_reg )
949 {
950 case 0: p = &regs->eax; break;
951 case 1: p = &regs->ecx; break;
952 case 2: p = &regs->edx; break;
953 case 3: p = &regs->ebx; break;
954 case 4: p = (highbyte_regs ?
955 ((unsigned char *)&regs->eax + 1) :
956 (unsigned char *)&regs->esp); break;
957 case 5: p = (highbyte_regs ?
958 ((unsigned char *)&regs->ecx + 1) :
959 (unsigned char *)&regs->ebp); break;
960 case 6: p = (highbyte_regs ?
961 ((unsigned char *)&regs->edx + 1) :
962 (unsigned char *)&regs->esi); break;
963 case 7: p = (highbyte_regs ?
964 ((unsigned char *)&regs->ebx + 1) :
965 (unsigned char *)&regs->edi); break;
966 #if defined(__x86_64__)
967 case 8: p = &regs->r8; break;
968 case 9: p = &regs->r9; break;
969 case 10: p = &regs->r10; break;
970 case 11: p = &regs->r11; break;
971 case 12: p = &regs->r12; break;
972 case 13: p = &regs->r13; break;
973 case 14: p = &regs->r14; break;
974 case 15: p = &regs->r15; break;
975 #endif
976 default: p = NULL; break;
977 }
979 return p;
980 }
982 #define decode_segment_failed x86_seg_tr
983 enum x86_segment
984 decode_segment(
985 uint8_t modrm_reg)
986 {
987 switch ( modrm_reg )
988 {
989 case 0: return x86_seg_es;
990 case 1: return x86_seg_cs;
991 case 2: return x86_seg_ss;
992 case 3: return x86_seg_ds;
993 case 4: return x86_seg_fs;
994 case 5: return x86_seg_gs;
995 default: break;
996 }
997 return decode_segment_failed;
998 }
1000 int
1001 x86_emulate(
1002 struct x86_emulate_ctxt *ctxt,
1003 struct x86_emulate_ops *ops)
1005 /* Shadow copy of register state. Committed on successful emulation. */
1006 struct cpu_user_regs _regs = *ctxt->regs;
1008 uint8_t b, d, sib, sib_index, sib_base, twobyte = 0, rex_prefix = 0;
1009 uint8_t modrm = 0, modrm_mod = 0, modrm_reg = 0, modrm_rm = 0;
1010 unsigned int op_bytes, def_op_bytes, ad_bytes, def_ad_bytes;
1011 #define REPE_PREFIX 1
1012 #define REPNE_PREFIX 2
1013 unsigned int lock_prefix = 0, rep_prefix = 0;
1014 int override_seg = -1, rc = X86EMUL_OKAY;
1015 struct operand src, dst;
1017 /* Data operand effective address (usually computed from ModRM). */
1018 struct operand ea;
1020 /* Default is a memory operand relative to segment DS. */
1021 ea.type = OP_MEM;
1022 ea.mem.seg = x86_seg_ds;
1023 ea.mem.off = 0;
1025 op_bytes = def_op_bytes = ad_bytes = def_ad_bytes = ctxt->addr_size/8;
1026 if ( op_bytes == 8 )
1028 op_bytes = def_op_bytes = 4;
1029 #ifndef __x86_64__
1030 return X86EMUL_UNHANDLEABLE;
1031 #endif
1034 /* Prefix bytes. */
1035 for ( ; ; )
1037 switch ( b = insn_fetch_type(uint8_t) )
1039 case 0x66: /* operand-size override */
1040 op_bytes = def_op_bytes ^ 6;
1041 break;
1042 case 0x67: /* address-size override */
1043 ad_bytes = def_ad_bytes ^ (mode_64bit() ? 12 : 6);
1044 break;
1045 case 0x2e: /* CS override */
1046 override_seg = x86_seg_cs;
1047 break;
1048 case 0x3e: /* DS override */
1049 override_seg = x86_seg_ds;
1050 break;
1051 case 0x26: /* ES override */
1052 override_seg = x86_seg_es;
1053 break;
1054 case 0x64: /* FS override */
1055 override_seg = x86_seg_fs;
1056 break;
1057 case 0x65: /* GS override */
1058 override_seg = x86_seg_gs;
1059 break;
1060 case 0x36: /* SS override */
1061 override_seg = x86_seg_ss;
1062 break;
1063 case 0xf0: /* LOCK */
1064 lock_prefix = 1;
1065 break;
1066 case 0xf2: /* REPNE/REPNZ */
1067 rep_prefix = REPNE_PREFIX;
1068 break;
1069 case 0xf3: /* REP/REPE/REPZ */
1070 rep_prefix = REPE_PREFIX;
1071 break;
1072 case 0x40 ... 0x4f: /* REX */
1073 if ( !mode_64bit() )
1074 goto done_prefixes;
1075 rex_prefix = b;
1076 continue;
1077 default:
1078 goto done_prefixes;
1081 /* Any legacy prefix after a REX prefix nullifies its effect. */
1082 rex_prefix = 0;
1084 done_prefixes:
1086 if ( rex_prefix & 8 ) /* REX.W */
1087 op_bytes = 8;
1089 /* Opcode byte(s). */
1090 d = opcode_table[b];
1091 if ( d == 0 )
1093 /* Two-byte opcode? */
1094 if ( b == 0x0f )
1096 twobyte = 1;
1097 b = insn_fetch_type(uint8_t);
1098 d = twobyte_table[b];
1101 /* Unrecognised? */
1102 if ( d == 0 )
1103 goto cannot_emulate;
1106 /* Lock prefix is allowed only on RMW instructions. */
1107 generate_exception_if((d & Mov) && lock_prefix, EXC_GP);
1109 /* ModRM and SIB bytes. */
1110 if ( d & ModRM )
1112 modrm = insn_fetch_type(uint8_t);
1113 modrm_mod = (modrm & 0xc0) >> 6;
1114 modrm_reg = ((rex_prefix & 4) << 1) | ((modrm & 0x38) >> 3);
1115 modrm_rm = modrm & 0x07;
1117 if ( modrm_mod == 3 )
1119 modrm_rm |= (rex_prefix & 1) << 3;
1120 ea.type = OP_REG;
1121 ea.reg = decode_register(
1122 modrm_rm, &_regs, (d & ByteOp) && (rex_prefix == 0));
1124 else if ( ad_bytes == 2 )
1126 /* 16-bit ModR/M decode. */
1127 switch ( modrm_rm )
1129 case 0:
1130 ea.mem.off = _regs.ebx + _regs.esi;
1131 break;
1132 case 1:
1133 ea.mem.off = _regs.ebx + _regs.edi;
1134 break;
1135 case 2:
1136 ea.mem.seg = x86_seg_ss;
1137 ea.mem.off = _regs.ebp + _regs.esi;
1138 break;
1139 case 3:
1140 ea.mem.seg = x86_seg_ss;
1141 ea.mem.off = _regs.ebp + _regs.edi;
1142 break;
1143 case 4:
1144 ea.mem.off = _regs.esi;
1145 break;
1146 case 5:
1147 ea.mem.off = _regs.edi;
1148 break;
1149 case 6:
1150 if ( modrm_mod == 0 )
1151 break;
1152 ea.mem.seg = x86_seg_ss;
1153 ea.mem.off = _regs.ebp;
1154 break;
1155 case 7:
1156 ea.mem.off = _regs.ebx;
1157 break;
1159 switch ( modrm_mod )
1161 case 0:
1162 if ( modrm_rm == 6 )
1163 ea.mem.off = insn_fetch_type(int16_t);
1164 break;
1165 case 1:
1166 ea.mem.off += insn_fetch_type(int8_t);
1167 break;
1168 case 2:
1169 ea.mem.off += insn_fetch_type(int16_t);
1170 break;
1172 ea.mem.off = truncate_ea(ea.mem.off);
1174 else
1176 /* 32/64-bit ModR/M decode. */
1177 if ( modrm_rm == 4 )
1179 sib = insn_fetch_type(uint8_t);
1180 sib_index = ((sib >> 3) & 7) | ((rex_prefix << 2) & 8);
1181 sib_base = (sib & 7) | ((rex_prefix << 3) & 8);
1182 if ( sib_index != 4 )
1183 ea.mem.off = *(long*)decode_register(sib_index, &_regs, 0);
1184 ea.mem.off <<= (sib >> 6) & 3;
1185 if ( (modrm_mod == 0) && ((sib_base & 7) == 5) )
1186 ea.mem.off += insn_fetch_type(int32_t);
1187 else if ( sib_base == 4 )
1189 ea.mem.seg = x86_seg_ss;
1190 ea.mem.off += _regs.esp;
1191 if ( !twobyte && (b == 0x8f) )
1192 /* POP <rm> computes its EA post increment. */
1193 ea.mem.off += ((mode_64bit() && (op_bytes == 4))
1194 ? 8 : op_bytes);
1196 else if ( sib_base == 5 )
1198 ea.mem.seg = x86_seg_ss;
1199 ea.mem.off += _regs.ebp;
1201 else
1202 ea.mem.off += *(long*)decode_register(sib_base, &_regs, 0);
1204 else
1206 modrm_rm |= (rex_prefix & 1) << 3;
1207 ea.mem.off = *(long *)decode_register(modrm_rm, &_regs, 0);
1208 if ( (modrm_rm == 5) && (modrm_mod != 0) )
1209 ea.mem.seg = x86_seg_ss;
1211 switch ( modrm_mod )
1213 case 0:
1214 if ( (modrm_rm & 7) != 5 )
1215 break;
1216 ea.mem.off = insn_fetch_type(int32_t);
1217 if ( !mode_64bit() )
1218 break;
1219 /* Relative to RIP of next instruction. Argh! */
1220 ea.mem.off += _regs.eip;
1221 if ( (d & SrcMask) == SrcImm )
1222 ea.mem.off += (d & ByteOp) ? 1 :
1223 ((op_bytes == 8) ? 4 : op_bytes);
1224 else if ( (d & SrcMask) == SrcImmByte )
1225 ea.mem.off += 1;
1226 else if ( !twobyte && ((b & 0xfe) == 0xf6) &&
1227 ((modrm_reg & 7) <= 1) )
1228 /* Special case in Grp3: test has immediate operand. */
1229 ea.mem.off += (d & ByteOp) ? 1
1230 : ((op_bytes == 8) ? 4 : op_bytes);
1231 else if ( twobyte && ((b & 0xf7) == 0xa4) )
1232 /* SHLD/SHRD with immediate byte third operand. */
1233 ea.mem.off++;
1234 break;
1235 case 1:
1236 ea.mem.off += insn_fetch_type(int8_t);
1237 break;
1238 case 2:
1239 ea.mem.off += insn_fetch_type(int32_t);
1240 break;
1242 ea.mem.off = truncate_ea(ea.mem.off);
1246 if ( override_seg != -1 )
1247 ea.mem.seg = override_seg;
1249 /* Special instructions do their own operand decoding. */
1250 if ( (d & DstMask) == ImplicitOps )
1251 goto special_insn;
1253 /* Decode and fetch the source operand: register, memory or immediate. */
1254 switch ( d & SrcMask )
1256 case SrcNone:
1257 break;
1258 case SrcReg:
1259 src.type = OP_REG;
1260 if ( d & ByteOp )
1262 src.reg = decode_register(modrm_reg, &_regs, (rex_prefix == 0));
1263 src.val = *(uint8_t *)src.reg;
1264 src.bytes = 1;
1266 else
1268 src.reg = decode_register(modrm_reg, &_regs, 0);
1269 switch ( (src.bytes = op_bytes) )
1271 case 2: src.val = *(uint16_t *)src.reg; break;
1272 case 4: src.val = *(uint32_t *)src.reg; break;
1273 case 8: src.val = *(uint64_t *)src.reg; break;
1276 break;
1277 case SrcMem16:
1278 ea.bytes = 2;
1279 goto srcmem_common;
1280 case SrcMem:
1281 ea.bytes = (d & ByteOp) ? 1 : op_bytes;
1282 srcmem_common:
1283 src = ea;
1284 if ( src.type == OP_REG )
1286 switch ( src.bytes )
1288 case 1: src.val = *(uint8_t *)src.reg; break;
1289 case 2: src.val = *(uint16_t *)src.reg; break;
1290 case 4: src.val = *(uint32_t *)src.reg; break;
1291 case 8: src.val = *(uint64_t *)src.reg; break;
1294 else if ( (rc = ops->read(src.mem.seg, src.mem.off,
1295 &src.val, src.bytes, ctxt)) )
1296 goto done;
1297 break;
1298 case SrcImm:
1299 src.type = OP_IMM;
1300 src.bytes = (d & ByteOp) ? 1 : op_bytes;
1301 if ( src.bytes == 8 ) src.bytes = 4;
1302 /* NB. Immediates are sign-extended as necessary. */
1303 switch ( src.bytes )
1305 case 1: src.val = insn_fetch_type(int8_t); break;
1306 case 2: src.val = insn_fetch_type(int16_t); break;
1307 case 4: src.val = insn_fetch_type(int32_t); break;
1309 break;
1310 case SrcImmByte:
1311 src.type = OP_IMM;
1312 src.bytes = 1;
1313 src.val = insn_fetch_type(int8_t);
1314 break;
1317 /* Decode and fetch the destination operand: register or memory. */
1318 switch ( d & DstMask )
1320 case DstReg:
1321 dst.type = OP_REG;
1322 if ( d & ByteOp )
1324 dst.reg = decode_register(modrm_reg, &_regs, (rex_prefix == 0));
1325 dst.val = *(uint8_t *)dst.reg;
1326 dst.bytes = 1;
1328 else
1330 dst.reg = decode_register(modrm_reg, &_regs, 0);
1331 switch ( (dst.bytes = op_bytes) )
1333 case 2: dst.val = *(uint16_t *)dst.reg; break;
1334 case 4: dst.val = *(uint32_t *)dst.reg; break;
1335 case 8: dst.val = *(uint64_t *)dst.reg; break;
1338 break;
1339 case DstBitBase:
1340 if ( ((d & SrcMask) == SrcImmByte) || (ea.type == OP_REG) )
1342 src.val &= (op_bytes << 3) - 1;
1344 else
1346 /*
1347 * EA += BitOffset DIV op_bytes*8
1348 * BitOffset = BitOffset MOD op_bytes*8
1349 * DIV truncates towards negative infinity.
1350 * MOD always produces a positive result.
1351 */
1352 if ( op_bytes == 2 )
1353 src.val = (int16_t)src.val;
1354 else if ( op_bytes == 4 )
1355 src.val = (int32_t)src.val;
1356 if ( (long)src.val < 0 )
1358 unsigned long byte_offset;
1359 byte_offset = op_bytes + (((-src.val-1) >> 3) & ~(op_bytes-1));
1360 ea.mem.off -= byte_offset;
1361 src.val = (byte_offset << 3) + src.val;
1363 else
1365 ea.mem.off += (src.val >> 3) & ~(op_bytes - 1);
1366 src.val &= (op_bytes << 3) - 1;
1369 /* Becomes a normal DstMem operation from here on. */
1370 d = (d & ~DstMask) | DstMem;
1371 case DstMem:
1372 ea.bytes = (d & ByteOp) ? 1 : op_bytes;
1373 dst = ea;
1374 if ( dst.type == OP_REG )
1376 switch ( dst.bytes )
1378 case 1: dst.val = *(uint8_t *)dst.reg; break;
1379 case 2: dst.val = *(uint16_t *)dst.reg; break;
1380 case 4: dst.val = *(uint32_t *)dst.reg; break;
1381 case 8: dst.val = *(uint64_t *)dst.reg; break;
1384 else if ( !(d & Mov) ) /* optimisation - avoid slow emulated read */
1386 if ( (rc = ops->read(dst.mem.seg, dst.mem.off,
1387 &dst.val, dst.bytes, ctxt)) )
1388 goto done;
1389 dst.orig_val = dst.val;
1391 break;
1394 /* LOCK prefix allowed only on instructions with memory destination. */
1395 generate_exception_if(lock_prefix && (dst.type != OP_MEM), EXC_GP);
1397 if ( twobyte )
1398 goto twobyte_insn;
1400 switch ( b )
1402 case 0x04 ... 0x05: /* add imm,%%eax */
1403 dst.reg = (unsigned long *)&_regs.eax;
1404 dst.val = _regs.eax;
1405 case 0x00 ... 0x03: add: /* add */
1406 emulate_2op_SrcV("add", src, dst, _regs.eflags);
1407 break;
1409 case 0x0c ... 0x0d: /* or imm,%%eax */
1410 dst.reg = (unsigned long *)&_regs.eax;
1411 dst.val = _regs.eax;
1412 case 0x08 ... 0x0b: or: /* or */
1413 emulate_2op_SrcV("or", src, dst, _regs.eflags);
1414 break;
1416 case 0x14 ... 0x15: /* adc imm,%%eax */
1417 dst.reg = (unsigned long *)&_regs.eax;
1418 dst.val = _regs.eax;
1419 case 0x10 ... 0x13: adc: /* adc */
1420 emulate_2op_SrcV("adc", src, dst, _regs.eflags);
1421 break;
1423 case 0x1c ... 0x1d: /* sbb imm,%%eax */
1424 dst.reg = (unsigned long *)&_regs.eax;
1425 dst.val = _regs.eax;
1426 case 0x18 ... 0x1b: sbb: /* sbb */
1427 emulate_2op_SrcV("sbb", src, dst, _regs.eflags);
1428 break;
1430 case 0x24 ... 0x25: /* and imm,%%eax */
1431 dst.reg = (unsigned long *)&_regs.eax;
1432 dst.val = _regs.eax;
1433 case 0x20 ... 0x23: and: /* and */
1434 emulate_2op_SrcV("and", src, dst, _regs.eflags);
1435 break;
1437 case 0x2c ... 0x2d: /* sub imm,%%eax */
1438 dst.reg = (unsigned long *)&_regs.eax;
1439 dst.val = _regs.eax;
1440 case 0x28 ... 0x2b: sub: /* sub */
1441 emulate_2op_SrcV("sub", src, dst, _regs.eflags);
1442 break;
1444 case 0x34 ... 0x35: /* xor imm,%%eax */
1445 dst.reg = (unsigned long *)&_regs.eax;
1446 dst.val = _regs.eax;
1447 case 0x30 ... 0x33: xor: /* xor */
1448 emulate_2op_SrcV("xor", src, dst, _regs.eflags);
1449 break;
1451 case 0x3c ... 0x3d: /* cmp imm,%%eax */
1452 dst.reg = (unsigned long *)&_regs.eax;
1453 dst.val = _regs.eax;
1454 case 0x38 ... 0x3b: cmp: /* cmp */
1455 emulate_2op_SrcV("cmp", src, dst, _regs.eflags);
1456 break;
1458 case 0x62: /* bound */ {
1459 unsigned long src_val2;
1460 int lb, ub, idx;
1461 generate_exception_if(mode_64bit() || (src.type != OP_MEM), EXC_UD);
1462 if ( (rc = ops->read(src.mem.seg, src.mem.off + op_bytes,
1463 &src_val2, op_bytes, ctxt)) )
1464 goto done;
1465 ub = (op_bytes == 2) ? (int16_t)src_val2 : (int32_t)src_val2;
1466 lb = (op_bytes == 2) ? (int16_t)src.val : (int32_t)src.val;
1467 idx = (op_bytes == 2) ? (int16_t)dst.val : (int32_t)dst.val;
1468 generate_exception_if((idx < lb) || (idx > ub), EXC_BR);
1469 dst.type = OP_NONE;
1470 break;
1473 case 0x63: /* movsxd (x86/64) / arpl (x86/32) */
1474 if ( mode_64bit() )
1476 /* movsxd */
1477 if ( src.type == OP_REG )
1478 src.val = *(int32_t *)src.reg;
1479 else if ( (rc = ops->read(src.mem.seg, src.mem.off,
1480 &src.val, 4, ctxt)) )
1481 goto done;
1482 dst.val = (int32_t)src.val;
1484 else
1486 /* arpl */
1487 uint16_t src_val = dst.val;
1488 dst = src;
1489 _regs.eflags &= ~EFLG_ZF;
1490 _regs.eflags |= ((src_val & 3) > (dst.val & 3)) ? EFLG_ZF : 0;
1491 if ( _regs.eflags & EFLG_ZF )
1492 dst.val = (dst.val & ~3) | (src_val & 3);
1493 else
1494 dst.type = OP_NONE;
1495 generate_exception_if(in_realmode(ctxt, ops), EXC_UD);
1497 break;
1499 case 0x69: /* imul imm16/32 */
1500 case 0x6b: /* imul imm8 */ {
1501 unsigned long src1; /* ModR/M source operand */
1502 if ( ea.type == OP_REG )
1503 src1 = *ea.reg;
1504 else if ( (rc = ops->read(ea.mem.seg, ea.mem.off,
1505 &src1, op_bytes, ctxt)) )
1506 goto done;
1507 _regs.eflags &= ~(EFLG_OF|EFLG_CF);
1508 switch ( dst.bytes )
1510 case 2:
1511 dst.val = ((uint32_t)(int16_t)src.val *
1512 (uint32_t)(int16_t)src1);
1513 if ( (int16_t)dst.val != (uint32_t)dst.val )
1514 _regs.eflags |= EFLG_OF|EFLG_CF;
1515 break;
1516 #ifdef __x86_64__
1517 case 4:
1518 dst.val = ((uint64_t)(int32_t)src.val *
1519 (uint64_t)(int32_t)src1);
1520 if ( (int32_t)dst.val != dst.val )
1521 _regs.eflags |= EFLG_OF|EFLG_CF;
1522 break;
1523 #endif
1524 default: {
1525 unsigned long m[2] = { src.val, src1 };
1526 if ( imul_dbl(m) )
1527 _regs.eflags |= EFLG_OF|EFLG_CF;
1528 dst.val = m[0];
1529 break;
1532 break;
1535 case 0x82: /* Grp1 (x86/32 only) */
1536 generate_exception_if(mode_64bit(), EXC_UD);
1537 case 0x80: case 0x81: case 0x83: /* Grp1 */
1538 switch ( modrm_reg & 7 )
1540 case 0: goto add;
1541 case 1: goto or;
1542 case 2: goto adc;
1543 case 3: goto sbb;
1544 case 4: goto and;
1545 case 5: goto sub;
1546 case 6: goto xor;
1547 case 7: goto cmp;
1549 break;
1551 case 0xa8 ... 0xa9: /* test imm,%%eax */
1552 dst.reg = (unsigned long *)&_regs.eax;
1553 dst.val = _regs.eax;
1554 case 0x84 ... 0x85: test: /* test */
1555 emulate_2op_SrcV("test", src, dst, _regs.eflags);
1556 break;
1558 case 0x86 ... 0x87: xchg: /* xchg */
1559 /* Write back the register source. */
1560 switch ( dst.bytes )
1562 case 1: *(uint8_t *)src.reg = (uint8_t)dst.val; break;
1563 case 2: *(uint16_t *)src.reg = (uint16_t)dst.val; break;
1564 case 4: *src.reg = (uint32_t)dst.val; break; /* 64b reg: zero-extend */
1565 case 8: *src.reg = dst.val; break;
1567 /* Write back the memory destination with implicit LOCK prefix. */
1568 dst.val = src.val;
1569 lock_prefix = 1;
1570 break;
1572 case 0xc6 ... 0xc7: /* mov (sole member of Grp11) */
1573 generate_exception_if((modrm_reg & 7) != 0, EXC_UD);
1574 case 0x88 ... 0x8b: /* mov */
1575 dst.val = src.val;
1576 break;
1578 case 0x8c: /* mov Sreg,r/m */ {
1579 struct segment_register reg;
1580 enum x86_segment seg = decode_segment(modrm_reg);
1581 generate_exception_if(seg == decode_segment_failed, EXC_UD);
1582 fail_if(ops->read_segment == NULL);
1583 if ( (rc = ops->read_segment(seg, &reg, ctxt)) != 0 )
1584 goto done;
1585 dst.val = reg.sel;
1586 if ( dst.type == OP_MEM )
1587 dst.bytes = 2;
1588 break;
1591 case 0x8e: /* mov r/m,Sreg */ {
1592 enum x86_segment seg = decode_segment(modrm_reg);
1593 generate_exception_if(seg == decode_segment_failed, EXC_UD);
1594 if ( (rc = load_seg(seg, (uint16_t)src.val, ctxt, ops)) != 0 )
1595 goto done;
1596 dst.type = OP_NONE;
1597 break;
1600 case 0x8d: /* lea */
1601 dst.val = ea.mem.off;
1602 break;
1604 case 0x8f: /* pop (sole member of Grp1a) */
1605 generate_exception_if((modrm_reg & 7) != 0, EXC_UD);
1606 /* 64-bit mode: POP defaults to a 64-bit operand. */
1607 if ( mode_64bit() && (dst.bytes == 4) )
1608 dst.bytes = 8;
1609 if ( (rc = ops->read(x86_seg_ss, sp_post_inc(dst.bytes),
1610 &dst.val, dst.bytes, ctxt)) != 0 )
1611 goto done;
1612 break;
1614 case 0xb0 ... 0xb7: /* mov imm8,r8 */
1615 dst.reg = decode_register(
1616 (b & 7) | ((rex_prefix & 1) << 3), &_regs, (rex_prefix == 0));
1617 dst.val = src.val;
1618 break;
1620 case 0xb8 ... 0xbf: /* mov imm{16,32,64},r{16,32,64} */
1621 if ( dst.bytes == 8 ) /* Fetch more bytes to obtain imm64 */
1622 src.val = ((uint32_t)src.val |
1623 ((uint64_t)insn_fetch_type(uint32_t) << 32));
1624 dst.reg = decode_register(
1625 (b & 7) | ((rex_prefix & 1) << 3), &_regs, 0);
1626 dst.val = src.val;
1627 break;
1629 case 0xc0 ... 0xc1: grp2: /* Grp2 */
1630 switch ( modrm_reg & 7 )
1632 case 0: /* rol */
1633 emulate_2op_SrcB("rol", src, dst, _regs.eflags);
1634 break;
1635 case 1: /* ror */
1636 emulate_2op_SrcB("ror", src, dst, _regs.eflags);
1637 break;
1638 case 2: /* rcl */
1639 emulate_2op_SrcB("rcl", src, dst, _regs.eflags);
1640 break;
1641 case 3: /* rcr */
1642 emulate_2op_SrcB("rcr", src, dst, _regs.eflags);
1643 break;
1644 case 4: /* sal/shl */
1645 case 6: /* sal/shl */
1646 emulate_2op_SrcB("sal", src, dst, _regs.eflags);
1647 break;
1648 case 5: /* shr */
1649 emulate_2op_SrcB("shr", src, dst, _regs.eflags);
1650 break;
1651 case 7: /* sar */
1652 emulate_2op_SrcB("sar", src, dst, _regs.eflags);
1653 break;
1655 break;
1657 case 0xc4: /* les */ {
1658 unsigned long sel;
1659 dst.val = x86_seg_es;
1660 les: /* dst.val identifies the segment */
1661 generate_exception_if(src.type != OP_MEM, EXC_UD);
1662 if ( (rc = ops->read(src.mem.seg, src.mem.off + src.bytes,
1663 &sel, 2, ctxt)) != 0 )
1664 goto done;
1665 if ( (rc = load_seg(dst.val, (uint16_t)sel, ctxt, ops)) != 0 )
1666 goto done;
1667 dst.val = src.val;
1668 break;
1671 case 0xc5: /* lds */
1672 dst.val = x86_seg_ds;
1673 goto les;
1675 case 0xd0 ... 0xd1: /* Grp2 */
1676 src.val = 1;
1677 goto grp2;
1679 case 0xd2 ... 0xd3: /* Grp2 */
1680 src.val = _regs.ecx;
1681 goto grp2;
1683 case 0xf6 ... 0xf7: /* Grp3 */
1684 switch ( modrm_reg & 7 )
1686 case 0 ... 1: /* test */
1687 /* Special case in Grp3: test has an immediate source operand. */
1688 src.type = OP_IMM;
1689 src.bytes = (d & ByteOp) ? 1 : op_bytes;
1690 if ( src.bytes == 8 ) src.bytes = 4;
1691 switch ( src.bytes )
1693 case 1: src.val = insn_fetch_type(int8_t); break;
1694 case 2: src.val = insn_fetch_type(int16_t); break;
1695 case 4: src.val = insn_fetch_type(int32_t); break;
1697 goto test;
1698 case 2: /* not */
1699 dst.val = ~dst.val;
1700 break;
1701 case 3: /* neg */
1702 emulate_1op("neg", dst, _regs.eflags);
1703 break;
1704 case 4: /* mul */
1705 src = dst;
1706 dst.type = OP_REG;
1707 dst.reg = (unsigned long *)&_regs.eax;
1708 dst.val = *dst.reg;
1709 _regs.eflags &= ~(EFLG_OF|EFLG_CF);
1710 switch ( src.bytes )
1712 case 1:
1713 dst.val *= src.val;
1714 if ( (uint8_t)dst.val != (uint16_t)dst.val )
1715 _regs.eflags |= EFLG_OF|EFLG_CF;
1716 break;
1717 case 2:
1718 dst.val *= src.val;
1719 if ( (uint16_t)dst.val != (uint32_t)dst.val )
1720 _regs.eflags |= EFLG_OF|EFLG_CF;
1721 *(uint16_t *)&_regs.edx = dst.val >> 16;
1722 break;
1723 #ifdef __x86_64__
1724 case 4:
1725 dst.val *= src.val;
1726 if ( (uint32_t)dst.val != dst.val )
1727 _regs.eflags |= EFLG_OF|EFLG_CF;
1728 _regs.edx = (uint32_t)(dst.val >> 32);
1729 break;
1730 #endif
1731 default: {
1732 unsigned long m[2] = { src.val, dst.val };
1733 if ( mul_dbl(m) )
1734 _regs.eflags |= EFLG_OF|EFLG_CF;
1735 _regs.edx = m[1];
1736 dst.val = m[0];
1737 break;
1740 break;
1741 case 5: /* imul */
1742 src = dst;
1743 dst.type = OP_REG;
1744 dst.reg = (unsigned long *)&_regs.eax;
1745 dst.val = *dst.reg;
1746 _regs.eflags &= ~(EFLG_OF|EFLG_CF);
1747 switch ( src.bytes )
1749 case 1:
1750 dst.val = ((uint16_t)(int8_t)src.val *
1751 (uint16_t)(int8_t)dst.val);
1752 if ( (int8_t)dst.val != (uint16_t)dst.val )
1753 _regs.eflags |= EFLG_OF|EFLG_CF;
1754 break;
1755 case 2:
1756 dst.val = ((uint32_t)(int16_t)src.val *
1757 (uint32_t)(int16_t)dst.val);
1758 if ( (int16_t)dst.val != (uint32_t)dst.val )
1759 _regs.eflags |= EFLG_OF|EFLG_CF;
1760 *(uint16_t *)&_regs.edx = dst.val >> 16;
1761 break;
1762 #ifdef __x86_64__
1763 case 4:
1764 dst.val = ((uint64_t)(int32_t)src.val *
1765 (uint64_t)(int32_t)dst.val);
1766 if ( (int32_t)dst.val != dst.val )
1767 _regs.eflags |= EFLG_OF|EFLG_CF;
1768 _regs.edx = (uint32_t)(dst.val >> 32);
1769 break;
1770 #endif
1771 default: {
1772 unsigned long m[2] = { src.val, dst.val };
1773 if ( imul_dbl(m) )
1774 _regs.eflags |= EFLG_OF|EFLG_CF;
1775 _regs.edx = m[1];
1776 dst.val = m[0];
1777 break;
1780 break;
1781 case 6: /* div */ {
1782 unsigned long u[2], v;
1783 src = dst;
1784 dst.type = OP_REG;
1785 dst.reg = (unsigned long *)&_regs.eax;
1786 switch ( src.bytes )
1788 case 1:
1789 u[0] = (uint16_t)_regs.eax;
1790 u[1] = 0;
1791 v = (uint8_t)src.val;
1792 generate_exception_if(
1793 div_dbl(u, v) || ((uint8_t)u[0] != (uint16_t)u[0]),
1794 EXC_DE);
1795 dst.val = (uint8_t)u[0];
1796 ((uint8_t *)&_regs.eax)[1] = u[1];
1797 break;
1798 case 2:
1799 u[0] = ((uint32_t)_regs.edx << 16) | (uint16_t)_regs.eax;
1800 u[1] = 0;
1801 v = (uint16_t)src.val;
1802 generate_exception_if(
1803 div_dbl(u, v) || ((uint16_t)u[0] != (uint32_t)u[0]),
1804 EXC_DE);
1805 dst.val = (uint16_t)u[0];
1806 *(uint16_t *)&_regs.edx = u[1];
1807 break;
1808 #ifdef __x86_64__
1809 case 4:
1810 u[0] = (_regs.edx << 32) | (uint32_t)_regs.eax;
1811 u[1] = 0;
1812 v = (uint32_t)src.val;
1813 generate_exception_if(
1814 div_dbl(u, v) || ((uint32_t)u[0] != u[0]),
1815 EXC_DE);
1816 dst.val = (uint32_t)u[0];
1817 _regs.edx = (uint32_t)u[1];
1818 break;
1819 #endif
1820 default:
1821 u[0] = _regs.eax;
1822 u[1] = _regs.edx;
1823 v = src.val;
1824 generate_exception_if(div_dbl(u, v), EXC_DE);
1825 dst.val = u[0];
1826 _regs.edx = u[1];
1827 break;
1829 break;
1831 case 7: /* idiv */ {
1832 unsigned long u[2], v;
1833 src = dst;
1834 dst.type = OP_REG;
1835 dst.reg = (unsigned long *)&_regs.eax;
1836 switch ( src.bytes )
1838 case 1:
1839 u[0] = (int16_t)_regs.eax;
1840 u[1] = ((long)u[0] < 0) ? ~0UL : 0UL;
1841 v = (int8_t)src.val;
1842 generate_exception_if(
1843 idiv_dbl(u, v) || ((int8_t)u[0] != (int16_t)u[0]),
1844 EXC_DE);
1845 dst.val = (int8_t)u[0];
1846 ((int8_t *)&_regs.eax)[1] = u[1];
1847 break;
1848 case 2:
1849 u[0] = (int32_t)((_regs.edx << 16) | (uint16_t)_regs.eax);
1850 u[1] = ((long)u[0] < 0) ? ~0UL : 0UL;
1851 v = (int16_t)src.val;
1852 generate_exception_if(
1853 idiv_dbl(u, v) || ((int16_t)u[0] != (int32_t)u[0]),
1854 EXC_DE);
1855 dst.val = (int16_t)u[0];
1856 *(int16_t *)&_regs.edx = u[1];
1857 break;
1858 #ifdef __x86_64__
1859 case 4:
1860 u[0] = (_regs.edx << 32) | (uint32_t)_regs.eax;
1861 u[1] = ((long)u[0] < 0) ? ~0UL : 0UL;
1862 v = (int32_t)src.val;
1863 generate_exception_if(
1864 idiv_dbl(u, v) || ((int32_t)u[0] != u[0]),
1865 EXC_DE);
1866 dst.val = (int32_t)u[0];
1867 _regs.edx = (uint32_t)u[1];
1868 break;
1869 #endif
1870 default:
1871 u[0] = _regs.eax;
1872 u[1] = _regs.edx;
1873 v = src.val;
1874 generate_exception_if(idiv_dbl(u, v), EXC_DE);
1875 dst.val = u[0];
1876 _regs.edx = u[1];
1877 break;
1879 break;
1881 default:
1882 goto cannot_emulate;
1884 break;
1886 case 0xfe: /* Grp4 */
1887 generate_exception_if((modrm_reg & 7) >= 2, EXC_UD);
1888 case 0xff: /* Grp5 */
1889 switch ( modrm_reg & 7 )
1891 case 0: /* inc */
1892 emulate_1op("inc", dst, _regs.eflags);
1893 break;
1894 case 1: /* dec */
1895 emulate_1op("dec", dst, _regs.eflags);
1896 break;
1897 case 2: /* call (near) */
1898 case 4: /* jmp (near) */
1899 if ( (dst.bytes != 8) && mode_64bit() )
1901 dst.bytes = op_bytes = 8;
1902 if ( dst.type == OP_REG )
1903 dst.val = *dst.reg;
1904 else if ( (rc = ops->read(dst.mem.seg, dst.mem.off,
1905 &dst.val, 8, ctxt)) != 0 )
1906 goto done;
1908 src.val = _regs.eip;
1909 _regs.eip = dst.val;
1910 if ( (modrm_reg & 7) == 2 )
1911 goto push; /* call */
1912 dst.type = OP_NONE;
1913 break;
1914 case 3: /* call (far, absolute indirect) */
1915 case 5: /* jmp (far, absolute indirect) */ {
1916 unsigned long sel;
1918 generate_exception_if(dst.type != OP_MEM, EXC_UD);
1920 if ( (rc = ops->read(dst.mem.seg, dst.mem.off+dst.bytes,
1921 &sel, 2, ctxt)) )
1922 goto done;
1924 if ( (modrm_reg & 7) == 3 ) /* call */
1926 struct segment_register reg;
1927 fail_if(ops->read_segment == NULL);
1928 if ( (rc = ops->read_segment(x86_seg_cs, &reg, ctxt)) ||
1929 (rc = ops->write(x86_seg_ss, sp_pre_dec(op_bytes),
1930 reg.sel, op_bytes, ctxt)) ||
1931 (rc = ops->write(x86_seg_ss, sp_pre_dec(op_bytes),
1932 _regs.eip, op_bytes, ctxt)) )
1933 goto done;
1936 if ( (rc = load_seg(x86_seg_cs, sel, ctxt, ops)) != 0 )
1937 goto done;
1938 _regs.eip = dst.val;
1940 dst.type = OP_NONE;
1941 break;
1943 case 6: /* push */
1944 /* 64-bit mode: PUSH defaults to a 64-bit operand. */
1945 if ( mode_64bit() && (dst.bytes == 4) )
1947 dst.bytes = 8;
1948 if ( dst.type == OP_REG )
1949 dst.val = *dst.reg;
1950 else if ( (rc = ops->read(dst.mem.seg, dst.mem.off,
1951 &dst.val, 8, ctxt)) != 0 )
1952 goto done;
1954 if ( (rc = ops->write(x86_seg_ss, sp_pre_dec(dst.bytes),
1955 dst.val, dst.bytes, ctxt)) != 0 )
1956 goto done;
1957 dst.type = OP_NONE;
1958 break;
1959 case 7:
1960 generate_exception_if(1, EXC_UD);
1961 default:
1962 goto cannot_emulate;
1964 break;
1967 writeback:
1968 switch ( dst.type )
1970 case OP_REG:
1971 /* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */
1972 switch ( dst.bytes )
1974 case 1: *(uint8_t *)dst.reg = (uint8_t)dst.val; break;
1975 case 2: *(uint16_t *)dst.reg = (uint16_t)dst.val; break;
1976 case 4: *dst.reg = (uint32_t)dst.val; break; /* 64b: zero-ext */
1977 case 8: *dst.reg = dst.val; break;
1979 break;
1980 case OP_MEM:
1981 if ( !(d & Mov) && (dst.orig_val == dst.val) )
1982 /* nothing to do */;
1983 else if ( lock_prefix )
1984 rc = ops->cmpxchg(
1985 dst.mem.seg, dst.mem.off, dst.orig_val,
1986 dst.val, dst.bytes, ctxt);
1987 else
1988 rc = ops->write(
1989 dst.mem.seg, dst.mem.off, dst.val, dst.bytes, ctxt);
1990 if ( rc != 0 )
1991 goto done;
1992 default:
1993 break;
1996 /* Commit shadow register state. */
1997 _regs.eflags &= ~EFLG_RF;
1998 *ctxt->regs = _regs;
2000 if ( (_regs.eflags & EFLG_TF) &&
2001 (rc == X86EMUL_OKAY) &&
2002 (ops->inject_hw_exception != NULL) )
2003 rc = ops->inject_hw_exception(EXC_DB, 0, ctxt) ? : X86EMUL_EXCEPTION;
2005 done:
2006 return rc;
2008 special_insn:
2009 dst.type = OP_NONE;
2011 /*
2012 * The only implicit-operands instructions allowed a LOCK prefix are
2013 * CMPXCHG{8,16}B, MOV CRn, MOV DRn.
2014 */
2015 generate_exception_if(lock_prefix &&
2016 ((b < 0x20) || (b > 0x23)) && /* MOV CRn/DRn */
2017 (b != 0xc7), /* CMPXCHG{8,16}B */
2018 EXC_GP);
2020 if ( twobyte )
2021 goto twobyte_special_insn;
2023 switch ( b )
2025 case 0x06: /* push %%es */ {
2026 struct segment_register reg;
2027 src.val = x86_seg_es;
2028 push_seg:
2029 fail_if(ops->read_segment == NULL);
2030 if ( (rc = ops->read_segment(src.val, &reg, ctxt)) != 0 )
2031 return rc;
2032 /* 64-bit mode: PUSH defaults to a 64-bit operand. */
2033 if ( mode_64bit() && (op_bytes == 4) )
2034 op_bytes = 8;
2035 if ( (rc = ops->write(x86_seg_ss, sp_pre_dec(op_bytes),
2036 reg.sel, op_bytes, ctxt)) != 0 )
2037 goto done;
2038 break;
2041 case 0x07: /* pop %%es */
2042 src.val = x86_seg_es;
2043 pop_seg:
2044 fail_if(ops->write_segment == NULL);
2045 /* 64-bit mode: POP defaults to a 64-bit operand. */
2046 if ( mode_64bit() && (op_bytes == 4) )
2047 op_bytes = 8;
2048 if ( (rc = ops->read(x86_seg_ss, sp_post_inc(op_bytes),
2049 &dst.val, op_bytes, ctxt)) != 0 )
2050 goto done;
2051 if ( (rc = load_seg(src.val, (uint16_t)dst.val, ctxt, ops)) != 0 )
2052 return rc;
2053 break;
2055 case 0x0e: /* push %%cs */
2056 src.val = x86_seg_cs;
2057 goto push_seg;
2059 case 0x16: /* push %%ss */
2060 src.val = x86_seg_ss;
2061 goto push_seg;
2063 case 0x17: /* pop %%ss */
2064 src.val = x86_seg_ss;
2065 goto pop_seg;
2067 case 0x1e: /* push %%ds */
2068 src.val = x86_seg_ds;
2069 goto push_seg;
2071 case 0x1f: /* pop %%ds */
2072 src.val = x86_seg_ds;
2073 goto pop_seg;
2075 case 0x27: /* daa */ {
2076 uint8_t al = _regs.eax;
2077 unsigned long eflags = _regs.eflags;
2078 generate_exception_if(mode_64bit(), EXC_UD);
2079 _regs.eflags &= ~(EFLG_CF|EFLG_AF);
2080 if ( ((al & 0x0f) > 9) || (eflags & EFLG_AF) )
2082 *(uint8_t *)&_regs.eax += 6;
2083 _regs.eflags |= EFLG_AF;
2085 if ( (al > 0x99) || (eflags & EFLG_CF) )
2087 *(uint8_t *)&_regs.eax += 0x60;
2088 _regs.eflags |= EFLG_CF;
2090 _regs.eflags &= ~(EFLG_SF|EFLG_ZF|EFLG_PF);
2091 _regs.eflags |= ((uint8_t)_regs.eax == 0) ? EFLG_ZF : 0;
2092 _regs.eflags |= (( int8_t)_regs.eax < 0) ? EFLG_SF : 0;
2093 _regs.eflags |= even_parity(_regs.eax) ? EFLG_PF : 0;
2094 break;
2097 case 0x2f: /* das */ {
2098 uint8_t al = _regs.eax;
2099 unsigned long eflags = _regs.eflags;
2100 generate_exception_if(mode_64bit(), EXC_UD);
2101 _regs.eflags &= ~(EFLG_CF|EFLG_AF);
2102 if ( ((al & 0x0f) > 9) || (eflags & EFLG_AF) )
2104 _regs.eflags |= EFLG_AF;
2105 if ( (al < 6) || (eflags & EFLG_CF) )
2106 _regs.eflags |= EFLG_CF;
2107 *(uint8_t *)&_regs.eax -= 6;
2109 if ( (al > 0x99) || (eflags & EFLG_CF) )
2111 *(uint8_t *)&_regs.eax -= 0x60;
2112 _regs.eflags |= EFLG_CF;
2114 _regs.eflags &= ~(EFLG_SF|EFLG_ZF|EFLG_PF);
2115 _regs.eflags |= ((uint8_t)_regs.eax == 0) ? EFLG_ZF : 0;
2116 _regs.eflags |= (( int8_t)_regs.eax < 0) ? EFLG_SF : 0;
2117 _regs.eflags |= even_parity(_regs.eax) ? EFLG_PF : 0;
2118 break;
2121 case 0x37: /* aaa */
2122 case 0x3f: /* aas */
2123 generate_exception_if(mode_64bit(), EXC_UD);
2124 _regs.eflags &= ~EFLG_CF;
2125 if ( ((uint8_t)_regs.eax > 9) || (_regs.eflags & EFLG_AF) )
2127 ((uint8_t *)&_regs.eax)[0] += (b == 0x37) ? 6 : -6;
2128 ((uint8_t *)&_regs.eax)[1] += (b == 0x37) ? 1 : -1;
2129 _regs.eflags |= EFLG_CF | EFLG_AF;
2131 ((uint8_t *)&_regs.eax)[0] &= 0x0f;
2132 break;
2134 case 0x40 ... 0x4f: /* inc/dec reg */
2135 dst.type = OP_REG;
2136 dst.reg = decode_register(b & 7, &_regs, 0);
2137 dst.bytes = op_bytes;
2138 dst.val = *dst.reg;
2139 if ( b & 8 )
2140 emulate_1op("dec", dst, _regs.eflags);
2141 else
2142 emulate_1op("inc", dst, _regs.eflags);
2143 break;
2145 case 0x50 ... 0x57: /* push reg */
2146 src.val = *(unsigned long *)decode_register(
2147 (b & 7) | ((rex_prefix & 1) << 3), &_regs, 0);
2148 goto push;
2150 case 0x58 ... 0x5f: /* pop reg */
2151 dst.type = OP_REG;
2152 dst.reg = decode_register(
2153 (b & 7) | ((rex_prefix & 1) << 3), &_regs, 0);
2154 dst.bytes = op_bytes;
2155 if ( mode_64bit() && (dst.bytes == 4) )
2156 dst.bytes = 8;
2157 if ( (rc = ops->read(x86_seg_ss, sp_post_inc(dst.bytes),
2158 &dst.val, dst.bytes, ctxt)) != 0 )
2159 goto done;
2160 break;
2162 case 0x60: /* pusha */ {
2163 int i;
2164 unsigned long regs[] = {
2165 _regs.eax, _regs.ecx, _regs.edx, _regs.ebx,
2166 _regs.esp, _regs.ebp, _regs.esi, _regs.edi };
2167 generate_exception_if(mode_64bit(), EXC_UD);
2168 for ( i = 0; i < 8; i++ )
2169 if ( (rc = ops->write(x86_seg_ss, sp_pre_dec(op_bytes),
2170 regs[i], op_bytes, ctxt)) != 0 )
2171 goto done;
2172 break;
2175 case 0x61: /* popa */ {
2176 int i;
2177 unsigned long dummy_esp, *regs[] = {
2178 (unsigned long *)&_regs.edi, (unsigned long *)&_regs.esi,
2179 (unsigned long *)&_regs.ebp, (unsigned long *)&dummy_esp,
2180 (unsigned long *)&_regs.ebx, (unsigned long *)&_regs.edx,
2181 (unsigned long *)&_regs.ecx, (unsigned long *)&_regs.eax };
2182 generate_exception_if(mode_64bit(), EXC_UD);
2183 for ( i = 0; i < 8; i++ )
2185 if ( (rc = ops->read(x86_seg_ss, sp_post_inc(op_bytes),
2186 &dst.val, op_bytes, ctxt)) != 0 )
2187 goto done;
2188 switch ( op_bytes )
2190 case 1: *(uint8_t *)regs[i] = (uint8_t)dst.val; break;
2191 case 2: *(uint16_t *)regs[i] = (uint16_t)dst.val; break;
2192 case 4: *regs[i] = (uint32_t)dst.val; break; /* 64b: zero-ext */
2193 case 8: *regs[i] = dst.val; break;
2196 break;
2199 case 0x68: /* push imm{16,32,64} */
2200 src.val = ((op_bytes == 2)
2201 ? (int32_t)insn_fetch_type(int16_t)
2202 : insn_fetch_type(int32_t));
2203 goto push;
2205 case 0x6a: /* push imm8 */
2206 src.val = insn_fetch_type(int8_t);
2207 push:
2208 d |= Mov; /* force writeback */
2209 dst.type = OP_MEM;
2210 dst.bytes = op_bytes;
2211 if ( mode_64bit() && (dst.bytes == 4) )
2212 dst.bytes = 8;
2213 dst.val = src.val;
2214 dst.mem.seg = x86_seg_ss;
2215 dst.mem.off = sp_pre_dec(dst.bytes);
2216 break;
2218 case 0x6c ... 0x6d: /* ins %dx,%es:%edi */ {
2219 unsigned long nr_reps = get_rep_prefix();
2220 generate_exception_if(!mode_iopl(), EXC_GP);
2221 dst.bytes = !(b & 1) ? 1 : (op_bytes == 8) ? 4 : op_bytes;
2222 dst.mem.seg = x86_seg_es;
2223 dst.mem.off = truncate_ea(_regs.edi);
2224 if ( (nr_reps > 1) && (ops->rep_ins != NULL) )
2226 if ( (rc = ops->rep_ins((uint16_t)_regs.edx, dst.mem.seg,
2227 dst.mem.off, dst.bytes,
2228 &nr_reps, ctxt)) != 0 )
2229 goto done;
2231 else
2233 fail_if(ops->read_io == NULL);
2234 if ( (rc = ops->read_io((uint16_t)_regs.edx, dst.bytes,
2235 &dst.val, ctxt)) != 0 )
2236 goto done;
2237 dst.type = OP_MEM;
2238 nr_reps = 1;
2240 register_address_increment(
2241 _regs.edi,
2242 nr_reps * ((_regs.eflags & EFLG_DF) ? -dst.bytes : dst.bytes));
2243 put_rep_prefix(nr_reps);
2244 break;
2247 case 0x6e ... 0x6f: /* outs %esi,%dx */ {
2248 unsigned long nr_reps = get_rep_prefix();
2249 generate_exception_if(!mode_iopl(), EXC_GP);
2250 dst.bytes = !(b & 1) ? 1 : (op_bytes == 8) ? 4 : op_bytes;
2251 if ( (nr_reps > 1) && (ops->rep_outs != NULL) )
2253 if ( (rc = ops->rep_outs(ea.mem.seg, truncate_ea(_regs.esi),
2254 (uint16_t)_regs.edx, dst.bytes,
2255 &nr_reps, ctxt)) != 0 )
2256 goto done;
2258 else
2260 if ( (rc = ops->read(ea.mem.seg, truncate_ea(_regs.esi),
2261 &dst.val, dst.bytes, ctxt)) != 0 )
2262 goto done;
2263 fail_if(ops->write_io == NULL);
2264 if ( (rc = ops->write_io((uint16_t)_regs.edx, dst.bytes,
2265 dst.val, ctxt)) != 0 )
2266 goto done;
2267 nr_reps = 1;
2269 register_address_increment(
2270 _regs.esi,
2271 nr_reps * ((_regs.eflags & EFLG_DF) ? -dst.bytes : dst.bytes));
2272 put_rep_prefix(nr_reps);
2273 break;
2276 case 0x70 ... 0x7f: /* jcc (short) */ {
2277 int rel = insn_fetch_type(int8_t);
2278 if ( test_cc(b, _regs.eflags) )
2279 jmp_rel(rel);
2280 break;
2283 case 0x90: /* nop / xchg %%r8,%%rax */
2284 if ( !(rex_prefix & 1) )
2285 break; /* nop */
2287 case 0x91 ... 0x97: /* xchg reg,%%rax */
2288 src.type = dst.type = OP_REG;
2289 src.bytes = dst.bytes = op_bytes;
2290 src.reg = (unsigned long *)&_regs.eax;
2291 src.val = *src.reg;
2292 dst.reg = decode_register(
2293 (b & 7) | ((rex_prefix & 1) << 3), &_regs, 0);
2294 dst.val = *dst.reg;
2295 goto xchg;
2297 case 0x98: /* cbw/cwde/cdqe */
2298 switch ( op_bytes )
2300 case 2: *(int16_t *)&_regs.eax = (int8_t)_regs.eax; break; /* cbw */
2301 case 4: _regs.eax = (uint32_t)(int16_t)_regs.eax; break; /* cwde */
2302 case 8: _regs.eax = (int32_t)_regs.eax; break; /* cdqe */
2304 break;
2306 case 0x99: /* cwd/cdq/cqo */
2307 switch ( op_bytes )
2309 case 2:
2310 *(int16_t *)&_regs.edx = ((int16_t)_regs.eax < 0) ? -1 : 0;
2311 break;
2312 case 4:
2313 _regs.edx = (uint32_t)(((int32_t)_regs.eax < 0) ? -1 : 0);
2314 break;
2315 case 8:
2316 _regs.edx = (_regs.eax < 0) ? -1 : 0;
2317 break;
2319 break;
2321 case 0x9a: /* call (far, absolute) */ {
2322 struct segment_register reg;
2323 uint16_t sel;
2324 uint32_t eip;
2326 fail_if(ops->read_segment == NULL);
2327 generate_exception_if(mode_64bit(), EXC_UD);
2329 eip = insn_fetch_bytes(op_bytes);
2330 sel = insn_fetch_type(uint16_t);
2332 if ( (rc = ops->read_segment(x86_seg_cs, &reg, ctxt)) ||
2333 (rc = ops->write(x86_seg_ss, sp_pre_dec(op_bytes),
2334 reg.sel, op_bytes, ctxt)) ||
2335 (rc = ops->write(x86_seg_ss, sp_pre_dec(op_bytes),
2336 _regs.eip, op_bytes, ctxt)) )
2337 goto done;
2339 if ( (rc = load_seg(x86_seg_cs, sel, ctxt, ops)) != 0 )
2340 goto done;
2341 _regs.eip = eip;
2342 break;
2345 case 0x9c: /* pushf */
2346 src.val = _regs.eflags;
2347 goto push;
2349 case 0x9d: /* popf */ {
2350 uint32_t mask = EFLG_VIP | EFLG_VIF | EFLG_VM;
2351 if ( !mode_iopl() )
2352 mask |= EFLG_IOPL;
2353 fail_if(ops->write_rflags == NULL);
2354 /* 64-bit mode: POP defaults to a 64-bit operand. */
2355 if ( mode_64bit() && (op_bytes == 4) )
2356 op_bytes = 8;
2357 if ( (rc = ops->read(x86_seg_ss, sp_post_inc(op_bytes),
2358 &dst.val, op_bytes, ctxt)) != 0 )
2359 goto done;
2360 if ( op_bytes == 2 )
2361 dst.val = (uint16_t)dst.val | (_regs.eflags & 0xffff0000u);
2362 dst.val &= 0x257fd5;
2363 _regs.eflags &= mask;
2364 _regs.eflags |= (uint32_t)(dst.val & ~mask) | 0x02;
2365 if ( (rc = ops->write_rflags(_regs.eflags, ctxt)) != 0 )
2366 goto done;
2367 break;
2370 case 0x9e: /* sahf */
2371 *(uint8_t *)&_regs.eflags = (((uint8_t *)&_regs.eax)[1] & 0xd7) | 0x02;
2372 break;
2374 case 0x9f: /* lahf */
2375 ((uint8_t *)&_regs.eax)[1] = (_regs.eflags & 0xd7) | 0x02;
2376 break;
2378 case 0xa0 ... 0xa1: /* mov mem.offs,{%al,%ax,%eax,%rax} */
2379 /* Source EA is not encoded via ModRM. */
2380 dst.type = OP_REG;
2381 dst.reg = (unsigned long *)&_regs.eax;
2382 dst.bytes = (d & ByteOp) ? 1 : op_bytes;
2383 if ( (rc = ops->read(ea.mem.seg, insn_fetch_bytes(ad_bytes),
2384 &dst.val, dst.bytes, ctxt)) != 0 )
2385 goto done;
2386 break;
2388 case 0xa2 ... 0xa3: /* mov {%al,%ax,%eax,%rax},mem.offs */
2389 /* Destination EA is not encoded via ModRM. */
2390 dst.type = OP_MEM;
2391 dst.mem.seg = ea.mem.seg;
2392 dst.mem.off = insn_fetch_bytes(ad_bytes);
2393 dst.bytes = (d & ByteOp) ? 1 : op_bytes;
2394 dst.val = (unsigned long)_regs.eax;
2395 break;
2397 case 0xa4 ... 0xa5: /* movs */ {
2398 unsigned long nr_reps = get_rep_prefix();
2399 dst.bytes = (d & ByteOp) ? 1 : op_bytes;
2400 dst.mem.seg = x86_seg_es;
2401 dst.mem.off = truncate_ea(_regs.edi);
2402 if ( (nr_reps > 1) && (ops->rep_movs != NULL) )
2404 if ( (rc = ops->rep_movs(ea.mem.seg, truncate_ea(_regs.esi),
2405 dst.mem.seg, dst.mem.off, dst.bytes,
2406 &nr_reps, ctxt)) != 0 )
2407 goto done;
2409 else
2411 if ( (rc = ops->read(ea.mem.seg, truncate_ea(_regs.esi),
2412 &dst.val, dst.bytes, ctxt)) != 0 )
2413 goto done;
2414 dst.type = OP_MEM;
2415 nr_reps = 1;
2417 register_address_increment(
2418 _regs.esi,
2419 nr_reps * ((_regs.eflags & EFLG_DF) ? -dst.bytes : dst.bytes));
2420 register_address_increment(
2421 _regs.edi,
2422 nr_reps * ((_regs.eflags & EFLG_DF) ? -dst.bytes : dst.bytes));
2423 put_rep_prefix(nr_reps);
2424 break;
2427 case 0xa6 ... 0xa7: /* cmps */ {
2428 unsigned long next_eip = _regs.eip;
2429 get_rep_prefix();
2430 src.bytes = dst.bytes = (d & ByteOp) ? 1 : op_bytes;
2431 if ( (rc = ops->read(ea.mem.seg, truncate_ea(_regs.esi),
2432 &dst.val, dst.bytes, ctxt)) ||
2433 (rc = ops->read(x86_seg_es, truncate_ea(_regs.edi),
2434 &src.val, src.bytes, ctxt)) )
2435 goto done;
2436 register_address_increment(
2437 _regs.esi, (_regs.eflags & EFLG_DF) ? -dst.bytes : dst.bytes);
2438 register_address_increment(
2439 _regs.edi, (_regs.eflags & EFLG_DF) ? -src.bytes : src.bytes);
2440 put_rep_prefix(1);
2441 /* cmp: dst - src ==> src=*%%edi,dst=*%%esi ==> *%%esi - *%%edi */
2442 emulate_2op_SrcV("cmp", src, dst, _regs.eflags);
2443 if ( ((rep_prefix == REPE_PREFIX) && !(_regs.eflags & EFLG_ZF)) ||
2444 ((rep_prefix == REPNE_PREFIX) && (_regs.eflags & EFLG_ZF)) )
2445 _regs.eip = next_eip;
2446 break;
2449 case 0xaa ... 0xab: /* stos */ {
2450 /* unsigned long max_reps = */get_rep_prefix();
2451 dst.type = OP_MEM;
2452 dst.bytes = (d & ByteOp) ? 1 : op_bytes;
2453 dst.mem.seg = x86_seg_es;
2454 dst.mem.off = truncate_ea(_regs.edi);
2455 dst.val = _regs.eax;
2456 register_address_increment(
2457 _regs.edi, (_regs.eflags & EFLG_DF) ? -dst.bytes : dst.bytes);
2458 put_rep_prefix(1);
2459 break;
2462 case 0xac ... 0xad: /* lods */ {
2463 /* unsigned long max_reps = */get_rep_prefix();
2464 dst.type = OP_REG;
2465 dst.bytes = (d & ByteOp) ? 1 : op_bytes;
2466 dst.reg = (unsigned long *)&_regs.eax;
2467 if ( (rc = ops->read(ea.mem.seg, truncate_ea(_regs.esi),
2468 &dst.val, dst.bytes, ctxt)) != 0 )
2469 goto done;
2470 register_address_increment(
2471 _regs.esi, (_regs.eflags & EFLG_DF) ? -dst.bytes : dst.bytes);
2472 put_rep_prefix(1);
2473 break;
2476 case 0xae ... 0xaf: /* scas */ {
2477 unsigned long next_eip = _regs.eip;
2478 get_rep_prefix();
2479 src.bytes = dst.bytes = (d & ByteOp) ? 1 : op_bytes;
2480 dst.val = _regs.eax;
2481 if ( (rc = ops->read(x86_seg_es, truncate_ea(_regs.edi),
2482 &src.val, src.bytes, ctxt)) != 0 )
2483 goto done;
2484 register_address_increment(
2485 _regs.edi, (_regs.eflags & EFLG_DF) ? -src.bytes : src.bytes);
2486 put_rep_prefix(1);
2487 /* cmp: dst - src ==> src=*%%edi,dst=%%eax ==> %%eax - *%%edi */
2488 emulate_2op_SrcV("cmp", src, dst, _regs.eflags);
2489 if ( ((rep_prefix == REPE_PREFIX) && !(_regs.eflags & EFLG_ZF)) ||
2490 ((rep_prefix == REPNE_PREFIX) && (_regs.eflags & EFLG_ZF)) )
2491 _regs.eip = next_eip;
2492 break;
2495 case 0xc2: /* ret imm16 (near) */
2496 case 0xc3: /* ret (near) */ {
2497 int offset = (b == 0xc2) ? insn_fetch_type(uint16_t) : 0;
2498 op_bytes = mode_64bit() ? 8 : op_bytes;
2499 if ( (rc = ops->read(x86_seg_ss, sp_post_inc(op_bytes + offset),
2500 &dst.val, op_bytes, ctxt)) != 0 )
2501 goto done;
2502 _regs.eip = dst.val;
2503 break;
2506 case 0xc8: /* enter imm16,imm8 */ {
2507 uint16_t size = insn_fetch_type(uint16_t);
2508 uint8_t depth = insn_fetch_type(uint8_t) & 31;
2509 int i;
2511 dst.type = OP_REG;
2512 dst.bytes = (mode_64bit() && (op_bytes == 4)) ? 8 : op_bytes;
2513 dst.reg = (unsigned long *)&_regs.ebp;
2514 if ( (rc = ops->write(x86_seg_ss, sp_pre_dec(dst.bytes),
2515 _regs.ebp, dst.bytes, ctxt)) )
2516 goto done;
2517 dst.val = _regs.esp;
2519 if ( depth > 0 )
2521 for ( i = 1; i < depth; i++ )
2523 unsigned long ebp, temp_data;
2524 ebp = truncate_word(_regs.ebp - i*dst.bytes, ctxt->sp_size/8);
2525 if ( (rc = ops->read(x86_seg_ss, ebp,
2526 &temp_data, dst.bytes, ctxt)) ||
2527 (rc = ops->write(x86_seg_ss, sp_pre_dec(dst.bytes),
2528 temp_data, dst.bytes, ctxt)) )
2529 goto done;
2531 if ( (rc = ops->write(x86_seg_ss, sp_pre_dec(dst.bytes),
2532 dst.val, dst.bytes, ctxt)) )
2533 goto done;
2536 sp_pre_dec(size);
2537 break;
2540 case 0xc9: /* leave */
2541 /* First writeback, to %%esp. */
2542 dst.type = OP_REG;
2543 dst.bytes = (mode_64bit() && (op_bytes == 4)) ? 8 : op_bytes;
2544 dst.reg = (unsigned long *)&_regs.esp;
2545 dst.val = _regs.ebp;
2547 /* Flush first writeback, since there is a second. */
2548 switch ( dst.bytes )
2550 case 1: *(uint8_t *)dst.reg = (uint8_t)dst.val; break;
2551 case 2: *(uint16_t *)dst.reg = (uint16_t)dst.val; break;
2552 case 4: *dst.reg = (uint32_t)dst.val; break; /* 64b: zero-ext */
2553 case 8: *dst.reg = dst.val; break;
2556 /* Second writeback, to %%ebp. */
2557 dst.reg = (unsigned long *)&_regs.ebp;
2558 if ( (rc = ops->read(x86_seg_ss, sp_post_inc(dst.bytes),
2559 &dst.val, dst.bytes, ctxt)) )
2560 goto done;
2561 break;
2563 case 0xca: /* ret imm16 (far) */
2564 case 0xcb: /* ret (far) */ {
2565 int offset = (b == 0xca) ? insn_fetch_type(uint16_t) : 0;
2566 op_bytes = mode_64bit() ? 8 : op_bytes;
2567 if ( (rc = ops->read(x86_seg_ss, sp_post_inc(op_bytes),
2568 &dst.val, op_bytes, ctxt)) ||
2569 (rc = ops->read(x86_seg_ss, sp_post_inc(op_bytes + offset),
2570 &src.val, op_bytes, ctxt)) ||
2571 (rc = load_seg(x86_seg_cs, (uint16_t)src.val, ctxt, ops)) )
2572 goto done;
2573 _regs.eip = dst.val;
2574 break;
2577 case 0xcc: /* int3 */
2578 src.val = EXC_BP;
2579 goto swint;
2581 case 0xcd: /* int imm8 */
2582 src.val = insn_fetch_type(uint8_t);
2583 swint:
2584 fail_if(ops->inject_sw_interrupt == NULL);
2585 rc = ops->inject_sw_interrupt(src.val, _regs.eip - ctxt->regs->eip,
2586 ctxt) ? : X86EMUL_EXCEPTION;
2587 goto done;
2589 case 0xce: /* into */
2590 generate_exception_if(mode_64bit(), EXC_UD);
2591 if ( !(_regs.eflags & EFLG_OF) )
2592 break;
2593 src.val = EXC_OF;
2594 goto swint;
2596 case 0xcf: /* iret */ {
2597 unsigned long cs, eip, eflags;
2598 uint32_t mask = EFLG_VIP | EFLG_VIF | EFLG_VM;
2599 if ( !mode_iopl() )
2600 mask |= EFLG_IOPL;
2601 fail_if(!in_realmode(ctxt, ops));
2602 fail_if(ops->write_rflags == NULL);
2603 if ( (rc = ops->read(x86_seg_ss, sp_post_inc(op_bytes),
2604 &eip, op_bytes, ctxt)) ||
2605 (rc = ops->read(x86_seg_ss, sp_post_inc(op_bytes),
2606 &cs, op_bytes, ctxt)) ||
2607 (rc = ops->read(x86_seg_ss, sp_post_inc(op_bytes),
2608 &eflags, op_bytes, ctxt)) )
2609 goto done;
2610 if ( op_bytes == 2 )
2611 eflags = (uint16_t)eflags | (_regs.eflags & 0xffff0000u);
2612 eflags &= 0x257fd5;
2613 _regs.eflags &= mask;
2614 _regs.eflags |= (uint32_t)(eflags & ~mask) | 0x02;
2615 if ( (rc = ops->write_rflags(_regs.eflags, ctxt)) != 0 )
2616 goto done;
2617 _regs.eip = eip;
2618 if ( (rc = load_seg(x86_seg_cs, (uint16_t)cs, ctxt, ops)) != 0 )
2619 goto done;
2620 break;
2623 case 0xd4: /* aam */ {
2624 unsigned int base = insn_fetch_type(uint8_t);
2625 uint8_t al = _regs.eax;
2626 generate_exception_if(mode_64bit(), EXC_UD);
2627 generate_exception_if(base == 0, EXC_DE);
2628 *(uint16_t *)&_regs.eax = ((al / base) << 8) | (al % base);
2629 _regs.eflags &= ~(EFLG_SF|EFLG_ZF|EFLG_PF);
2630 _regs.eflags |= ((uint8_t)_regs.eax == 0) ? EFLG_ZF : 0;
2631 _regs.eflags |= (( int8_t)_regs.eax < 0) ? EFLG_SF : 0;
2632 _regs.eflags |= even_parity(_regs.eax) ? EFLG_PF : 0;
2633 break;
2636 case 0xd5: /* aad */ {
2637 unsigned int base = insn_fetch_type(uint8_t);
2638 uint16_t ax = _regs.eax;
2639 generate_exception_if(mode_64bit(), EXC_UD);
2640 *(uint16_t *)&_regs.eax = (uint8_t)(ax + ((ax >> 8) * base));
2641 _regs.eflags &= ~(EFLG_SF|EFLG_ZF|EFLG_PF);
2642 _regs.eflags |= ((uint8_t)_regs.eax == 0) ? EFLG_ZF : 0;
2643 _regs.eflags |= (( int8_t)_regs.eax < 0) ? EFLG_SF : 0;
2644 _regs.eflags |= even_parity(_regs.eax) ? EFLG_PF : 0;
2645 break;
2648 case 0xd6: /* salc */
2649 generate_exception_if(mode_64bit(), EXC_UD);
2650 *(uint8_t *)&_regs.eax = (_regs.eflags & EFLG_CF) ? 0xff : 0x00;
2651 break;
2653 case 0xd7: /* xlat */ {
2654 unsigned long al = (uint8_t)_regs.eax;
2655 if ( (rc = ops->read(ea.mem.seg, truncate_ea(_regs.ebx + al),
2656 &al, 1, ctxt)) != 0 )
2657 goto done;
2658 *(uint8_t *)&_regs.eax = al;
2659 break;
2662 case 0xd9: /* FPU 0xd9 */
2663 fail_if(ops->load_fpu_ctxt == NULL);
2664 ops->load_fpu_ctxt(ctxt);
2665 fail_if((modrm_reg & 7) != 7);
2666 fail_if(modrm_reg >= 0xc0);
2667 /* fnstcw m2byte */
2668 ea.bytes = 2;
2669 dst = ea;
2670 asm volatile ( "fnstcw %0" : "=m" (dst.val) );
2671 break;
2673 case 0xdb: /* FPU 0xdb */
2674 fail_if(ops->load_fpu_ctxt == NULL);
2675 ops->load_fpu_ctxt(ctxt);
2676 fail_if(modrm != 0xe3);
2677 /* fninit */
2678 asm volatile ( "fninit" );
2679 break;
2681 case 0xdd: /* FPU 0xdd */
2682 fail_if(ops->load_fpu_ctxt == NULL);
2683 ops->load_fpu_ctxt(ctxt);
2684 fail_if((modrm_reg & 7) != 7);
2685 fail_if(modrm_reg >= 0xc0);
2686 /* fnstsw m2byte */
2687 ea.bytes = 2;
2688 dst = ea;
2689 asm volatile ( "fnstsw %0" : "=m" (dst.val) );
2690 break;
2692 case 0xe0 ... 0xe2: /* loop{,z,nz} */ {
2693 int rel = insn_fetch_type(int8_t);
2694 int do_jmp = !(_regs.eflags & EFLG_ZF); /* loopnz */
2695 if ( b == 0xe1 )
2696 do_jmp = !do_jmp; /* loopz */
2697 else if ( b == 0xe2 )
2698 do_jmp = 1; /* loop */
2699 switch ( ad_bytes )
2701 case 2:
2702 do_jmp &= --(*(uint16_t *)&_regs.ecx) != 0;
2703 break;
2704 case 4:
2705 do_jmp &= --(*(uint32_t *)&_regs.ecx) != 0;
2706 _regs.ecx = (uint32_t)_regs.ecx; /* zero extend in x86/64 mode */
2707 break;
2708 default: /* case 8: */
2709 do_jmp &= --_regs.ecx != 0;
2710 break;
2712 if ( do_jmp )
2713 jmp_rel(rel);
2714 break;
2717 case 0xe3: /* jcxz/jecxz (short) */ {
2718 int rel = insn_fetch_type(int8_t);
2719 if ( (ad_bytes == 2) ? !(uint16_t)_regs.ecx :
2720 (ad_bytes == 4) ? !(uint32_t)_regs.ecx : !_regs.ecx )
2721 jmp_rel(rel);
2722 break;
2725 case 0xe4: /* in imm8,%al */
2726 case 0xe5: /* in imm8,%eax */
2727 case 0xe6: /* out %al,imm8 */
2728 case 0xe7: /* out %eax,imm8 */
2729 case 0xec: /* in %dx,%al */
2730 case 0xed: /* in %dx,%eax */
2731 case 0xee: /* out %al,%dx */
2732 case 0xef: /* out %eax,%dx */ {
2733 unsigned int port = ((b < 0xe8)
2734 ? insn_fetch_type(uint8_t)
2735 : (uint16_t)_regs.edx);
2736 generate_exception_if(!mode_iopl(), EXC_GP);
2737 op_bytes = !(b & 1) ? 1 : (op_bytes == 8) ? 4 : op_bytes;
2738 if ( b & 2 )
2740 /* out */
2741 fail_if(ops->write_io == NULL);
2742 rc = ops->write_io(port, op_bytes, _regs.eax, ctxt);
2745 else
2747 /* in */
2748 dst.type = OP_REG;
2749 dst.bytes = op_bytes;
2750 dst.reg = (unsigned long *)&_regs.eax;
2751 fail_if(ops->read_io == NULL);
2752 rc = ops->read_io(port, dst.bytes, &dst.val, ctxt);
2754 if ( rc != 0 )
2755 goto done;
2756 break;
2759 case 0xe8: /* call (near) */ {
2760 int rel = (((op_bytes == 2) && !mode_64bit())
2761 ? (int32_t)insn_fetch_type(int16_t)
2762 : insn_fetch_type(int32_t));
2763 op_bytes = mode_64bit() ? 8 : op_bytes;
2764 src.val = _regs.eip;
2765 jmp_rel(rel);
2766 goto push;
2769 case 0xe9: /* jmp (near) */ {
2770 int rel = (((op_bytes == 2) && !mode_64bit())
2771 ? (int32_t)insn_fetch_type(int16_t)
2772 : insn_fetch_type(int32_t));
2773 jmp_rel(rel);
2774 break;
2777 case 0xea: /* jmp (far, absolute) */ {
2778 uint16_t sel;
2779 uint32_t eip;
2780 generate_exception_if(mode_64bit(), EXC_UD);
2781 eip = insn_fetch_bytes(op_bytes);
2782 sel = insn_fetch_type(uint16_t);
2783 if ( (rc = load_seg(x86_seg_cs, sel, ctxt, ops)) != 0 )
2784 goto done;
2785 _regs.eip = eip;
2786 break;
2789 case 0xeb: /* jmp (short) */ {
2790 int rel = insn_fetch_type(int8_t);
2791 jmp_rel(rel);
2792 break;
2795 case 0xf1: /* int1 (icebp) */
2796 src.val = EXC_DB;
2797 goto swint;
2799 case 0xf4: /* hlt */
2800 fail_if(ops->hlt == NULL);
2801 if ( (rc = ops->hlt(ctxt)) != 0 )
2802 goto done;
2803 break;
2805 case 0xf5: /* cmc */
2806 _regs.eflags ^= EFLG_CF;
2807 break;
2809 case 0xf8: /* clc */
2810 _regs.eflags &= ~EFLG_CF;
2811 break;
2813 case 0xf9: /* stc */
2814 _regs.eflags |= EFLG_CF;
2815 break;
2817 case 0xfa: /* cli */
2818 case 0xfb: /* sti */
2819 generate_exception_if(!mode_iopl(), EXC_GP);
2820 fail_if(ops->write_rflags == NULL);
2821 _regs.eflags &= ~EFLG_IF;
2822 if ( b == 0xfb ) /* sti */
2823 _regs.eflags |= EFLG_IF;
2824 if ( (rc = ops->write_rflags(_regs.eflags, ctxt)) != 0 )
2825 goto done;
2826 break;
2828 case 0xfc: /* cld */
2829 _regs.eflags &= ~EFLG_DF;
2830 break;
2832 case 0xfd: /* std */
2833 _regs.eflags |= EFLG_DF;
2834 break;
2836 goto writeback;
2838 twobyte_insn:
2839 switch ( b )
2841 case 0x40 ... 0x4f: /* cmovcc */
2842 dst.val = src.val;
2843 if ( !test_cc(b, _regs.eflags) )
2844 dst.type = OP_NONE;
2845 break;
2847 case 0x90 ... 0x9f: /* setcc */
2848 dst.val = test_cc(b, _regs.eflags);
2849 break;
2851 case 0xb0 ... 0xb1: /* cmpxchg */
2852 /* Save real source value, then compare EAX against destination. */
2853 src.orig_val = src.val;
2854 src.val = _regs.eax;
2855 emulate_2op_SrcV("cmp", src, dst, _regs.eflags);
2856 /* Always write back. The question is: where to? */
2857 d |= Mov;
2858 if ( _regs.eflags & EFLG_ZF )
2860 /* Success: write back to memory. */
2861 dst.val = src.orig_val;
2863 else
2865 /* Failure: write the value we saw to EAX. */
2866 dst.type = OP_REG;
2867 dst.reg = (unsigned long *)&_regs.eax;
2869 break;
2871 case 0xa3: bt: /* bt */
2872 emulate_2op_SrcV_nobyte("bt", src, dst, _regs.eflags);
2873 break;
2875 case 0xa4: /* shld imm8,r,r/m */
2876 case 0xa5: /* shld %%cl,r,r/m */
2877 case 0xac: /* shrd imm8,r,r/m */
2878 case 0xad: /* shrd %%cl,r,r/m */ {
2879 uint8_t shift, width = dst.bytes << 3;
2880 shift = (b & 1) ? (uint8_t)_regs.ecx : insn_fetch_type(uint8_t);
2881 if ( (shift &= width - 1) == 0 )
2882 break;
2883 dst.orig_val = truncate_word(dst.val, dst.bytes);
2884 dst.val = ((shift == width) ? src.val :
2885 (b & 8) ?
2886 /* shrd */
2887 ((dst.orig_val >> shift) |
2888 truncate_word(src.val << (width - shift), dst.bytes)) :
2889 /* shld */
2890 ((dst.orig_val << shift) |
2891 ((src.val >> (width - shift)) & ((1ull << shift) - 1))));
2892 dst.val = truncate_word(dst.val, dst.bytes);
2893 _regs.eflags &= ~(EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_PF|EFLG_CF);
2894 if ( (dst.val >> ((b & 8) ? (shift - 1) : (width - shift))) & 1 )
2895 _regs.eflags |= EFLG_CF;
2896 if ( ((dst.val ^ dst.orig_val) >> (width - 1)) & 1 )
2897 _regs.eflags |= EFLG_OF;
2898 _regs.eflags |= ((dst.val >> (width - 1)) & 1) ? EFLG_SF : 0;
2899 _regs.eflags |= (dst.val == 0) ? EFLG_ZF : 0;
2900 _regs.eflags |= even_parity(dst.val) ? EFLG_PF : 0;
2901 break;
2904 case 0xb3: btr: /* btr */
2905 emulate_2op_SrcV_nobyte("btr", src, dst, _regs.eflags);
2906 break;
2908 case 0xab: bts: /* bts */
2909 emulate_2op_SrcV_nobyte("bts", src, dst, _regs.eflags);
2910 break;
2912 case 0xaf: /* imul */
2913 _regs.eflags &= ~(EFLG_OF|EFLG_CF);
2914 switch ( dst.bytes )
2916 case 2:
2917 dst.val = ((uint32_t)(int16_t)src.val *
2918 (uint32_t)(int16_t)dst.val);
2919 if ( (int16_t)dst.val != (uint32_t)dst.val )
2920 _regs.eflags |= EFLG_OF|EFLG_CF;
2921 break;
2922 #ifdef __x86_64__
2923 case 4:
2924 dst.val = ((uint64_t)(int32_t)src.val *
2925 (uint64_t)(int32_t)dst.val);
2926 if ( (int32_t)dst.val != dst.val )
2927 _regs.eflags |= EFLG_OF|EFLG_CF;
2928 break;
2929 #endif
2930 default: {
2931 unsigned long m[2] = { src.val, dst.val };
2932 if ( imul_dbl(m) )
2933 _regs.eflags |= EFLG_OF|EFLG_CF;
2934 dst.val = m[0];
2935 break;
2938 break;
2940 case 0xb2: /* lss */
2941 dst.val = x86_seg_ss;
2942 goto les;
2944 case 0xb4: /* lfs */
2945 dst.val = x86_seg_fs;
2946 goto les;
2948 case 0xb5: /* lgs */
2949 dst.val = x86_seg_gs;
2950 goto les;
2952 case 0xb6: /* movzx rm8,r{16,32,64} */
2953 /* Recompute DstReg as we may have decoded AH/BH/CH/DH. */
2954 dst.reg = decode_register(modrm_reg, &_regs, 0);
2955 dst.bytes = op_bytes;
2956 dst.val = (uint8_t)src.val;
2957 break;
2959 case 0xbc: /* bsf */ {
2960 int zf;
2961 asm ( "bsf %2,%0; setz %b1"
2962 : "=r" (dst.val), "=q" (zf)
2963 : "r" (src.val), "1" (0) );
2964 _regs.eflags &= ~EFLG_ZF;
2965 _regs.eflags |= zf ? EFLG_ZF : 0;
2966 break;
2969 case 0xbd: /* bsr */ {
2970 int zf;
2971 asm ( "bsr %2,%0; setz %b1"
2972 : "=r" (dst.val), "=q" (zf)
2973 : "r" (src.val), "1" (0) );
2974 _regs.eflags &= ~EFLG_ZF;
2975 _regs.eflags |= zf ? EFLG_ZF : 0;
2976 break;
2979 case 0xb7: /* movzx rm16,r{16,32,64} */
2980 dst.val = (uint16_t)src.val;
2981 break;
2983 case 0xbb: btc: /* btc */
2984 emulate_2op_SrcV_nobyte("btc", src, dst, _regs.eflags);
2985 break;
2987 case 0xba: /* Grp8 */
2988 switch ( modrm_reg & 7 )
2990 case 4: goto bt;
2991 case 5: goto bts;
2992 case 6: goto btr;
2993 case 7: goto btc;
2994 default: generate_exception_if(1, EXC_UD);
2996 break;
2998 case 0xbe: /* movsx rm8,r{16,32,64} */
2999 /* Recompute DstReg as we may have decoded AH/BH/CH/DH. */
3000 dst.reg = decode_register(modrm_reg, &_regs, 0);
3001 dst.bytes = op_bytes;
3002 dst.val = (int8_t)src.val;
3003 break;
3005 case 0xbf: /* movsx rm16,r{16,32,64} */
3006 dst.val = (int16_t)src.val;
3007 break;
3009 case 0xc0 ... 0xc1: /* xadd */
3010 /* Write back the register source. */
3011 switch ( dst.bytes )
3013 case 1: *(uint8_t *)src.reg = (uint8_t)dst.val; break;
3014 case 2: *(uint16_t *)src.reg = (uint16_t)dst.val; break;
3015 case 4: *src.reg = (uint32_t)dst.val; break; /* 64b reg: zero-extend */
3016 case 8: *src.reg = dst.val; break;
3018 goto add;
3020 goto writeback;
3022 twobyte_special_insn:
3023 switch ( b )
3025 case 0x01: /* Grp7 */ {
3026 struct segment_register reg;
3027 unsigned long base, limit, cr0, cr0w;
3029 switch ( modrm_reg & 7 )
3031 case 0: /* sgdt */
3032 case 1: /* sidt */
3033 generate_exception_if(ea.type != OP_MEM, EXC_UD);
3034 fail_if(ops->read_segment == NULL);
3035 if ( (rc = ops->read_segment((modrm_reg & 1) ?
3036 x86_seg_idtr : x86_seg_gdtr,
3037 &reg, ctxt)) )
3038 goto done;
3039 if ( op_bytes == 2 )
3040 reg.base &= 0xffffff;
3041 if ( (rc = ops->write(ea.mem.seg, ea.mem.off+0,
3042 reg.limit, 2, ctxt)) ||
3043 (rc = ops->write(ea.mem.seg, ea.mem.off+2,
3044 reg.base, mode_64bit() ? 8 : 4, ctxt)) )
3045 goto done;
3046 break;
3047 case 2: /* lgdt */
3048 case 3: /* lidt */
3049 generate_exception_if(ea.type != OP_MEM, EXC_UD);
3050 fail_if(ops->write_segment == NULL);
3051 memset(&reg, 0, sizeof(reg));
3052 if ( (rc = ops->read(ea.mem.seg, ea.mem.off+0,
3053 &limit, 2, ctxt)) ||
3054 (rc = ops->read(ea.mem.seg, ea.mem.off+2,
3055 &base, mode_64bit() ? 8 : 4, ctxt)) )
3056 goto done;
3057 reg.base = base;
3058 reg.limit = limit;
3059 if ( op_bytes == 2 )
3060 reg.base &= 0xffffff;
3061 if ( (rc = ops->write_segment((modrm_reg & 1) ?
3062 x86_seg_idtr : x86_seg_gdtr,
3063 &reg, ctxt)) )
3064 goto done;
3065 break;
3066 case 4: /* smsw */
3067 ea.bytes = 2;
3068 dst = ea;
3069 fail_if(ops->read_cr == NULL);
3070 if ( (rc = ops->read_cr(0, &dst.val, ctxt)) )
3071 goto done;
3072 d |= Mov; /* force writeback */
3073 break;
3074 case 6: /* lmsw */
3075 fail_if(ops->read_cr == NULL);
3076 fail_if(ops->write_cr == NULL);
3077 if ( (rc = ops->read_cr(0, &cr0, ctxt)) )
3078 goto done;
3079 if ( ea.type == OP_REG )
3080 cr0w = *ea.reg;
3081 else if ( (rc = ops->read(ea.mem.seg, ea.mem.off,
3082 &cr0w, 2, ctxt)) )
3083 goto done;
3084 cr0 &= 0xffff0000;
3085 cr0 |= (uint16_t)cr0w;
3086 if ( (rc = ops->write_cr(0, cr0, ctxt)) )
3087 goto done;
3088 break;
3089 default:
3090 goto cannot_emulate;
3092 break;
3095 case 0x06: /* clts */
3096 generate_exception_if(!mode_ring0(), EXC_GP);
3097 fail_if((ops->read_cr == NULL) || (ops->write_cr == NULL));
3098 if ( (rc = ops->read_cr(0, &dst.val, ctxt)) ||
3099 (rc = ops->write_cr(0, dst.val&~8, ctxt)) )
3100 goto done;
3101 break;
3103 case 0x08: /* invd */
3104 case 0x09: /* wbinvd */
3105 generate_exception_if(!mode_ring0(), EXC_GP);
3106 fail_if(ops->wbinvd == NULL);
3107 if ( (rc = ops->wbinvd(ctxt)) != 0 )
3108 goto done;
3109 break;
3111 case 0x0d: /* GrpP (prefetch) */
3112 case 0x18: /* Grp16 (prefetch/nop) */
3113 case 0x19 ... 0x1f: /* nop (amd-defined) */
3114 break;
3116 case 0x20: /* mov cr,reg */
3117 case 0x21: /* mov dr,reg */
3118 case 0x22: /* mov reg,cr */
3119 case 0x23: /* mov reg,dr */
3120 generate_exception_if(!mode_ring0(), EXC_GP);
3121 modrm_rm |= (rex_prefix & 1) << 3;
3122 modrm_reg |= lock_prefix << 3;
3123 if ( b & 2 )
3125 /* Write to CR/DR. */
3126 src.val = *(unsigned long *)decode_register(modrm_rm, &_regs, 0);
3127 if ( !mode_64bit() )
3128 src.val = (uint32_t)src.val;
3129 rc = ((b & 1)
3130 ? (ops->write_dr
3131 ? ops->write_dr(modrm_reg, src.val, ctxt)
3132 : X86EMUL_UNHANDLEABLE)
3133 : (ops->write_cr
3134 ? ops->write_cr(modrm_reg, src.val, ctxt)
3135 : X86EMUL_UNHANDLEABLE));
3137 else
3139 /* Read from CR/DR. */
3140 dst.type = OP_REG;
3141 dst.bytes = mode_64bit() ? 8 : 4;
3142 dst.reg = decode_register(modrm_rm, &_regs, 0);
3143 rc = ((b & 1)
3144 ? (ops->read_dr
3145 ? ops->read_dr(modrm_reg, &dst.val, ctxt)
3146 : X86EMUL_UNHANDLEABLE)
3147 : (ops->read_cr
3148 ? ops->read_cr(modrm_reg, &dst.val, ctxt)
3149 : X86EMUL_UNHANDLEABLE));
3151 if ( rc != 0 )
3152 goto done;
3153 break;
3155 case 0x30: /* wrmsr */ {
3156 uint64_t val = ((uint64_t)_regs.edx << 32) | (uint32_t)_regs.eax;
3157 generate_exception_if(!mode_ring0(), EXC_GP);
3158 fail_if(ops->write_msr == NULL);
3159 if ( (rc = ops->write_msr((uint32_t)_regs.ecx, val, ctxt)) != 0 )
3160 goto done;
3161 break;
3164 case 0x31: /* rdtsc */ {
3165 unsigned long cr4;
3166 uint64_t val;
3167 fail_if(ops->read_cr == NULL);
3168 if ( (rc = ops->read_cr(4, &cr4, ctxt)) )
3169 goto done;
3170 generate_exception_if((cr4 & CR4_TSD) && !mode_ring0(), EXC_GP);
3171 fail_if(ops->read_msr == NULL);
3172 if ( (rc = ops->read_msr(MSR_TSC, &val, ctxt)) != 0 )
3173 goto done;
3174 _regs.edx = (uint32_t)(val >> 32);
3175 _regs.eax = (uint32_t)(val >> 0);
3176 break;
3179 case 0x32: /* rdmsr */ {
3180 uint64_t val;
3181 generate_exception_if(!mode_ring0(), EXC_GP);
3182 fail_if(ops->read_msr == NULL);
3183 if ( (rc = ops->read_msr((uint32_t)_regs.ecx, &val, ctxt)) != 0 )
3184 goto done;
3185 _regs.edx = (uint32_t)(val >> 32);
3186 _regs.eax = (uint32_t)(val >> 0);
3187 break;
3190 case 0x80 ... 0x8f: /* jcc (near) */ {
3191 int rel = (((op_bytes == 2) && !mode_64bit())
3192 ? (int32_t)insn_fetch_type(int16_t)
3193 : insn_fetch_type(int32_t));
3194 if ( test_cc(b, _regs.eflags) )
3195 jmp_rel(rel);
3196 break;
3199 case 0xa0: /* push %%fs */
3200 src.val = x86_seg_fs;
3201 goto push_seg;
3203 case 0xa1: /* pop %%fs */
3204 src.val = x86_seg_fs;
3205 goto pop_seg;
3207 case 0xa2: /* cpuid */ {
3208 unsigned int eax = _regs.eax, ebx = _regs.ebx;
3209 unsigned int ecx = _regs.ecx, edx = _regs.edx;
3210 fail_if(ops->cpuid == NULL);
3211 if ( (rc = ops->cpuid(&eax, &ebx, &ecx, &edx, ctxt)) != 0 )
3212 goto done;
3213 _regs.eax = eax; _regs.ebx = ebx;
3214 _regs.ecx = ecx; _regs.edx = edx;
3215 break;
3218 case 0xa8: /* push %%gs */
3219 src.val = x86_seg_gs;
3220 goto push_seg;
3222 case 0xa9: /* pop %%gs */
3223 src.val = x86_seg_gs;
3224 goto pop_seg;
3226 case 0xc7: /* Grp9 (cmpxchg8b) */
3227 #if defined(__i386__)
3229 unsigned long old_lo, old_hi;
3230 generate_exception_if((modrm_reg & 7) != 1, EXC_UD);
3231 generate_exception_if(ea.type != OP_MEM, EXC_UD);
3232 if ( (rc = ops->read(ea.mem.seg, ea.mem.off+0, &old_lo, 4, ctxt)) ||
3233 (rc = ops->read(ea.mem.seg, ea.mem.off+4, &old_hi, 4, ctxt)) )
3234 goto done;
3235 if ( (old_lo != _regs.eax) || (old_hi != _regs.edx) )
3237 _regs.eax = old_lo;
3238 _regs.edx = old_hi;
3239 _regs.eflags &= ~EFLG_ZF;
3241 else if ( ops->cmpxchg8b == NULL )
3243 rc = X86EMUL_UNHANDLEABLE;
3244 goto done;
3246 else
3248 if ( (rc = ops->cmpxchg8b(ea.mem.seg, ea.mem.off, old_lo, old_hi,
3249 _regs.ebx, _regs.ecx, ctxt)) != 0 )
3250 goto done;
3251 _regs.eflags |= EFLG_ZF;
3253 break;
3255 #elif defined(__x86_64__)
3257 unsigned long old, new;
3258 generate_exception_if((modrm_reg & 7) != 1, EXC_UD);
3259 generate_exception_if(ea.type != OP_MEM, EXC_UD);
3260 if ( (rc = ops->read(ea.mem.seg, ea.mem.off, &old, 8, ctxt)) != 0 )
3261 goto done;
3262 if ( ((uint32_t)(old>>0) != (uint32_t)_regs.eax) ||
3263 ((uint32_t)(old>>32) != (uint32_t)_regs.edx) )
3265 _regs.eax = (uint32_t)(old>>0);
3266 _regs.edx = (uint32_t)(old>>32);
3267 _regs.eflags &= ~EFLG_ZF;
3269 else
3271 new = (_regs.ecx<<32)|(uint32_t)_regs.ebx;
3272 if ( (rc = ops->cmpxchg(ea.mem.seg, ea.mem.off, old,
3273 new, 8, ctxt)) != 0 )
3274 goto done;
3275 _regs.eflags |= EFLG_ZF;
3277 break;
3279 #endif
3281 case 0xc8 ... 0xcf: /* bswap */
3282 dst.type = OP_REG;
3283 dst.reg = decode_register(
3284 (b & 7) | ((rex_prefix & 1) << 3), &_regs, 0);
3285 switch ( dst.bytes = op_bytes )
3287 default: /* case 2: */
3288 /* Undefined behaviour. Writes zero on all tested CPUs. */
3289 dst.val = 0;
3290 break;
3291 case 4:
3292 #ifdef __x86_64__
3293 asm ( "bswap %k0" : "=r" (dst.val) : "0" (*dst.reg) );
3294 break;
3295 case 8:
3296 #endif
3297 asm ( "bswap %0" : "=r" (dst.val) : "0" (*dst.reg) );
3298 break;
3300 break;
3302 goto writeback;
3304 cannot_emulate:
3305 #if 0
3306 gdprintk(XENLOG_DEBUG, "Instr:");
3307 for ( ea.mem.off = ctxt->regs->eip; ea.mem.off < _regs.eip; ea.mem.off++ )
3309 unsigned long x;
3310 ops->insn_fetch(x86_seg_cs, ea.mem.off, &x, 1, ctxt);
3311 printk(" %02x", (uint8_t)x);
3313 printk("\n");
3314 #endif
3315 return X86EMUL_UNHANDLEABLE;