ia64/xen-unstable

view xen/arch/x86/io_apic.c @ 18814:bddd2d344c54

x86: secure ioapic_guest_write() against FREE_TO_ASSIGN irq values

Signed-off-by: Jan Beulich <jbeulich@novell.com>
author Keir Fraser <keir.fraser@citrix.com>
date Wed Nov 19 16:11:39 2008 +0000 (2008-11-19)
parents 26985a665ded
children 6468257e9e62
line source
1 /*
2 * Intel IO-APIC support for multi-Pentium hosts.
3 *
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
5 *
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
8 *
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
14 *
15 * Fixes
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
18 * and Rolf G. Tews
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
21 */
23 #include <xen/config.h>
24 #include <xen/lib.h>
25 #include <xen/init.h>
26 #include <xen/irq.h>
27 #include <xen/delay.h>
28 #include <xen/sched.h>
29 #include <xen/acpi.h>
30 #include <xen/pci.h>
31 #include <xen/pci_regs.h>
32 #include <xen/keyhandler.h>
33 #include <asm/io.h>
34 #include <asm/mc146818rtc.h>
35 #include <asm/smp.h>
36 #include <asm/desc.h>
37 #include <asm/msi.h>
38 #include <mach_apic.h>
39 #include <io_ports.h>
40 #include <public/physdev.h>
42 /* Different to Linux: our implementation can be simpler. */
43 #define make_8259A_irq(irq) (io_apic_irqs &= ~(1<<(irq)))
45 int (*ioapic_renumber_irq)(int ioapic, int irq);
46 atomic_t irq_mis_count;
48 /* Where if anywhere is the i8259 connect in external int mode */
49 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
51 static DEFINE_SPINLOCK(ioapic_lock);
52 static DEFINE_SPINLOCK(vector_lock);
54 int skip_ioapic_setup;
56 #ifndef sis_apic_bug
57 /*
58 * Is the SiS APIC rmw bug present?
59 * -1 = don't know, 0 = no, 1 = yes
60 */
61 int sis_apic_bug = -1;
62 #endif
64 /*
65 * # of IRQ routing registers
66 */
67 int nr_ioapic_registers[MAX_IO_APICS];
69 int disable_timer_pin_1 __initdata;
71 /*
72 * Rough estimation of how many shared IRQs there are, can
73 * be changed anytime.
74 */
75 #define MAX_PLUS_SHARED_IRQS NR_IRQS
76 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
78 /*
79 * This is performance-critical, we want to do it O(1)
80 *
81 * the indexing order of this array favors 1:1 mappings
82 * between pins and IRQs.
83 */
85 static struct irq_pin_list {
86 int apic, pin, next;
87 } irq_2_pin[PIN_MAP_SIZE];
88 static int irq_2_pin_free_entry = NR_IRQS;
90 int vector_irq[NR_VECTORS] __read_mostly = {
91 [0 ... NR_VECTORS - 1] = FREE_TO_ASSIGN};
93 /*
94 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
95 * shared ISA-space IRQs, so we have to support them. We are super
96 * fast in the common case, and fast for shared ISA-space IRQs.
97 */
98 static void add_pin_to_irq(unsigned int irq, int apic, int pin)
99 {
100 struct irq_pin_list *entry = irq_2_pin + irq;
102 while (entry->next) {
103 BUG_ON((entry->apic == apic) && (entry->pin == pin));
104 entry = irq_2_pin + entry->next;
105 }
107 BUG_ON((entry->apic == apic) && (entry->pin == pin));
109 if (entry->pin != -1) {
110 if (irq_2_pin_free_entry >= PIN_MAP_SIZE)
111 panic("io_apic.c: whoops");
112 entry->next = irq_2_pin_free_entry;
113 entry = irq_2_pin + entry->next;
114 irq_2_pin_free_entry = entry->next;
115 entry->next = 0;
116 }
117 entry->apic = apic;
118 entry->pin = pin;
119 }
121 static void remove_pin_at_irq(unsigned int irq, int apic, int pin)
122 {
123 struct irq_pin_list *entry, *prev;
125 for (entry = &irq_2_pin[irq]; ; entry = &irq_2_pin[entry->next]) {
126 if ((entry->apic == apic) && (entry->pin == pin))
127 break;
128 if (!entry->next)
129 BUG();
130 }
132 entry->pin = entry->apic = -1;
134 if (entry != &irq_2_pin[irq]) {
135 /* Removed entry is not at head of list. */
136 prev = &irq_2_pin[irq];
137 while (&irq_2_pin[prev->next] != entry)
138 prev = &irq_2_pin[prev->next];
139 prev->next = entry->next;
140 entry->next = irq_2_pin_free_entry;
141 irq_2_pin_free_entry = entry - irq_2_pin;
142 } else if (entry->next != 0) {
143 /* Removed entry is at head of multi-item list. */
144 prev = entry;
145 entry = &irq_2_pin[entry->next];
146 *prev = *entry;
147 entry->pin = entry->apic = -1;
148 entry->next = irq_2_pin_free_entry;
149 irq_2_pin_free_entry = entry - irq_2_pin;
150 }
151 }
153 /*
154 * Reroute an IRQ to a different pin.
155 */
156 static void __init replace_pin_at_irq(unsigned int irq,
157 int oldapic, int oldpin,
158 int newapic, int newpin)
159 {
160 struct irq_pin_list *entry = irq_2_pin + irq;
162 while (1) {
163 if (entry->apic == oldapic && entry->pin == oldpin) {
164 entry->apic = newapic;
165 entry->pin = newpin;
166 }
167 if (!entry->next)
168 break;
169 entry = irq_2_pin + entry->next;
170 }
171 }
173 static void __modify_IO_APIC_irq (unsigned int irq, unsigned long enable, unsigned long disable)
174 {
175 struct irq_pin_list *entry = irq_2_pin + irq;
176 unsigned int pin, reg;
178 for (;;) {
179 pin = entry->pin;
180 if (pin == -1)
181 break;
182 reg = io_apic_read(entry->apic, 0x10 + pin*2);
183 reg &= ~disable;
184 reg |= enable;
185 io_apic_modify(entry->apic, 0x10 + pin*2, reg);
186 if (!entry->next)
187 break;
188 entry = irq_2_pin + entry->next;
189 }
190 }
192 /* mask = 1 */
193 static void __mask_IO_APIC_irq (unsigned int irq)
194 {
195 __modify_IO_APIC_irq(irq, 0x00010000, 0);
196 }
198 /* mask = 0 */
199 static void __unmask_IO_APIC_irq (unsigned int irq)
200 {
201 __modify_IO_APIC_irq(irq, 0, 0x00010000);
202 }
204 /* trigger = 0 */
205 static void __edge_IO_APIC_irq (unsigned int irq)
206 {
207 __modify_IO_APIC_irq(irq, 0, 0x00008000);
208 }
210 /* trigger = 1 */
211 static void __level_IO_APIC_irq (unsigned int irq)
212 {
213 __modify_IO_APIC_irq(irq, 0x00008000, 0);
214 }
216 static void mask_IO_APIC_irq (unsigned int irq)
217 {
218 unsigned long flags;
220 spin_lock_irqsave(&ioapic_lock, flags);
221 __mask_IO_APIC_irq(irq);
222 spin_unlock_irqrestore(&ioapic_lock, flags);
223 }
225 static void unmask_IO_APIC_irq (unsigned int irq)
226 {
227 unsigned long flags;
229 spin_lock_irqsave(&ioapic_lock, flags);
230 __unmask_IO_APIC_irq(irq);
231 spin_unlock_irqrestore(&ioapic_lock, flags);
232 }
234 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
235 {
236 struct IO_APIC_route_entry entry;
237 unsigned long flags;
239 /* Check delivery_mode to be sure we're not clearing an SMI pin */
240 spin_lock_irqsave(&ioapic_lock, flags);
241 *(((int*)&entry) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
242 *(((int*)&entry) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
243 spin_unlock_irqrestore(&ioapic_lock, flags);
244 if (entry.delivery_mode == dest_SMI)
245 return;
247 /*
248 * Disable it in the IO-APIC irq-routing table:
249 */
250 memset(&entry, 0, sizeof(entry));
251 entry.mask = 1;
252 spin_lock_irqsave(&ioapic_lock, flags);
253 io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry) + 0));
254 io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry) + 1));
255 spin_unlock_irqrestore(&ioapic_lock, flags);
256 }
258 static void clear_IO_APIC (void)
259 {
260 int apic, pin;
262 for (apic = 0; apic < nr_ioapics; apic++)
263 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
264 clear_IO_APIC_pin(apic, pin);
265 }
267 #ifdef CONFIG_SMP
268 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t cpumask)
269 {
270 unsigned long flags;
271 int pin;
272 struct irq_pin_list *entry = irq_2_pin + irq;
273 unsigned int apicid_value;
275 cpus_and(cpumask, cpumask, cpu_online_map);
276 if (cpus_empty(cpumask))
277 cpumask = TARGET_CPUS;
279 apicid_value = cpu_mask_to_apicid(cpumask);
280 /* Prepare to do the io_apic_write */
281 apicid_value = apicid_value << 24;
282 spin_lock_irqsave(&ioapic_lock, flags);
283 for (;;) {
284 pin = entry->pin;
285 if (pin == -1)
286 break;
287 io_apic_write(entry->apic, 0x10 + 1 + pin*2, apicid_value);
288 if (!entry->next)
289 break;
290 entry = irq_2_pin + entry->next;
291 }
292 set_irq_info(irq, cpumask);
293 spin_unlock_irqrestore(&ioapic_lock, flags);
294 }
295 #endif /* CONFIG_SMP */
297 /*
298 * Find the IRQ entry number of a certain pin.
299 */
300 static int find_irq_entry(int apic, int pin, int type)
301 {
302 int i;
304 for (i = 0; i < mp_irq_entries; i++)
305 if (mp_irqs[i].mpc_irqtype == type &&
306 (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
307 mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
308 mp_irqs[i].mpc_dstirq == pin)
309 return i;
311 return -1;
312 }
314 /*
315 * Find the pin to which IRQ[irq] (ISA) is connected
316 */
317 static int __init find_isa_irq_pin(int irq, int type)
318 {
319 int i;
321 for (i = 0; i < mp_irq_entries; i++) {
322 int lbus = mp_irqs[i].mpc_srcbus;
324 if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA ||
325 mp_bus_id_to_type[lbus] == MP_BUS_EISA ||
326 mp_bus_id_to_type[lbus] == MP_BUS_MCA ||
327 mp_bus_id_to_type[lbus] == MP_BUS_NEC98
328 ) &&
329 (mp_irqs[i].mpc_irqtype == type) &&
330 (mp_irqs[i].mpc_srcbusirq == irq))
332 return mp_irqs[i].mpc_dstirq;
333 }
334 return -1;
335 }
337 static int __init find_isa_irq_apic(int irq, int type)
338 {
339 int i;
341 for (i = 0; i < mp_irq_entries; i++) {
342 int lbus = mp_irqs[i].mpc_srcbus;
344 if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA ||
345 mp_bus_id_to_type[lbus] == MP_BUS_EISA ||
346 mp_bus_id_to_type[lbus] == MP_BUS_MCA ||
347 mp_bus_id_to_type[lbus] == MP_BUS_NEC98
348 ) &&
349 (mp_irqs[i].mpc_irqtype == type) &&
350 (mp_irqs[i].mpc_srcbusirq == irq))
351 break;
352 }
353 if (i < mp_irq_entries) {
354 int apic;
355 for(apic = 0; apic < nr_ioapics; apic++) {
356 if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic)
357 return apic;
358 }
359 }
361 return -1;
362 }
364 /*
365 * Find a specific PCI IRQ entry.
366 * Not an __init, possibly needed by modules
367 */
368 static int pin_2_irq(int idx, int apic, int pin);
370 /*
371 * This function currently is only a helper for the i386 smp boot process where
372 * we need to reprogram the ioredtbls to cater for the cpus which have come online
373 * so mask in all cases should simply be TARGET_CPUS
374 */
375 #ifdef CONFIG_SMP
376 void /*__init*/ setup_ioapic_dest(void)
377 {
378 int pin, ioapic, irq, irq_entry;
380 if (skip_ioapic_setup == 1)
381 return;
383 for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
384 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
385 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
386 if (irq_entry == -1)
387 continue;
388 irq = pin_2_irq(irq_entry, ioapic, pin);
389 set_ioapic_affinity_irq(irq, TARGET_CPUS);
390 }
392 }
393 }
394 #endif
396 /*
397 * EISA Edge/Level control register, ELCR
398 */
399 static int EISA_ELCR(unsigned int irq)
400 {
401 if (irq < 16) {
402 unsigned int port = 0x4d0 + (irq >> 3);
403 return (inb(port) >> (irq & 7)) & 1;
404 }
405 apic_printk(APIC_VERBOSE, KERN_INFO
406 "Broken MPtable reports ISA irq %d\n", irq);
407 return 0;
408 }
410 /* EISA interrupts are always polarity zero and can be edge or level
411 * trigger depending on the ELCR value. If an interrupt is listed as
412 * EISA conforming in the MP table, that means its trigger type must
413 * be read in from the ELCR */
415 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].mpc_srcbusirq))
416 #define default_EISA_polarity(idx) (0)
418 /* ISA interrupts are always polarity zero edge triggered,
419 * when listed as conforming in the MP table. */
421 #define default_ISA_trigger(idx) (0)
422 #define default_ISA_polarity(idx) (0)
424 /* PCI interrupts are always polarity one level triggered,
425 * when listed as conforming in the MP table. */
427 #define default_PCI_trigger(idx) (1)
428 #define default_PCI_polarity(idx) (1)
430 /* MCA interrupts are always polarity zero level triggered,
431 * when listed as conforming in the MP table. */
433 #define default_MCA_trigger(idx) (1)
434 #define default_MCA_polarity(idx) (0)
436 /* NEC98 interrupts are always polarity zero edge triggered,
437 * when listed as conforming in the MP table. */
439 #define default_NEC98_trigger(idx) (0)
440 #define default_NEC98_polarity(idx) (0)
442 static int __init MPBIOS_polarity(int idx)
443 {
444 int bus = mp_irqs[idx].mpc_srcbus;
445 int polarity;
447 /*
448 * Determine IRQ line polarity (high active or low active):
449 */
450 switch (mp_irqs[idx].mpc_irqflag & 3)
451 {
452 case 0: /* conforms, ie. bus-type dependent polarity */
453 {
454 switch (mp_bus_id_to_type[bus])
455 {
456 case MP_BUS_ISA: /* ISA pin */
457 {
458 polarity = default_ISA_polarity(idx);
459 break;
460 }
461 case MP_BUS_EISA: /* EISA pin */
462 {
463 polarity = default_EISA_polarity(idx);
464 break;
465 }
466 case MP_BUS_PCI: /* PCI pin */
467 {
468 polarity = default_PCI_polarity(idx);
469 break;
470 }
471 case MP_BUS_MCA: /* MCA pin */
472 {
473 polarity = default_MCA_polarity(idx);
474 break;
475 }
476 case MP_BUS_NEC98: /* NEC 98 pin */
477 {
478 polarity = default_NEC98_polarity(idx);
479 break;
480 }
481 default:
482 {
483 printk(KERN_WARNING "broken BIOS!!\n");
484 polarity = 1;
485 break;
486 }
487 }
488 break;
489 }
490 case 1: /* high active */
491 {
492 polarity = 0;
493 break;
494 }
495 case 2: /* reserved */
496 {
497 printk(KERN_WARNING "broken BIOS!!\n");
498 polarity = 1;
499 break;
500 }
501 case 3: /* low active */
502 {
503 polarity = 1;
504 break;
505 }
506 default: /* invalid */
507 {
508 printk(KERN_WARNING "broken BIOS!!\n");
509 polarity = 1;
510 break;
511 }
512 }
513 return polarity;
514 }
516 static int MPBIOS_trigger(int idx)
517 {
518 int bus = mp_irqs[idx].mpc_srcbus;
519 int trigger;
521 /*
522 * Determine IRQ trigger mode (edge or level sensitive):
523 */
524 switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
525 {
526 case 0: /* conforms, ie. bus-type dependent */
527 {
528 switch (mp_bus_id_to_type[bus])
529 {
530 case MP_BUS_ISA: /* ISA pin */
531 {
532 trigger = default_ISA_trigger(idx);
533 break;
534 }
535 case MP_BUS_EISA: /* EISA pin */
536 {
537 trigger = default_EISA_trigger(idx);
538 break;
539 }
540 case MP_BUS_PCI: /* PCI pin */
541 {
542 trigger = default_PCI_trigger(idx);
543 break;
544 }
545 case MP_BUS_MCA: /* MCA pin */
546 {
547 trigger = default_MCA_trigger(idx);
548 break;
549 }
550 case MP_BUS_NEC98: /* NEC 98 pin */
551 {
552 trigger = default_NEC98_trigger(idx);
553 break;
554 }
555 default:
556 {
557 printk(KERN_WARNING "broken BIOS!!\n");
558 trigger = 1;
559 break;
560 }
561 }
562 break;
563 }
564 case 1: /* edge */
565 {
566 trigger = 0;
567 break;
568 }
569 case 2: /* reserved */
570 {
571 printk(KERN_WARNING "broken BIOS!!\n");
572 trigger = 1;
573 break;
574 }
575 case 3: /* level */
576 {
577 trigger = 1;
578 break;
579 }
580 default: /* invalid */
581 {
582 printk(KERN_WARNING "broken BIOS!!\n");
583 trigger = 0;
584 break;
585 }
586 }
587 return trigger;
588 }
590 static inline int irq_polarity(int idx)
591 {
592 return MPBIOS_polarity(idx);
593 }
595 static inline int irq_trigger(int idx)
596 {
597 return MPBIOS_trigger(idx);
598 }
600 static int pin_2_irq(int idx, int apic, int pin)
601 {
602 int irq, i;
603 int bus = mp_irqs[idx].mpc_srcbus;
605 /*
606 * Debugging check, we are in big trouble if this message pops up!
607 */
608 if (mp_irqs[idx].mpc_dstirq != pin)
609 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
611 switch (mp_bus_id_to_type[bus])
612 {
613 case MP_BUS_ISA: /* ISA pin */
614 case MP_BUS_EISA:
615 case MP_BUS_MCA:
616 case MP_BUS_NEC98:
617 {
618 irq = mp_irqs[idx].mpc_srcbusirq;
619 break;
620 }
621 case MP_BUS_PCI: /* PCI pin */
622 {
623 /*
624 * PCI IRQs are mapped in order
625 */
626 i = irq = 0;
627 while (i < apic)
628 irq += nr_ioapic_registers[i++];
629 irq += pin;
631 /*
632 * For MPS mode, so far only needed by ES7000 platform
633 */
634 if (ioapic_renumber_irq)
635 irq = ioapic_renumber_irq(apic, irq);
637 break;
638 }
639 default:
640 {
641 printk(KERN_ERR "unknown bus type %d.\n",bus);
642 irq = 0;
643 break;
644 }
645 }
647 return irq;
648 }
650 static inline int IO_APIC_irq_trigger(int irq)
651 {
652 int apic, idx, pin;
654 for (apic = 0; apic < nr_ioapics; apic++) {
655 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
656 idx = find_irq_entry(apic,pin,mp_INT);
657 if ((idx != -1) && (irq == pin_2_irq(idx,apic,pin)))
658 return irq_trigger(idx);
659 }
660 }
661 /*
662 * nonexistent IRQs are edge default
663 */
664 return 0;
665 }
667 /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
668 u8 irq_vector[NR_IRQ_VECTORS] __read_mostly;
670 int free_irq_vector(int vector)
671 {
672 int irq;
674 BUG_ON((vector > LAST_DYNAMIC_VECTOR) || (vector < FIRST_DYNAMIC_VECTOR));
676 spin_lock(&vector_lock);
677 if ((irq = vector_irq[vector]) == AUTO_ASSIGN)
678 vector_irq[vector] = FREE_TO_ASSIGN;
679 spin_unlock(&vector_lock);
681 return (irq == AUTO_ASSIGN) ? 0 : -EINVAL;
682 }
684 int assign_irq_vector(int irq)
685 {
686 static unsigned current_vector = FIRST_DYNAMIC_VECTOR;
687 unsigned vector;
689 BUG_ON(irq >= NR_IRQ_VECTORS);
691 spin_lock(&vector_lock);
693 if ((irq != AUTO_ASSIGN) && (IO_APIC_VECTOR(irq) > 0)) {
694 spin_unlock(&vector_lock);
695 return IO_APIC_VECTOR(irq);
696 }
698 vector = current_vector;
699 while (vector_irq[vector] != FREE_TO_ASSIGN) {
700 vector += 8;
701 if (vector > LAST_DYNAMIC_VECTOR)
702 vector = FIRST_DYNAMIC_VECTOR + ((vector + 1) & 7);
704 if (vector == current_vector) {
705 spin_unlock(&vector_lock);
706 return -ENOSPC;
707 }
708 }
710 current_vector = vector;
711 vector_irq[vector] = irq;
712 if (irq != AUTO_ASSIGN)
713 IO_APIC_VECTOR(irq) = vector;
715 spin_unlock(&vector_lock);
717 return vector;
718 }
720 static struct hw_interrupt_type ioapic_level_type;
721 static struct hw_interrupt_type ioapic_edge_type;
723 #define IOAPIC_AUTO -1
724 #define IOAPIC_EDGE 0
725 #define IOAPIC_LEVEL 1
727 static inline void ioapic_register_intr(int irq, int vector, unsigned long trigger)
728 {
729 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
730 trigger == IOAPIC_LEVEL)
731 irq_desc[vector].handler = &ioapic_level_type;
732 else
733 irq_desc[vector].handler = &ioapic_edge_type;
734 }
736 static void __init setup_IO_APIC_irqs(void)
737 {
738 struct IO_APIC_route_entry entry;
739 int apic, pin, idx, irq, first_notcon = 1, vector;
740 unsigned long flags;
742 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
744 for (apic = 0; apic < nr_ioapics; apic++) {
745 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
747 /*
748 * add it to the IO-APIC irq-routing table:
749 */
750 memset(&entry,0,sizeof(entry));
752 entry.delivery_mode = INT_DELIVERY_MODE;
753 entry.dest_mode = INT_DEST_MODE;
754 entry.mask = 0; /* enable IRQ */
755 entry.dest.logical.logical_dest =
756 cpu_mask_to_apicid(TARGET_CPUS);
758 idx = find_irq_entry(apic,pin,mp_INT);
759 if (idx == -1) {
760 if (first_notcon) {
761 apic_printk(APIC_VERBOSE, KERN_DEBUG
762 " IO-APIC (apicid-pin) %d-%d",
763 mp_ioapics[apic].mpc_apicid,
764 pin);
765 first_notcon = 0;
766 } else
767 apic_printk(APIC_VERBOSE, ", %d-%d",
768 mp_ioapics[apic].mpc_apicid, pin);
769 continue;
770 }
772 entry.trigger = irq_trigger(idx);
773 entry.polarity = irq_polarity(idx);
775 if (irq_trigger(idx)) {
776 entry.trigger = 1;
777 entry.mask = 1;
778 }
780 irq = pin_2_irq(idx, apic, pin);
781 /*
782 * skip adding the timer int on secondary nodes, which causes
783 * a small but painful rift in the time-space continuum
784 */
785 if (multi_timer_check(apic, irq))
786 continue;
787 else
788 add_pin_to_irq(irq, apic, pin);
790 if (!apic && !IO_APIC_IRQ(irq))
791 continue;
793 if (IO_APIC_IRQ(irq)) {
794 vector = assign_irq_vector(irq);
795 entry.vector = vector;
796 ioapic_register_intr(irq, vector, IOAPIC_AUTO);
798 if (!apic && (irq < 16))
799 disable_8259A_irq(irq);
800 }
801 spin_lock_irqsave(&ioapic_lock, flags);
802 io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
803 io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
804 set_native_irq_info(entry.vector, TARGET_CPUS);
805 spin_unlock_irqrestore(&ioapic_lock, flags);
806 }
807 }
809 if (!first_notcon)
810 apic_printk(APIC_VERBOSE, " not connected.\n");
811 }
813 /*
814 * Set up the 8259A-master output pin:
815 */
816 static void __init setup_ExtINT_IRQ0_pin(unsigned int apic, unsigned int pin, int vector)
817 {
818 struct IO_APIC_route_entry entry;
819 unsigned long flags;
821 memset(&entry,0,sizeof(entry));
823 disable_8259A_irq(0);
825 /* mask LVT0 */
826 apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
828 /*
829 * We use logical delivery to get the timer IRQ
830 * to the first CPU.
831 */
832 entry.dest_mode = INT_DEST_MODE;
833 entry.mask = 0; /* unmask IRQ now */
834 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
835 entry.delivery_mode = INT_DELIVERY_MODE;
836 entry.polarity = 0;
837 entry.trigger = 0;
838 entry.vector = vector;
840 /*
841 * The timer IRQ doesn't have to know that behind the
842 * scene we have a 8259A-master in AEOI mode ...
843 */
844 irq_desc[IO_APIC_VECTOR(0)].handler = &ioapic_edge_type;
846 /*
847 * Add it to the IO-APIC irq-routing table:
848 */
849 spin_lock_irqsave(&ioapic_lock, flags);
850 io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
851 io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
852 spin_unlock_irqrestore(&ioapic_lock, flags);
854 enable_8259A_irq(0);
855 }
857 static inline void UNEXPECTED_IO_APIC(void)
858 {
859 }
861 void /*__init*/ __print_IO_APIC(void)
862 {
863 int apic, i;
864 union IO_APIC_reg_00 reg_00;
865 union IO_APIC_reg_01 reg_01;
866 union IO_APIC_reg_02 reg_02;
867 union IO_APIC_reg_03 reg_03;
868 unsigned long flags;
870 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
871 for (i = 0; i < nr_ioapics; i++)
872 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
873 mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
875 /*
876 * We are a bit conservative about what we expect. We have to
877 * know about every hardware change ASAP.
878 */
879 printk(KERN_INFO "testing the IO APIC.......................\n");
881 for (apic = 0; apic < nr_ioapics; apic++) {
883 spin_lock_irqsave(&ioapic_lock, flags);
884 reg_00.raw = io_apic_read(apic, 0);
885 reg_01.raw = io_apic_read(apic, 1);
886 if (reg_01.bits.version >= 0x10)
887 reg_02.raw = io_apic_read(apic, 2);
888 if (reg_01.bits.version >= 0x20)
889 reg_03.raw = io_apic_read(apic, 3);
890 spin_unlock_irqrestore(&ioapic_lock, flags);
892 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
893 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
894 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
895 printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type);
896 printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS);
897 if (reg_00.bits.ID >= get_physical_broadcast())
898 UNEXPECTED_IO_APIC();
899 if (reg_00.bits.__reserved_1 || reg_00.bits.__reserved_2)
900 UNEXPECTED_IO_APIC();
902 printk(KERN_DEBUG ".... register #01: %08X\n", reg_01.raw);
903 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
904 if ( (reg_01.bits.entries != 0x0f) && /* older (Neptune) boards */
905 (reg_01.bits.entries != 0x17) && /* typical ISA+PCI boards */
906 (reg_01.bits.entries != 0x1b) && /* Compaq Proliant boards */
907 (reg_01.bits.entries != 0x1f) && /* dual Xeon boards */
908 (reg_01.bits.entries != 0x22) && /* bigger Xeon boards */
909 (reg_01.bits.entries != 0x2E) &&
910 (reg_01.bits.entries != 0x3F)
911 )
912 UNEXPECTED_IO_APIC();
914 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
915 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
916 if ( (reg_01.bits.version != 0x01) && /* 82489DX IO-APICs */
917 (reg_01.bits.version != 0x10) && /* oldest IO-APICs */
918 (reg_01.bits.version != 0x11) && /* Pentium/Pro IO-APICs */
919 (reg_01.bits.version != 0x13) && /* Xeon IO-APICs */
920 (reg_01.bits.version != 0x20) /* Intel P64H (82806 AA) */
921 )
922 UNEXPECTED_IO_APIC();
923 if (reg_01.bits.__reserved_1 || reg_01.bits.__reserved_2)
924 UNEXPECTED_IO_APIC();
926 /*
927 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
928 * but the value of reg_02 is read as the previous read register
929 * value, so ignore it if reg_02 == reg_01.
930 */
931 if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
932 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
933 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
934 if (reg_02.bits.__reserved_1 || reg_02.bits.__reserved_2)
935 UNEXPECTED_IO_APIC();
936 }
938 /*
939 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
940 * or reg_03, but the value of reg_0[23] is read as the previous read
941 * register value, so ignore it if reg_03 == reg_0[12].
942 */
943 if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
944 reg_03.raw != reg_01.raw) {
945 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
946 printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT);
947 if (reg_03.bits.__reserved_1)
948 UNEXPECTED_IO_APIC();
949 }
951 printk(KERN_DEBUG ".... IRQ redirection table:\n");
953 printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol"
954 " Stat Dest Deli Vect: \n");
956 for (i = 0; i <= reg_01.bits.entries; i++) {
957 struct IO_APIC_route_entry entry;
959 spin_lock_irqsave(&ioapic_lock, flags);
960 *(((int *)&entry)+0) = io_apic_read(apic, 0x10+i*2);
961 *(((int *)&entry)+1) = io_apic_read(apic, 0x11+i*2);
962 spin_unlock_irqrestore(&ioapic_lock, flags);
964 printk(KERN_DEBUG " %02x %03X %02X ",
965 i,
966 entry.dest.logical.logical_dest,
967 entry.dest.physical.physical_dest
968 );
970 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
971 entry.mask,
972 entry.trigger,
973 entry.irr,
974 entry.polarity,
975 entry.delivery_status,
976 entry.dest_mode,
977 entry.delivery_mode,
978 entry.vector
979 );
980 }
981 }
982 printk(KERN_INFO "Using vector-based indexing\n");
983 printk(KERN_DEBUG "IRQ to pin mappings:\n");
984 for (i = 0; i < NR_IRQS; i++) {
985 struct irq_pin_list *entry = irq_2_pin + i;
986 if (entry->pin < 0)
987 continue;
988 printk(KERN_DEBUG "IRQ%d ", IO_APIC_VECTOR(i));
989 for (;;) {
990 printk("-> %d:%d", entry->apic, entry->pin);
991 if (!entry->next)
992 break;
993 entry = irq_2_pin + entry->next;
994 }
995 printk("\n");
996 }
998 printk(KERN_INFO ".................................... done.\n");
1000 return;
1003 void print_IO_APIC(void)
1005 if (apic_verbosity != APIC_QUIET)
1006 __print_IO_APIC();
1009 void print_IO_APIC_keyhandler(unsigned char key)
1011 __print_IO_APIC();
1014 static void __init enable_IO_APIC(void)
1016 union IO_APIC_reg_01 reg_01;
1017 int i8259_apic, i8259_pin;
1018 int i, apic;
1019 unsigned long flags;
1021 for (i = 0; i < PIN_MAP_SIZE; i++) {
1022 irq_2_pin[i].pin = -1;
1023 irq_2_pin[i].next = 0;
1026 /* Initialise dynamic irq_2_pin free list. */
1027 for (i = NR_IRQS; i < PIN_MAP_SIZE; i++)
1028 irq_2_pin[i].next = i + 1;
1030 /*
1031 * The number of IO-APIC IRQ registers (== #pins):
1032 */
1033 for (apic = 0; apic < nr_ioapics; apic++) {
1034 spin_lock_irqsave(&ioapic_lock, flags);
1035 reg_01.raw = io_apic_read(apic, 1);
1036 spin_unlock_irqrestore(&ioapic_lock, flags);
1037 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1039 for(apic = 0; apic < nr_ioapics; apic++) {
1040 int pin;
1041 /* See if any of the pins is in ExtINT mode */
1042 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1043 struct IO_APIC_route_entry entry;
1044 spin_lock_irqsave(&ioapic_lock, flags);
1045 *(((int *)&entry) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
1046 *(((int *)&entry) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
1047 spin_unlock_irqrestore(&ioapic_lock, flags);
1050 /* If the interrupt line is enabled and in ExtInt mode
1051 * I have found the pin where the i8259 is connected.
1052 */
1053 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1054 ioapic_i8259.apic = apic;
1055 ioapic_i8259.pin = pin;
1056 goto found_i8259;
1060 found_i8259:
1061 /* Look to see what if the MP table has reported the ExtINT */
1062 /* If we could not find the appropriate pin by looking at the ioapic
1063 * the i8259 probably is not connected the ioapic but give the
1064 * mptable a chance anyway.
1065 */
1066 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1067 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1068 /* Trust the MP table if nothing is setup in the hardware */
1069 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1070 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1071 ioapic_i8259.pin = i8259_pin;
1072 ioapic_i8259.apic = i8259_apic;
1074 /* Complain if the MP table and the hardware disagree */
1075 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1076 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1078 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1081 /*
1082 * Do not trust the IO-APIC being empty at bootup
1083 */
1084 clear_IO_APIC();
1087 /*
1088 * Not an __init, needed by the reboot code
1089 */
1090 void disable_IO_APIC(void)
1092 /*
1093 * Clear the IO-APIC before rebooting:
1094 */
1095 clear_IO_APIC();
1097 /*
1098 * If the i8259 is routed through an IOAPIC
1099 * Put that IOAPIC in virtual wire mode
1100 * so legacy interrupts can be delivered.
1101 */
1102 if (ioapic_i8259.pin != -1) {
1103 struct IO_APIC_route_entry entry;
1104 unsigned long flags;
1106 memset(&entry, 0, sizeof(entry));
1107 entry.mask = 0; /* Enabled */
1108 entry.trigger = 0; /* Edge */
1109 entry.irr = 0;
1110 entry.polarity = 0; /* High */
1111 entry.delivery_status = 0;
1112 entry.dest_mode = 0; /* Physical */
1113 entry.delivery_mode = dest_ExtINT; /* ExtInt */
1114 entry.vector = 0;
1115 entry.dest.physical.physical_dest =
1116 get_apic_id();
1118 /*
1119 * Add it to the IO-APIC irq-routing table:
1120 */
1121 spin_lock_irqsave(&ioapic_lock, flags);
1122 io_apic_write(ioapic_i8259.apic, 0x11+2*ioapic_i8259.pin,
1123 *(((int *)&entry)+1));
1124 io_apic_write(ioapic_i8259.apic, 0x10+2*ioapic_i8259.pin,
1125 *(((int *)&entry)+0));
1126 spin_unlock_irqrestore(&ioapic_lock, flags);
1128 disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1131 /*
1132 * function to set the IO-APIC physical IDs based on the
1133 * values stored in the MPC table.
1135 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
1136 */
1138 #ifndef CONFIG_X86_NUMAQ
1139 static void __init setup_ioapic_ids_from_mpc(void)
1141 union IO_APIC_reg_00 reg_00;
1142 physid_mask_t phys_id_present_map;
1143 int apic;
1144 int i;
1145 unsigned char old_id;
1146 unsigned long flags;
1148 /*
1149 * Don't check I/O APIC IDs for xAPIC systems. They have
1150 * no meaning without the serial APIC bus.
1151 */
1152 if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
1153 || APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
1154 return;
1156 /*
1157 * This is broken; anything with a real cpu count has to
1158 * circumvent this idiocy regardless.
1159 */
1160 phys_id_present_map = ioapic_phys_id_map(phys_cpu_present_map);
1162 /*
1163 * Set the IOAPIC ID to the value stored in the MPC table.
1164 */
1165 for (apic = 0; apic < nr_ioapics; apic++) {
1167 /* Read the register 0 value */
1168 spin_lock_irqsave(&ioapic_lock, flags);
1169 reg_00.raw = io_apic_read(apic, 0);
1170 spin_unlock_irqrestore(&ioapic_lock, flags);
1172 old_id = mp_ioapics[apic].mpc_apicid;
1174 if (mp_ioapics[apic].mpc_apicid >= get_physical_broadcast()) {
1175 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1176 apic, mp_ioapics[apic].mpc_apicid);
1177 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1178 reg_00.bits.ID);
1179 mp_ioapics[apic].mpc_apicid = reg_00.bits.ID;
1182 /*
1183 * Sanity check, is the ID really free? Every APIC in a
1184 * system must have a unique ID or we get lots of nice
1185 * 'stuck on smp_invalidate_needed IPI wait' messages.
1186 */
1187 if (check_apicid_used(phys_id_present_map,
1188 mp_ioapics[apic].mpc_apicid)) {
1189 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1190 apic, mp_ioapics[apic].mpc_apicid);
1191 for (i = 0; i < get_physical_broadcast(); i++)
1192 if (!physid_isset(i, phys_id_present_map))
1193 break;
1194 if (i >= get_physical_broadcast())
1195 panic("Max APIC ID exceeded!\n");
1196 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1197 i);
1198 physid_set(i, phys_id_present_map);
1199 mp_ioapics[apic].mpc_apicid = i;
1200 } else {
1201 physid_mask_t tmp;
1202 tmp = apicid_to_cpu_present(mp_ioapics[apic].mpc_apicid);
1203 apic_printk(APIC_VERBOSE, "Setting %d in the "
1204 "phys_id_present_map\n",
1205 mp_ioapics[apic].mpc_apicid);
1206 physids_or(phys_id_present_map, phys_id_present_map, tmp);
1210 /*
1211 * We need to adjust the IRQ routing table
1212 * if the ID changed.
1213 */
1214 if (old_id != mp_ioapics[apic].mpc_apicid)
1215 for (i = 0; i < mp_irq_entries; i++)
1216 if (mp_irqs[i].mpc_dstapic == old_id)
1217 mp_irqs[i].mpc_dstapic
1218 = mp_ioapics[apic].mpc_apicid;
1220 /*
1221 * Read the right value from the MPC table and
1222 * write it into the ID register.
1223 */
1224 apic_printk(APIC_VERBOSE, KERN_INFO
1225 "...changing IO-APIC physical APIC ID to %d ...",
1226 mp_ioapics[apic].mpc_apicid);
1228 reg_00.bits.ID = mp_ioapics[apic].mpc_apicid;
1229 spin_lock_irqsave(&ioapic_lock, flags);
1230 io_apic_write(apic, 0, reg_00.raw);
1231 spin_unlock_irqrestore(&ioapic_lock, flags);
1233 /*
1234 * Sanity check
1235 */
1236 spin_lock_irqsave(&ioapic_lock, flags);
1237 reg_00.raw = io_apic_read(apic, 0);
1238 spin_unlock_irqrestore(&ioapic_lock, flags);
1239 if (reg_00.bits.ID != mp_ioapics[apic].mpc_apicid)
1240 printk("could not set ID!\n");
1241 else
1242 apic_printk(APIC_VERBOSE, " ok.\n");
1245 #else
1246 static void __init setup_ioapic_ids_from_mpc(void) { }
1247 #endif
1249 /*
1250 * There is a nasty bug in some older SMP boards, their mptable lies
1251 * about the timer IRQ. We do the following to work around the situation:
1253 * - timer IRQ defaults to IO-APIC IRQ
1254 * - if this function detects that timer IRQs are defunct, then we fall
1255 * back to ISA timer IRQs
1256 */
1257 static int __init timer_irq_works(void)
1259 extern unsigned long pit0_ticks;
1260 unsigned long t1;
1262 t1 = pit0_ticks;
1263 mb();
1265 local_irq_enable();
1266 /* Let ten ticks pass... */
1267 mdelay((10 * 1000) / HZ);
1269 /*
1270 * Expect a few ticks at least, to be sure some possible
1271 * glue logic does not lock up after one or two first
1272 * ticks in a non-ExtINT mode. Also the local APIC
1273 * might have cached one ExtINT interrupt. Finally, at
1274 * least one tick may be lost due to delays.
1275 */
1276 mb();
1277 if (pit0_ticks - t1 > 4)
1278 return 1;
1280 return 0;
1283 /*
1284 * In the SMP+IOAPIC case it might happen that there are an unspecified
1285 * number of pending IRQ events unhandled. These cases are very rare,
1286 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1287 * better to do it this way as thus we do not have to be aware of
1288 * 'pending' interrupts in the IRQ path, except at this point.
1289 */
1290 /*
1291 * Edge triggered needs to resend any interrupt
1292 * that was delayed but this is now handled in the device
1293 * independent code.
1294 */
1296 /*
1297 * Starting up a edge-triggered IO-APIC interrupt is
1298 * nasty - we need to make sure that we get the edge.
1299 * If it is already asserted for some reason, we need
1300 * return 1 to indicate that is was pending.
1302 * This is not complete - we should be able to fake
1303 * an edge even if it isn't on the 8259A...
1304 */
1305 static unsigned int startup_edge_ioapic_irq(unsigned int irq)
1307 int was_pending = 0;
1308 unsigned long flags;
1310 spin_lock_irqsave(&ioapic_lock, flags);
1311 if (irq < 16) {
1312 disable_8259A_irq(irq);
1313 if (i8259A_irq_pending(irq))
1314 was_pending = 1;
1316 __unmask_IO_APIC_irq(irq);
1317 spin_unlock_irqrestore(&ioapic_lock, flags);
1319 return was_pending;
1322 /*
1323 * Once we have recorded IRQ_PENDING already, we can mask the
1324 * interrupt for real. This prevents IRQ storms from unhandled
1325 * devices.
1326 */
1327 static void ack_edge_ioapic_irq(unsigned int irq)
1329 if ((irq_desc[IO_APIC_VECTOR(irq)].status & (IRQ_PENDING | IRQ_DISABLED))
1330 == (IRQ_PENDING | IRQ_DISABLED))
1331 mask_IO_APIC_irq(irq);
1332 ack_APIC_irq();
1335 /*
1336 * Level triggered interrupts can just be masked,
1337 * and shutting down and starting up the interrupt
1338 * is the same as enabling and disabling them -- except
1339 * with a startup need to return a "was pending" value.
1341 * Level triggered interrupts are special because we
1342 * do not touch any IO-APIC register while handling
1343 * them. We ack the APIC in the end-IRQ handler, not
1344 * in the start-IRQ-handler. Protection against reentrance
1345 * from the same interrupt is still provided, both by the
1346 * generic IRQ layer and by the fact that an unacked local
1347 * APIC does not accept IRQs.
1348 */
1349 static unsigned int startup_level_ioapic_irq (unsigned int irq)
1351 unmask_IO_APIC_irq(irq);
1353 return 0; /* don't check for pending */
1356 int ioapic_ack_new = 1;
1357 static void setup_ioapic_ack(char *s)
1359 if ( !strcmp(s, "old") )
1360 ioapic_ack_new = 0;
1361 else if ( !strcmp(s, "new") )
1362 ioapic_ack_new = 1;
1363 else
1364 printk("Unknown ioapic_ack value specified: '%s'\n", s);
1366 custom_param("ioapic_ack", setup_ioapic_ack);
1368 static void mask_and_ack_level_ioapic_irq (unsigned int irq)
1370 unsigned long v;
1371 int i;
1373 if ( ioapic_ack_new )
1374 return;
1376 mask_IO_APIC_irq(irq);
1378 /*
1379 * It appears there is an erratum which affects at least version 0x11
1380 * of I/O APIC (that's the 82093AA and cores integrated into various
1381 * chipsets). Under certain conditions a level-triggered interrupt is
1382 * erroneously delivered as edge-triggered one but the respective IRR
1383 * bit gets set nevertheless. As a result the I/O unit expects an EOI
1384 * message but it will never arrive and further interrupts are blocked
1385 * from the source. The exact reason is so far unknown, but the
1386 * phenomenon was observed when two consecutive interrupt requests
1387 * from a given source get delivered to the same CPU and the source is
1388 * temporarily disabled in between.
1390 * A workaround is to simulate an EOI message manually. We achieve it
1391 * by setting the trigger mode to edge and then to level when the edge
1392 * trigger mode gets detected in the TMR of a local APIC for a
1393 * level-triggered interrupt. We mask the source for the time of the
1394 * operation to prevent an edge-triggered interrupt escaping meanwhile.
1395 * The idea is from Manfred Spraul. --macro
1396 */
1397 i = IO_APIC_VECTOR(irq);
1399 v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
1401 ack_APIC_irq();
1403 if (!(v & (1 << (i & 0x1f)))) {
1404 atomic_inc(&irq_mis_count);
1405 spin_lock(&ioapic_lock);
1406 __edge_IO_APIC_irq(irq);
1407 __level_IO_APIC_irq(irq);
1408 spin_unlock(&ioapic_lock);
1412 static void end_level_ioapic_irq (unsigned int irq)
1414 unsigned long v;
1415 int i;
1417 if ( !ioapic_ack_new )
1419 if ( !(irq_desc[IO_APIC_VECTOR(irq)].status & IRQ_DISABLED) )
1420 unmask_IO_APIC_irq(irq);
1421 return;
1424 /*
1425 * It appears there is an erratum which affects at least version 0x11
1426 * of I/O APIC (that's the 82093AA and cores integrated into various
1427 * chipsets). Under certain conditions a level-triggered interrupt is
1428 * erroneously delivered as edge-triggered one but the respective IRR
1429 * bit gets set nevertheless. As a result the I/O unit expects an EOI
1430 * message but it will never arrive and further interrupts are blocked
1431 * from the source. The exact reason is so far unknown, but the
1432 * phenomenon was observed when two consecutive interrupt requests
1433 * from a given source get delivered to the same CPU and the source is
1434 * temporarily disabled in between.
1436 * A workaround is to simulate an EOI message manually. We achieve it
1437 * by setting the trigger mode to edge and then to level when the edge
1438 * trigger mode gets detected in the TMR of a local APIC for a
1439 * level-triggered interrupt. We mask the source for the time of the
1440 * operation to prevent an edge-triggered interrupt escaping meanwhile.
1441 * The idea is from Manfred Spraul. --macro
1442 */
1443 i = IO_APIC_VECTOR(irq);
1445 v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
1447 ack_APIC_irq();
1449 if (!(v & (1 << (i & 0x1f)))) {
1450 atomic_inc(&irq_mis_count);
1451 spin_lock(&ioapic_lock);
1452 __mask_IO_APIC_irq(irq);
1453 __edge_IO_APIC_irq(irq);
1454 __level_IO_APIC_irq(irq);
1455 if ( !(irq_desc[IO_APIC_VECTOR(irq)].status & IRQ_DISABLED) )
1456 __unmask_IO_APIC_irq(irq);
1457 spin_unlock(&ioapic_lock);
1461 static unsigned int startup_edge_ioapic_vector(unsigned int vector)
1463 int irq = vector_to_irq(vector);
1464 return startup_edge_ioapic_irq(irq);
1467 static void ack_edge_ioapic_vector(unsigned int vector)
1469 int irq = vector_to_irq(vector);
1470 ack_edge_ioapic_irq(irq);
1473 static unsigned int startup_level_ioapic_vector(unsigned int vector)
1475 int irq = vector_to_irq(vector);
1476 return startup_level_ioapic_irq (irq);
1479 static void mask_and_ack_level_ioapic_vector(unsigned int vector)
1481 int irq = vector_to_irq(vector);
1482 mask_and_ack_level_ioapic_irq(irq);
1485 static void end_level_ioapic_vector(unsigned int vector)
1487 int irq = vector_to_irq(vector);
1488 end_level_ioapic_irq(irq);
1491 static void mask_IO_APIC_vector(unsigned int vector)
1493 int irq = vector_to_irq(vector);
1494 mask_IO_APIC_irq(irq);
1497 static void unmask_IO_APIC_vector(unsigned int vector)
1499 int irq = vector_to_irq(vector);
1500 unmask_IO_APIC_irq(irq);
1503 static void set_ioapic_affinity_vector(
1504 unsigned int vector, cpumask_t cpu_mask)
1506 int irq = vector_to_irq(vector);
1508 set_native_irq_info(vector, cpu_mask);
1509 set_ioapic_affinity_irq(irq, cpu_mask);
1512 static void disable_edge_ioapic_vector(unsigned int vector)
1516 static void end_edge_ioapic_vector(unsigned int vector)
1520 /*
1521 * Level and edge triggered IO-APIC interrupts need different handling,
1522 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
1523 * handled with the level-triggered descriptor, but that one has slightly
1524 * more overhead. Level-triggered interrupts cannot be handled with the
1525 * edge-triggered handler, without risking IRQ storms and other ugly
1526 * races.
1527 */
1528 static struct hw_interrupt_type ioapic_edge_type = {
1529 .typename = "IO-APIC-edge",
1530 .startup = startup_edge_ioapic_vector,
1531 .shutdown = disable_edge_ioapic_vector,
1532 .enable = unmask_IO_APIC_vector,
1533 .disable = disable_edge_ioapic_vector,
1534 .ack = ack_edge_ioapic_vector,
1535 .end = end_edge_ioapic_vector,
1536 .set_affinity = set_ioapic_affinity_vector,
1537 };
1539 static struct hw_interrupt_type ioapic_level_type = {
1540 .typename = "IO-APIC-level",
1541 .startup = startup_level_ioapic_vector,
1542 .shutdown = mask_IO_APIC_vector,
1543 .enable = unmask_IO_APIC_vector,
1544 .disable = mask_IO_APIC_vector,
1545 .ack = mask_and_ack_level_ioapic_vector,
1546 .end = end_level_ioapic_vector,
1547 .set_affinity = set_ioapic_affinity_vector,
1548 };
1550 static void mask_msi_vector(unsigned int vector)
1552 mask_msi_irq(vector);
1555 static void unmask_msi_vector(unsigned int vector)
1557 unmask_msi_irq(vector);
1560 static unsigned int startup_msi_vector(unsigned int vector)
1562 dprintk(XENLOG_INFO, "startup msi vector %x\n", vector);
1563 unmask_msi_irq(vector);
1564 return 0;
1567 static void ack_msi_vector(unsigned int vector)
1569 ack_APIC_irq();
1572 static void end_msi_vector(unsigned int vector)
1576 static void shutdown_msi_vector(unsigned int vector)
1578 dprintk(XENLOG_INFO, "shutdown msi vector %x\n", vector);
1579 mask_msi_irq(vector);
1582 static void set_msi_affinity_vector(unsigned int vector, cpumask_t cpu_mask)
1584 set_native_irq_info(vector, cpu_mask);
1585 set_msi_irq_affinity(vector, cpu_mask);
1588 /*
1589 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
1590 * which implement the MSI or MSI-X Capability Structure.
1591 */
1592 struct hw_interrupt_type pci_msi_type = {
1593 .typename = "PCI-MSI",
1594 .startup = startup_msi_vector,
1595 .shutdown = shutdown_msi_vector,
1596 .enable = unmask_msi_vector,
1597 .disable = mask_msi_vector,
1598 .ack = ack_msi_vector,
1599 .end = end_msi_vector,
1600 .set_affinity = set_msi_affinity_vector,
1601 };
1603 static inline void init_IO_APIC_traps(void)
1605 int irq;
1606 /* Xen: This is way simpler than the Linux implementation. */
1607 for (irq = 0; irq < 16 ; irq++)
1608 if (IO_APIC_IRQ(irq) && !IO_APIC_VECTOR(irq))
1609 make_8259A_irq(irq);
1612 static void enable_lapic_vector(unsigned int vector)
1614 unsigned long v;
1616 v = apic_read(APIC_LVT0);
1617 apic_write_around(APIC_LVT0, v & ~APIC_LVT_MASKED);
1620 static void disable_lapic_vector(unsigned int vector)
1622 unsigned long v;
1624 v = apic_read(APIC_LVT0);
1625 apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED);
1628 static void ack_lapic_vector(unsigned int vector)
1630 ack_APIC_irq();
1633 static void end_lapic_vector(unsigned int vector) { /* nothing */ }
1635 static struct hw_interrupt_type lapic_irq_type = {
1636 .typename = "local-APIC-edge",
1637 .startup = NULL, /* startup_irq() not used for IRQ0 */
1638 .shutdown = NULL, /* shutdown_irq() not used for IRQ0 */
1639 .enable = enable_lapic_vector,
1640 .disable = disable_lapic_vector,
1641 .ack = ack_lapic_vector,
1642 .end = end_lapic_vector
1643 };
1645 /*
1646 * This looks a bit hackish but it's about the only one way of sending
1647 * a few INTA cycles to 8259As and any associated glue logic. ICR does
1648 * not support the ExtINT mode, unfortunately. We need to send these
1649 * cycles as some i82489DX-based boards have glue logic that keeps the
1650 * 8259A interrupt line asserted until INTA. --macro
1651 */
1652 static inline void unlock_ExtINT_logic(void)
1654 int apic, pin, i;
1655 struct IO_APIC_route_entry entry0, entry1;
1656 unsigned char save_control, save_freq_select;
1657 unsigned long flags;
1659 pin = find_isa_irq_pin(8, mp_INT);
1660 apic = find_isa_irq_apic(8, mp_INT);
1661 if (pin == -1)
1662 return;
1664 spin_lock_irqsave(&ioapic_lock, flags);
1665 *(((int *)&entry0) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
1666 *(((int *)&entry0) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
1667 spin_unlock_irqrestore(&ioapic_lock, flags);
1668 clear_IO_APIC_pin(apic, pin);
1670 memset(&entry1, 0, sizeof(entry1));
1672 entry1.dest_mode = 0; /* physical delivery */
1673 entry1.mask = 0; /* unmask IRQ now */
1674 entry1.dest.physical.physical_dest = hard_smp_processor_id();
1675 entry1.delivery_mode = dest_ExtINT;
1676 entry1.polarity = entry0.polarity;
1677 entry1.trigger = 0;
1678 entry1.vector = 0;
1680 spin_lock_irqsave(&ioapic_lock, flags);
1681 io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry1) + 1));
1682 io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry1) + 0));
1683 spin_unlock_irqrestore(&ioapic_lock, flags);
1685 save_control = CMOS_READ(RTC_CONTROL);
1686 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
1687 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
1688 RTC_FREQ_SELECT);
1689 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
1691 i = 100;
1692 while (i-- > 0) {
1693 mdelay(10);
1694 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
1695 i -= 10;
1698 CMOS_WRITE(save_control, RTC_CONTROL);
1699 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
1700 clear_IO_APIC_pin(apic, pin);
1702 spin_lock_irqsave(&ioapic_lock, flags);
1703 io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry0) + 1));
1704 io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry0) + 0));
1705 spin_unlock_irqrestore(&ioapic_lock, flags);
1708 int timer_uses_ioapic_pin_0;
1710 /*
1711 * This code may look a bit paranoid, but it's supposed to cooperate with
1712 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
1713 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
1714 * fanatically on his truly buggy board.
1715 */
1716 static inline void check_timer(void)
1718 int apic1, pin1, apic2, pin2;
1719 int vector;
1721 /*
1722 * get/set the timer IRQ vector:
1723 */
1724 disable_8259A_irq(0);
1725 vector = assign_irq_vector(0);
1727 irq_desc[IO_APIC_VECTOR(0)].action = irq_desc[LEGACY_VECTOR(0)].action;
1728 irq_desc[IO_APIC_VECTOR(0)].depth = 0;
1729 irq_desc[IO_APIC_VECTOR(0)].status &= ~IRQ_DISABLED;
1731 /*
1732 * Subtle, code in do_timer_interrupt() expects an AEOI
1733 * mode for the 8259A whenever interrupts are routed
1734 * through I/O APICs. Also IRQ0 has to be enabled in
1735 * the 8259A which implies the virtual wire has to be
1736 * disabled in the local APIC.
1737 */
1738 apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1739 init_8259A(1);
1740 /* XEN: Ripped out the legacy missed-tick logic, so below is not needed. */
1741 /*timer_ack = 1;*/
1742 /*enable_8259A_irq(0);*/
1744 pin1 = find_isa_irq_pin(0, mp_INT);
1745 apic1 = find_isa_irq_apic(0, mp_INT);
1746 pin2 = ioapic_i8259.pin;
1747 apic2 = ioapic_i8259.apic;
1749 if (pin1 == 0)
1750 timer_uses_ioapic_pin_0 = 1;
1752 printk(KERN_INFO "..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",
1753 vector, apic1, pin1, apic2, pin2);
1755 if (pin1 != -1) {
1756 /*
1757 * Ok, does IRQ0 through the IOAPIC work?
1758 */
1759 unmask_IO_APIC_irq(0);
1760 if (timer_irq_works()) {
1761 if (disable_timer_pin_1 > 0)
1762 clear_IO_APIC_pin(apic1, pin1);
1763 return;
1765 clear_IO_APIC_pin(apic1, pin1);
1766 printk(KERN_ERR "..MP-BIOS bug: 8254 timer not connected to "
1767 "IO-APIC\n");
1770 printk(KERN_INFO "...trying to set up timer (IRQ0) through the 8259A ... ");
1771 if (pin2 != -1) {
1772 printk("\n..... (found pin %d) ...", pin2);
1773 /*
1774 * legacy devices should be connected to IO APIC #0
1775 */
1776 setup_ExtINT_IRQ0_pin(apic2, pin2, vector);
1777 if (timer_irq_works()) {
1778 printk("works.\n");
1779 if (pin1 != -1)
1780 replace_pin_at_irq(0, apic1, pin1, apic2, pin2);
1781 else
1782 add_pin_to_irq(0, apic2, pin2);
1783 return;
1785 /*
1786 * Cleanup, just in case ...
1787 */
1788 clear_IO_APIC_pin(apic2, pin2);
1790 printk(" failed.\n");
1792 if (nmi_watchdog == NMI_IO_APIC) {
1793 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
1794 nmi_watchdog = 0;
1797 printk(KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
1799 disable_8259A_irq(0);
1800 irq_desc[vector].handler = &lapic_irq_type;
1801 apic_write_around(APIC_LVT0, APIC_DM_FIXED | vector); /* Fixed mode */
1802 enable_8259A_irq(0);
1804 if (timer_irq_works()) {
1805 printk(" works.\n");
1806 return;
1808 apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector);
1809 printk(" failed.\n");
1811 printk(KERN_INFO "...trying to set up timer as ExtINT IRQ...");
1813 /*timer_ack = 0;*/
1814 init_8259A(0);
1815 make_8259A_irq(0);
1816 apic_write_around(APIC_LVT0, APIC_DM_EXTINT);
1818 unlock_ExtINT_logic();
1820 if (timer_irq_works()) {
1821 printk(" works.\n");
1822 return;
1824 printk(" failed :(.\n");
1825 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
1826 "report. Then try booting with the 'noapic' option");
1829 /*
1831 * IRQ's that are handled by the PIC in the MPS IOAPIC case.
1832 * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
1833 * Linux doesn't really care, as it's not actually used
1834 * for any interrupt handling anyway.
1835 */
1836 #define PIC_IRQS (1 << PIC_CASCADE_IR)
1838 void __init setup_IO_APIC(void)
1840 enable_IO_APIC();
1842 if (acpi_ioapic)
1843 io_apic_irqs = ~0; /* all IRQs go through IOAPIC */
1844 else
1845 io_apic_irqs = ~PIC_IRQS;
1847 printk("ENABLING IO-APIC IRQs\n");
1848 printk(" -> Using %s ACK method\n", ioapic_ack_new ? "new" : "old");
1850 /*
1851 * Set up IO-APIC IRQ routing.
1852 */
1853 if (!acpi_ioapic)
1854 setup_ioapic_ids_from_mpc();
1855 sync_Arb_IDs();
1856 setup_IO_APIC_irqs();
1857 init_IO_APIC_traps();
1858 check_timer();
1859 print_IO_APIC();
1861 register_keyhandler('z', print_IO_APIC_keyhandler, "print ioapic info");
1864 struct IO_APIC_route_entry *ioapic_pm_state=NULL;
1866 void ioapic_pm_state_alloc(void)
1868 int i, nr_entry = 0;
1870 if (ioapic_pm_state != NULL)
1871 return;
1873 for (i = 0; i < nr_ioapics; i++)
1874 nr_entry += nr_ioapic_registers[i];
1876 ioapic_pm_state = _xmalloc(sizeof(struct IO_APIC_route_entry)*nr_entry,
1877 sizeof(struct IO_APIC_route_entry));
1880 int ioapic_suspend(void)
1882 struct IO_APIC_route_entry *entry;
1883 unsigned long flags;
1884 int apic,i;
1886 ioapic_pm_state_alloc();
1888 if (ioapic_pm_state == NULL) {
1889 printk("Cannot suspend ioapic due to lack of memory\n");
1890 return 1;
1893 entry = ioapic_pm_state;
1895 spin_lock_irqsave(&ioapic_lock, flags);
1896 for (apic = 0; apic < nr_ioapics; apic++) {
1897 for (i = 0; i < nr_ioapic_registers[apic]; i ++, entry ++ ) {
1898 *(((int *)entry) + 1) = io_apic_read(apic, 0x11 + 2 * i);
1899 *(((int *)entry) + 0) = io_apic_read(apic, 0x10 + 2 * i);
1902 spin_unlock_irqrestore(&ioapic_lock, flags);
1904 return 0;
1907 int ioapic_resume(void)
1909 struct IO_APIC_route_entry *entry;
1910 unsigned long flags;
1911 union IO_APIC_reg_00 reg_00;
1912 int i,apic;
1914 if (ioapic_pm_state == NULL){
1915 printk("Cannot resume ioapic due to lack of memory\n");
1916 return 1;
1919 entry = ioapic_pm_state;
1921 spin_lock_irqsave(&ioapic_lock, flags);
1922 for (apic = 0; apic < nr_ioapics; apic++){
1923 reg_00.raw = io_apic_read(apic, 0);
1924 if (reg_00.bits.ID != mp_ioapics[apic].mpc_apicid) {
1925 reg_00.bits.ID = mp_ioapics[apic].mpc_apicid;
1926 io_apic_write(apic, 0, reg_00.raw);
1928 for (i = 0; i < nr_ioapic_registers[apic]; i++, entry++) {
1929 io_apic_write(apic, 0x11+2*i, *(((int *)entry)+1));
1930 io_apic_write(apic, 0x10+2*i, *(((int *)entry)+0));
1933 spin_unlock_irqrestore(&ioapic_lock, flags);
1935 return 0;
1938 /* --------------------------------------------------------------------------
1939 ACPI-based IOAPIC Configuration
1940 -------------------------------------------------------------------------- */
1942 #ifdef CONFIG_ACPI_BOOT
1944 int __init io_apic_get_unique_id (int ioapic, int apic_id)
1946 union IO_APIC_reg_00 reg_00;
1947 static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
1948 physid_mask_t tmp;
1949 unsigned long flags;
1950 int i = 0;
1952 /*
1953 * The P4 platform supports up to 256 APIC IDs on two separate APIC
1954 * buses (one for LAPICs, one for IOAPICs), where predecessors only
1955 * supports up to 16 on one shared APIC bus.
1957 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
1958 * advantage of new APIC bus architecture.
1959 */
1961 if (physids_empty(apic_id_map))
1962 apic_id_map = ioapic_phys_id_map(phys_cpu_present_map);
1964 spin_lock_irqsave(&ioapic_lock, flags);
1965 reg_00.raw = io_apic_read(ioapic, 0);
1966 spin_unlock_irqrestore(&ioapic_lock, flags);
1968 if (apic_id >= get_physical_broadcast()) {
1969 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
1970 "%d\n", ioapic, apic_id, reg_00.bits.ID);
1971 apic_id = reg_00.bits.ID;
1974 /*
1975 * Every APIC in a system must have a unique ID or we get lots of nice
1976 * 'stuck on smp_invalidate_needed IPI wait' messages.
1977 */
1978 if (check_apicid_used(apic_id_map, apic_id)) {
1980 for (i = 0; i < get_physical_broadcast(); i++) {
1981 if (!check_apicid_used(apic_id_map, i))
1982 break;
1985 if (i == get_physical_broadcast())
1986 panic("Max apic_id exceeded!\n");
1988 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
1989 "trying %d\n", ioapic, apic_id, i);
1991 apic_id = i;
1994 tmp = apicid_to_cpu_present(apic_id);
1995 physids_or(apic_id_map, apic_id_map, tmp);
1997 if (reg_00.bits.ID != apic_id) {
1998 reg_00.bits.ID = apic_id;
2000 spin_lock_irqsave(&ioapic_lock, flags);
2001 io_apic_write(ioapic, 0, reg_00.raw);
2002 reg_00.raw = io_apic_read(ioapic, 0);
2003 spin_unlock_irqrestore(&ioapic_lock, flags);
2005 /* Sanity check */
2006 if (reg_00.bits.ID != apic_id) {
2007 printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic);
2008 return -1;
2012 apic_printk(APIC_VERBOSE, KERN_INFO
2013 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
2015 return apic_id;
2019 int __init io_apic_get_version (int ioapic)
2021 union IO_APIC_reg_01 reg_01;
2022 unsigned long flags;
2024 spin_lock_irqsave(&ioapic_lock, flags);
2025 reg_01.raw = io_apic_read(ioapic, 1);
2026 spin_unlock_irqrestore(&ioapic_lock, flags);
2028 return reg_01.bits.version;
2032 int __init io_apic_get_redir_entries (int ioapic)
2034 union IO_APIC_reg_01 reg_01;
2035 unsigned long flags;
2037 spin_lock_irqsave(&ioapic_lock, flags);
2038 reg_01.raw = io_apic_read(ioapic, 1);
2039 spin_unlock_irqrestore(&ioapic_lock, flags);
2041 return reg_01.bits.entries;
2045 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int edge_level, int active_high_low)
2047 struct IO_APIC_route_entry entry;
2048 unsigned long flags;
2050 if (!IO_APIC_IRQ(irq)) {
2051 printk(KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
2052 ioapic);
2053 return -EINVAL;
2056 /*
2057 * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
2058 * Note that we mask (disable) IRQs now -- these get enabled when the
2059 * corresponding device driver registers for this IRQ.
2060 */
2062 memset(&entry,0,sizeof(entry));
2064 entry.delivery_mode = INT_DELIVERY_MODE;
2065 entry.dest_mode = INT_DEST_MODE;
2066 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
2067 entry.trigger = edge_level;
2068 entry.polarity = active_high_low;
2069 entry.mask = 1;
2071 /*
2072 * IRQs < 16 are already in the irq_2_pin[] map
2073 */
2074 if (irq >= 16)
2075 add_pin_to_irq(irq, ioapic, pin);
2077 entry.vector = assign_irq_vector(irq);
2079 apic_printk(APIC_DEBUG, KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry "
2080 "(%d-%d -> 0x%x -> IRQ %d Mode:%i Active:%i)\n", ioapic,
2081 mp_ioapics[ioapic].mpc_apicid, pin, entry.vector, irq,
2082 edge_level, active_high_low);
2084 ioapic_register_intr(irq, entry.vector, edge_level);
2086 if (!ioapic && (irq < 16))
2087 disable_8259A_irq(irq);
2089 spin_lock_irqsave(&ioapic_lock, flags);
2090 io_apic_write(ioapic, 0x11+2*pin, *(((int *)&entry)+1));
2091 io_apic_write(ioapic, 0x10+2*pin, *(((int *)&entry)+0));
2092 set_native_irq_info(entry.vector, TARGET_CPUS);
2093 spin_unlock_irqrestore(&ioapic_lock, flags);
2095 return 0;
2098 #endif /*CONFIG_ACPI_BOOT*/
2100 static int ioapic_physbase_to_id(unsigned long physbase)
2102 int apic;
2103 for ( apic = 0; apic < nr_ioapics; apic++ )
2104 if ( mp_ioapics[apic].mpc_apicaddr == physbase )
2105 return apic;
2106 return -EINVAL;
2109 int ioapic_guest_read(unsigned long physbase, unsigned int reg, u32 *pval)
2111 int apic;
2112 unsigned long flags;
2114 if ( (apic = ioapic_physbase_to_id(physbase)) < 0 )
2115 return apic;
2117 spin_lock_irqsave(&ioapic_lock, flags);
2118 *pval = io_apic_read(apic, reg);
2119 spin_unlock_irqrestore(&ioapic_lock, flags);
2121 return 0;
2124 #define WARN_BOGUS_WRITE(f, a...) \
2125 dprintk(XENLOG_INFO, "\n%s: " \
2126 "apic=%d, pin=%d, old_irq=%d, new_irq=%d\n" \
2127 "%s: old_entry=%08x, new_entry=%08x\n" \
2128 "%s: " f, __FUNCTION__, apic, pin, old_irq, new_irq, \
2129 __FUNCTION__, *(u32 *)&old_rte, *(u32 *)&new_rte, \
2130 __FUNCTION__ , ##a )
2132 int ioapic_guest_write(unsigned long physbase, unsigned int reg, u32 val)
2134 int apic, pin, old_irq = -1, new_irq = -1;
2135 struct IO_APIC_route_entry old_rte = { 0 }, new_rte = { 0 };
2136 unsigned long flags;
2138 if ( (apic = ioapic_physbase_to_id(physbase)) < 0 )
2139 return apic;
2141 /* Only write to the first half of a route entry. */
2142 if ( (reg < 0x10) || (reg & 1) )
2143 return 0;
2145 pin = (reg - 0x10) >> 1;
2147 /* Write first half from guest; second half is target info. */
2148 *(u32 *)&new_rte = val;
2149 new_rte.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
2151 /*
2152 * What about weird destination types?
2153 * SMI: Ignore? Ought to be set up by the BIOS.
2154 * NMI: Ignore? Watchdog functionality is Xen's concern.
2155 * INIT: Definitely ignore: probably a guest OS bug.
2156 * ExtINT: Ignore? Linux only asserts this at start of day.
2157 * For now, print a message and return an error. We can fix up on demand.
2158 */
2159 if ( new_rte.delivery_mode > dest_LowestPrio )
2161 printk("ERROR: Attempt to write weird IOAPIC destination mode!\n");
2162 printk(" APIC=%d/%d, lo-reg=%x\n", apic, pin, val);
2163 return -EINVAL;
2166 /*
2167 * The guest does not know physical APIC arrangement (flat vs. cluster).
2168 * Apply genapic conventions for this platform.
2169 */
2170 new_rte.delivery_mode = INT_DELIVERY_MODE;
2171 new_rte.dest_mode = INT_DEST_MODE;
2173 spin_lock_irqsave(&ioapic_lock, flags);
2175 /* Read first (interesting) half of current routing entry. */
2176 *(u32 *)&old_rte = io_apic_read(apic, 0x10 + 2 * pin);
2178 /* No change to the first half of the routing entry? Bail quietly. */
2179 if ( *(u32 *)&old_rte == *(u32 *)&new_rte )
2181 spin_unlock_irqrestore(&ioapic_lock, flags);
2182 return 0;
2185 /* Special delivery modes (SMI,NMI,INIT,ExtInt) should have no vector. */
2186 if ( (old_rte.delivery_mode > dest_LowestPrio) && (old_rte.vector != 0) )
2188 WARN_BOGUS_WRITE("Special delivery mode %d with non-zero vector "
2189 "%02x\n", old_rte.delivery_mode, old_rte.vector);
2190 /* Nobble the vector here as it does not relate to a valid irq. */
2191 old_rte.vector = 0;
2194 if ( old_rte.vector >= FIRST_DYNAMIC_VECTOR )
2195 old_irq = vector_irq[old_rte.vector];
2196 if ( new_rte.vector >= FIRST_DYNAMIC_VECTOR )
2197 new_irq = vector_irq[new_rte.vector];
2199 if ( (old_irq != new_irq) && (old_irq >= 0) && IO_APIC_IRQ(old_irq) )
2201 if ( irq_desc[IO_APIC_VECTOR(old_irq)].action )
2203 WARN_BOGUS_WRITE("Attempt to remove IO-APIC pin of in-use IRQ!\n");
2204 spin_unlock_irqrestore(&ioapic_lock, flags);
2205 return 0;
2208 remove_pin_at_irq(old_irq, apic, pin);
2211 if ( (new_irq >= 0) && IO_APIC_IRQ(new_irq) )
2213 if ( irq_desc[IO_APIC_VECTOR(new_irq)].action )
2215 WARN_BOGUS_WRITE("Attempt to %s IO-APIC pin for in-use IRQ!\n",
2216 (old_irq != new_irq) ? "add" : "modify");
2217 spin_unlock_irqrestore(&ioapic_lock, flags);
2218 return 0;
2221 /* Set the correct irq-handling type. */
2222 irq_desc[IO_APIC_VECTOR(new_irq)].handler = new_rte.trigger ?
2223 &ioapic_level_type: &ioapic_edge_type;
2225 if ( old_irq != new_irq )
2226 add_pin_to_irq(new_irq, apic, pin);
2228 /* Mask iff level triggered. */
2229 new_rte.mask = new_rte.trigger;
2231 else if ( !new_rte.mask )
2233 /* This pin leads nowhere but the guest has not masked it. */
2234 WARN_BOGUS_WRITE("Installing bogus unmasked IO-APIC entry!\n");
2235 new_rte.mask = 1;
2239 io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&new_rte) + 0));
2240 io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&new_rte) + 1));
2242 spin_unlock_irqrestore(&ioapic_lock, flags);
2244 return 0;
2247 void dump_ioapic_irq_info(void)
2249 struct irq_pin_list *entry;
2250 struct IO_APIC_route_entry rte;
2251 unsigned int irq, pin, printed = 0;
2252 unsigned long flags;
2254 for ( irq = 0; irq < NR_IRQS; irq++ )
2256 entry = &irq_2_pin[irq];
2257 if ( entry->pin == -1 )
2258 continue;
2260 if ( !printed++ )
2261 printk("IO-APIC interrupt information:\n");
2263 printk(" IRQ%3d Vec%3d:\n", irq, irq_to_vector(irq));
2265 for ( ; ; )
2267 pin = entry->pin;
2269 printk(" Apic 0x%02x, Pin %2d: ", entry->apic, pin);
2271 spin_lock_irqsave(&ioapic_lock, flags);
2272 *(((int *)&rte) + 0) = io_apic_read(entry->apic, 0x10 + 2 * pin);
2273 *(((int *)&rte) + 1) = io_apic_read(entry->apic, 0x11 + 2 * pin);
2274 spin_unlock_irqrestore(&ioapic_lock, flags);
2276 printk("vector=%u, delivery_mode=%u, dest_mode=%s, "
2277 "delivery_status=%d, polarity=%d, irr=%d, "
2278 "trigger=%s, mask=%d\n",
2279 rte.vector, rte.delivery_mode,
2280 rte.dest_mode ? "logical" : "physical",
2281 rte.delivery_status, rte.polarity, rte.irr,
2282 rte.trigger ? "level" : "edge", rte.mask);
2284 if ( entry->next == 0 )
2285 break;
2286 entry = &irq_2_pin[entry->next];