ia64/xen-unstable

view extras/mini-os/hypervisor.c @ 9788:bdcc838b9a72

Add small memory warning message to domain configuration examples.

Signed-off-by: Daniel Stekloff <dsteklof@us.ibm.com>
author stekloff@dyn9047022152.beaverton.ibm.com
date Wed Apr 19 22:58:24 2006 +0100 (2006-04-19)
parents 198828cc103b
children f6507937cb7c
line source
1 /******************************************************************************
2 * hypervisor.c
3 *
4 * Communication to/from hypervisor.
5 *
6 * Copyright (c) 2002-2003, K A Fraser
7 * Copyright (c) 2005, Grzegorz Milos, gm281@cam.ac.uk,Intel Research Cambridge
8 *
9 * Permission is hereby granted, free of charge, to any person obtaining a copy
10 * of this software and associated documentation files (the "Software"), to
11 * deal in the Software without restriction, including without limitation the
12 * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
13 * sell copies of the Software, and to permit persons to whom the Software is
14 * furnished to do so, subject to the following conditions:
15 *
16 * The above copyright notice and this permission notice shall be included in
17 * all copies or substantial portions of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
22 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
26 */
28 #include <os.h>
29 #include <hypervisor.h>
30 #include <events.h>
32 #define active_evtchns(cpu,sh,idx) \
33 ((sh)->evtchn_pending[idx] & \
34 ~(sh)->evtchn_mask[idx])
36 void do_hypervisor_callback(struct pt_regs *regs)
37 {
38 u32 l1, l2;
39 unsigned int l1i, l2i, port;
40 int cpu = 0;
41 shared_info_t *s = HYPERVISOR_shared_info;
42 vcpu_info_t *vcpu_info = &s->vcpu_info[cpu];
44 vcpu_info->evtchn_upcall_pending = 0;
46 /* NB. No need for a barrier here -- XCHG is a barrier on x86. */
47 l1 = xchg(&vcpu_info->evtchn_pending_sel, 0);
48 while ( l1 != 0 )
49 {
50 l1i = __ffs(l1);
51 l1 &= ~(1 << l1i);
53 while ( (l2 = active_evtchns(cpu, s, l1i)) != 0 )
54 {
55 l2i = __ffs(l2);
56 l2 &= ~(1 << l2i);
58 port = (l1i << 5) + l2i;
59 do_event(port, regs);
60 }
61 }
62 }
65 inline void mask_evtchn(u32 port)
66 {
67 shared_info_t *s = HYPERVISOR_shared_info;
68 synch_set_bit(port, &s->evtchn_mask[0]);
69 }
71 inline void unmask_evtchn(u32 port)
72 {
73 shared_info_t *s = HYPERVISOR_shared_info;
74 vcpu_info_t *vcpu_info = &s->vcpu_info[smp_processor_id()];
76 synch_clear_bit(port, &s->evtchn_mask[0]);
78 /*
79 * The following is basically the equivalent of 'hw_resend_irq'. Just like
80 * a real IO-APIC we 'lose the interrupt edge' if the channel is masked.
81 */
82 if ( synch_test_bit (port, &s->evtchn_pending[0]) &&
83 !synch_test_and_set_bit(port>>5, &vcpu_info->evtchn_pending_sel) )
84 {
85 vcpu_info->evtchn_upcall_pending = 1;
86 if ( !vcpu_info->evtchn_upcall_mask )
87 force_evtchn_callback();
88 }
89 }
91 inline void clear_evtchn(u32 port)
92 {
93 shared_info_t *s = HYPERVISOR_shared_info;
94 synch_clear_bit(port, &s->evtchn_pending[0]);
95 }