ia64/xen-unstable

view xen/arch/ia64/linux-xen/setup.c @ 9690:bdb08c9ef3d1

[IA64] Remove unused variables. init_mm and swapper_pg_dir.

Signed-off-by: Kouya Shimura <kouya@jp.fujitsu.com>
author awilliam@xenbuild.aw
date Mon Apr 17 08:46:52 2006 -0600 (2006-04-17)
parents 3b3a5588baca
children ced37bea0647
line source
1 /*
2 * Architecture-specific setup.
3 *
4 * Copyright (C) 1998-2001, 2003-2004 Hewlett-Packard Co
5 * David Mosberger-Tang <davidm@hpl.hp.com>
6 * Stephane Eranian <eranian@hpl.hp.com>
7 * Copyright (C) 2000, 2004 Intel Corp
8 * Rohit Seth <rohit.seth@intel.com>
9 * Suresh Siddha <suresh.b.siddha@intel.com>
10 * Gordon Jin <gordon.jin@intel.com>
11 * Copyright (C) 1999 VA Linux Systems
12 * Copyright (C) 1999 Walt Drummond <drummond@valinux.com>
13 *
14 * 12/26/04 S.Siddha, G.Jin, R.Seth
15 * Add multi-threading and multi-core detection
16 * 11/12/01 D.Mosberger Convert get_cpuinfo() to seq_file based show_cpuinfo().
17 * 04/04/00 D.Mosberger renamed cpu_initialized to cpu_online_map
18 * 03/31/00 R.Seth cpu_initialized and current->processor fixes
19 * 02/04/00 D.Mosberger some more get_cpuinfo fixes...
20 * 02/01/00 R.Seth fixed get_cpuinfo for SMP
21 * 01/07/99 S.Eranian added the support for command line argument
22 * 06/24/99 W.Drummond added boot_cpu_data.
23 * 05/28/05 Z. Menyhart Dynamic stride size for "flush_icache_range()"
24 */
25 #include <linux/config.h>
26 #include <linux/module.h>
27 #include <linux/init.h>
29 #include <linux/acpi.h>
30 #include <linux/bootmem.h>
31 #include <linux/console.h>
32 #include <linux/delay.h>
33 #include <linux/kernel.h>
34 #include <linux/reboot.h>
35 #include <linux/sched.h>
36 #include <linux/seq_file.h>
37 #include <linux/string.h>
38 #include <linux/threads.h>
39 #include <linux/tty.h>
40 #include <linux/serial.h>
41 #include <linux/serial_core.h>
42 #include <linux/efi.h>
43 #include <linux/initrd.h>
44 #ifndef XEN
45 #include <linux/platform.h>
46 #include <linux/pm.h>
47 #endif
49 #include <asm/ia32.h>
50 #include <asm/machvec.h>
51 #include <asm/mca.h>
52 #include <asm/meminit.h>
53 #include <asm/page.h>
54 #include <asm/patch.h>
55 #include <asm/pgtable.h>
56 #include <asm/processor.h>
57 #include <asm/sal.h>
58 #include <asm/sections.h>
59 #include <asm/serial.h>
60 #include <asm/setup.h>
61 #include <asm/smp.h>
62 #include <asm/system.h>
63 #include <asm/unistd.h>
64 #ifdef XEN
65 #include <asm/vmx.h>
66 #include <asm/io.h>
67 #endif
69 #if defined(CONFIG_SMP) && (IA64_CPU_SIZE > PAGE_SIZE)
70 # error "struct cpuinfo_ia64 too big!"
71 #endif
73 #ifdef CONFIG_SMP
74 unsigned long __per_cpu_offset[NR_CPUS];
75 EXPORT_SYMBOL(__per_cpu_offset);
76 #endif
78 DEFINE_PER_CPU(struct cpuinfo_ia64, cpu_info);
79 #ifdef XEN
80 DEFINE_PER_CPU(cpu_kr_ia64_t, cpu_kr);
81 #endif
82 DEFINE_PER_CPU(unsigned long, local_per_cpu_offset);
83 DEFINE_PER_CPU(unsigned long, ia64_phys_stacked_size_p8);
84 unsigned long ia64_cycles_per_usec;
85 struct ia64_boot_param *ia64_boot_param;
86 struct screen_info screen_info;
87 unsigned long vga_console_iobase;
88 unsigned long vga_console_membase;
90 unsigned long ia64_max_cacheline_size;
91 unsigned long ia64_iobase; /* virtual address for I/O accesses */
92 EXPORT_SYMBOL(ia64_iobase);
93 struct io_space io_space[MAX_IO_SPACES];
94 EXPORT_SYMBOL(io_space);
95 unsigned int num_io_spaces;
97 #ifdef XEN
98 extern void early_cmdline_parse(char **);
99 #endif
101 /*
102 * "flush_icache_range()" needs to know what processor dependent stride size to use
103 * when it makes i-cache(s) coherent with d-caches.
104 */
105 #define I_CACHE_STRIDE_SHIFT 5 /* Safest way to go: 32 bytes by 32 bytes */
106 unsigned long ia64_i_cache_stride_shift = ~0;
108 #ifdef XEN
109 #define D_CACHE_STRIDE_SHIFT 5 /* Safest. */
110 unsigned long ia64_d_cache_stride_shift = ~0;
111 #endif
113 /*
114 * The merge_mask variable needs to be set to (max(iommu_page_size(iommu)) - 1). This
115 * mask specifies a mask of address bits that must be 0 in order for two buffers to be
116 * mergeable by the I/O MMU (i.e., the end address of the first buffer and the start
117 * address of the second buffer must be aligned to (merge_mask+1) in order to be
118 * mergeable). By default, we assume there is no I/O MMU which can merge physically
119 * discontiguous buffers, so we set the merge_mask to ~0UL, which corresponds to a iommu
120 * page-size of 2^64.
121 */
122 unsigned long ia64_max_iommu_merge_mask = ~0UL;
123 EXPORT_SYMBOL(ia64_max_iommu_merge_mask);
125 /*
126 * We use a special marker for the end of memory and it uses the extra (+1) slot
127 */
128 struct rsvd_region rsvd_region[IA64_MAX_RSVD_REGIONS + 1];
129 int num_rsvd_regions;
132 /*
133 * Filter incoming memory segments based on the primitive map created from the boot
134 * parameters. Segments contained in the map are removed from the memory ranges. A
135 * caller-specified function is called with the memory ranges that remain after filtering.
136 * This routine does not assume the incoming segments are sorted.
137 */
138 int
139 filter_rsvd_memory (unsigned long start, unsigned long end, void *arg)
140 {
141 unsigned long range_start, range_end, prev_start;
142 void (*func)(unsigned long, unsigned long, int);
143 int i;
145 #if IGNORE_PFN0
146 if (start == PAGE_OFFSET) {
147 printk(KERN_WARNING "warning: skipping physical page 0\n");
148 start += PAGE_SIZE;
149 if (start >= end) return 0;
150 }
151 #endif
152 /*
153 * lowest possible address(walker uses virtual)
154 */
155 prev_start = PAGE_OFFSET;
156 func = arg;
158 for (i = 0; i < num_rsvd_regions; ++i) {
159 range_start = max(start, prev_start);
160 range_end = min(end, rsvd_region[i].start);
162 if (range_start < range_end)
163 #ifdef XEN
164 {
165 /* init_boot_pages requires "ps, pe" */
166 printk("Init boot pages: 0x%lx -> 0x%lx.\n",
167 __pa(range_start), __pa(range_end));
168 (*func)(__pa(range_start), __pa(range_end), 0);
169 }
170 #else
171 call_pernode_memory(__pa(range_start), range_end - range_start, func);
172 #endif
174 /* nothing more available in this segment */
175 if (range_end == end) return 0;
177 prev_start = rsvd_region[i].end;
178 }
179 /* end of memory marker allows full processing inside loop body */
180 return 0;
181 }
183 static void
184 sort_regions (struct rsvd_region *rsvd_region, int max)
185 {
186 int j;
188 /* simple bubble sorting */
189 while (max--) {
190 for (j = 0; j < max; ++j) {
191 if (rsvd_region[j].start > rsvd_region[j+1].start) {
192 struct rsvd_region tmp;
193 tmp = rsvd_region[j];
194 rsvd_region[j] = rsvd_region[j + 1];
195 rsvd_region[j + 1] = tmp;
196 }
197 }
198 }
199 }
201 /**
202 * reserve_memory - setup reserved memory areas
203 *
204 * Setup the reserved memory areas set aside for the boot parameters,
205 * initrd, etc. There are currently %IA64_MAX_RSVD_REGIONS defined,
206 * see include/asm-ia64/meminit.h if you need to define more.
207 */
208 void
209 reserve_memory (void)
210 {
211 int n = 0;
213 /*
214 * none of the entries in this table overlap
215 */
216 rsvd_region[n].start = (unsigned long) ia64_boot_param;
217 rsvd_region[n].end = rsvd_region[n].start + sizeof(*ia64_boot_param);
218 n++;
220 rsvd_region[n].start = (unsigned long) __va(ia64_boot_param->efi_memmap);
221 rsvd_region[n].end = rsvd_region[n].start + ia64_boot_param->efi_memmap_size;
222 n++;
224 rsvd_region[n].start = (unsigned long) __va(ia64_boot_param->command_line);
225 rsvd_region[n].end = (rsvd_region[n].start
226 + strlen(__va(ia64_boot_param->command_line)) + 1);
227 n++;
229 rsvd_region[n].start = (unsigned long) ia64_imva((void *)KERNEL_START);
230 #ifdef XEN
231 /* Reserve xen image/bitmap/xen-heap */
232 rsvd_region[n].end = rsvd_region[n].start + xenheap_size;
233 #else
234 rsvd_region[n].end = (unsigned long) ia64_imva(_end);
235 #endif
236 n++;
238 #ifdef CONFIG_BLK_DEV_INITRD
239 if (ia64_boot_param->initrd_start) {
240 rsvd_region[n].start = (unsigned long)__va(ia64_boot_param->initrd_start);
241 rsvd_region[n].end = rsvd_region[n].start + ia64_boot_param->initrd_size;
242 n++;
243 }
244 #endif
246 /* end of memory marker */
247 rsvd_region[n].start = ~0UL;
248 rsvd_region[n].end = ~0UL;
249 n++;
251 num_rsvd_regions = n;
253 sort_regions(rsvd_region, num_rsvd_regions);
254 }
256 /**
257 * find_initrd - get initrd parameters from the boot parameter structure
258 *
259 * Grab the initrd start and end from the boot parameter struct given us by
260 * the boot loader.
261 */
262 void
263 find_initrd (void)
264 {
265 #ifdef CONFIG_BLK_DEV_INITRD
266 if (ia64_boot_param->initrd_start) {
267 initrd_start = (unsigned long)__va(ia64_boot_param->initrd_start);
268 initrd_end = initrd_start+ia64_boot_param->initrd_size;
270 printk(KERN_INFO "Initial ramdisk at: 0x%lx (%lu bytes)\n",
271 initrd_start, ia64_boot_param->initrd_size);
272 }
273 #endif
274 }
276 static void __init
277 io_port_init (void)
278 {
279 extern unsigned long ia64_iobase;
280 unsigned long phys_iobase;
282 /*
283 * Set `iobase' to the appropriate address in region 6 (uncached access range).
284 *
285 * The EFI memory map is the "preferred" location to get the I/O port space base,
286 * rather the relying on AR.KR0. This should become more clear in future SAL
287 * specs. We'll fall back to getting it out of AR.KR0 if no appropriate entry is
288 * found in the memory map.
289 */
290 phys_iobase = efi_get_iobase();
291 if (phys_iobase)
292 /* set AR.KR0 since this is all we use it for anyway */
293 ia64_set_kr(IA64_KR_IO_BASE, phys_iobase);
294 else {
295 phys_iobase = ia64_get_kr(IA64_KR_IO_BASE);
296 printk(KERN_INFO "No I/O port range found in EFI memory map, falling back "
297 "to AR.KR0\n");
298 printk(KERN_INFO "I/O port base = 0x%lx\n", phys_iobase);
299 }
300 ia64_iobase = (unsigned long) ioremap(phys_iobase, 0);
302 /* setup legacy IO port space */
303 io_space[0].mmio_base = ia64_iobase;
304 io_space[0].sparse = 1;
305 num_io_spaces = 1;
306 }
308 /**
309 * early_console_setup - setup debugging console
310 *
311 * Consoles started here require little enough setup that we can start using
312 * them very early in the boot process, either right after the machine
313 * vector initialization, or even before if the drivers can detect their hw.
314 *
315 * Returns non-zero if a console couldn't be setup.
316 */
317 static inline int __init
318 early_console_setup (char *cmdline)
319 {
320 int earlycons = 0;
322 #ifdef CONFIG_SERIAL_SGI_L1_CONSOLE
323 {
324 extern int sn_serial_console_early_setup(void);
325 if (!sn_serial_console_early_setup())
326 earlycons++;
327 }
328 #endif
329 #ifdef CONFIG_EFI_PCDP
330 if (!efi_setup_pcdp_console(cmdline))
331 earlycons++;
332 #endif
333 #ifdef CONFIG_SERIAL_8250_CONSOLE
334 if (!early_serial_console_init(cmdline))
335 earlycons++;
336 #endif
338 return (earlycons) ? 0 : -1;
339 }
341 static inline void
342 mark_bsp_online (void)
343 {
344 #ifdef CONFIG_SMP
345 /* If we register an early console, allow CPU 0 to printk */
346 cpu_set(smp_processor_id(), cpu_online_map);
347 #endif
348 }
350 #ifdef CONFIG_SMP
351 static void
352 check_for_logical_procs (void)
353 {
354 pal_logical_to_physical_t info;
355 s64 status;
357 status = ia64_pal_logical_to_phys(0, &info);
358 if (status == -1) {
359 printk(KERN_INFO "No logical to physical processor mapping "
360 "available\n");
361 return;
362 }
363 if (status) {
364 printk(KERN_ERR "ia64_pal_logical_to_phys failed with %ld\n",
365 status);
366 return;
367 }
368 /*
369 * Total number of siblings that BSP has. Though not all of them
370 * may have booted successfully. The correct number of siblings
371 * booted is in info.overview_num_log.
372 */
373 smp_num_siblings = info.overview_tpc;
374 smp_num_cpucores = info.overview_cpp;
375 }
376 #endif
378 void __init
379 #ifdef XEN
380 early_setup_arch (char **cmdline_p)
381 #else
382 setup_arch (char **cmdline_p)
383 #endif
384 {
385 unw_init();
387 ia64_patch_vtop((u64) __start___vtop_patchlist, (u64) __end___vtop_patchlist);
389 *cmdline_p = __va(ia64_boot_param->command_line);
390 #ifndef XEN
391 strlcpy(saved_command_line, *cmdline_p, COMMAND_LINE_SIZE);
392 #else
393 early_cmdline_parse(cmdline_p);
394 cmdline_parse(*cmdline_p);
395 #endif
397 efi_init();
398 io_port_init();
400 #ifdef CONFIG_IA64_GENERIC
401 {
402 const char *mvec_name = strstr (*cmdline_p, "machvec=");
403 char str[64];
405 if (mvec_name) {
406 const char *end;
407 size_t len;
409 mvec_name += 8;
410 end = strchr (mvec_name, ' ');
411 if (end)
412 len = end - mvec_name;
413 else
414 len = strlen (mvec_name);
415 len = min(len, sizeof (str) - 1);
416 strncpy (str, mvec_name, len);
417 str[len] = '\0';
418 mvec_name = str;
419 } else
420 mvec_name = acpi_get_sysname();
421 machvec_init(mvec_name);
422 }
423 #endif
425 if (early_console_setup(*cmdline_p) == 0)
426 mark_bsp_online();
428 #ifdef XEN
429 }
431 void __init
432 late_setup_arch (char **cmdline_p)
433 {
434 #endif
435 #ifdef CONFIG_ACPI_BOOT
436 /* Initialize the ACPI boot-time table parser */
437 acpi_table_init();
438 # ifdef CONFIG_ACPI_NUMA
439 acpi_numa_init();
440 # endif
441 #else
442 # ifdef CONFIG_SMP
443 smp_build_cpu_map(); /* happens, e.g., with the Ski simulator */
444 # endif
445 #endif /* CONFIG_APCI_BOOT */
447 #ifndef XEN
448 find_memory();
449 #endif
451 /* process SAL system table: */
452 ia64_sal_init(efi.sal_systab);
454 #ifdef CONFIG_SMP
455 #ifdef XEN
456 init_smp_config ();
457 #endif
459 cpu_physical_id(0) = hard_smp_processor_id();
461 cpu_set(0, cpu_sibling_map[0]);
462 cpu_set(0, cpu_core_map[0]);
464 check_for_logical_procs();
465 if (smp_num_cpucores > 1)
466 printk(KERN_INFO
467 "cpu package is Multi-Core capable: number of cores=%d\n",
468 smp_num_cpucores);
469 if (smp_num_siblings > 1)
470 printk(KERN_INFO
471 "cpu package is Multi-Threading capable: number of siblings=%d\n",
472 smp_num_siblings);
473 #endif
475 #ifdef XEN
476 identify_vmx_feature();
477 #endif
479 cpu_init(); /* initialize the bootstrap CPU */
481 #ifdef CONFIG_ACPI_BOOT
482 acpi_boot_init();
483 #endif
485 #ifdef CONFIG_VT
486 if (!conswitchp) {
487 # if defined(CONFIG_DUMMY_CONSOLE)
488 conswitchp = &dummy_con;
489 # endif
490 # if defined(CONFIG_VGA_CONSOLE)
491 /*
492 * Non-legacy systems may route legacy VGA MMIO range to system
493 * memory. vga_con probes the MMIO hole, so memory looks like
494 * a VGA device to it. The EFI memory map can tell us if it's
495 * memory so we can avoid this problem.
496 */
497 if (efi_mem_type(0xA0000) != EFI_CONVENTIONAL_MEMORY)
498 conswitchp = &vga_con;
499 # endif
500 }
501 #endif
503 /* enable IA-64 Machine Check Abort Handling unless disabled */
504 if (!strstr(saved_command_line, "nomca"))
505 ia64_mca_init();
507 platform_setup(cmdline_p);
508 paging_init();
509 }
511 #ifndef XEN
512 /*
513 * Display cpu info for all cpu's.
514 */
515 static int
516 show_cpuinfo (struct seq_file *m, void *v)
517 {
518 #ifdef CONFIG_SMP
519 # define lpj c->loops_per_jiffy
520 # define cpunum c->cpu
521 #else
522 # define lpj loops_per_jiffy
523 # define cpunum 0
524 #endif
525 static struct {
526 unsigned long mask;
527 const char *feature_name;
528 } feature_bits[] = {
529 { 1UL << 0, "branchlong" },
530 { 1UL << 1, "spontaneous deferral"},
531 { 1UL << 2, "16-byte atomic ops" }
532 };
533 char family[32], features[128], *cp, sep;
534 struct cpuinfo_ia64 *c = v;
535 unsigned long mask;
536 int i;
538 mask = c->features;
540 switch (c->family) {
541 case 0x07: memcpy(family, "Itanium", 8); break;
542 case 0x1f: memcpy(family, "Itanium 2", 10); break;
543 default: sprintf(family, "%u", c->family); break;
544 }
546 /* build the feature string: */
547 memcpy(features, " standard", 10);
548 cp = features;
549 sep = 0;
550 for (i = 0; i < (int) ARRAY_SIZE(feature_bits); ++i) {
551 if (mask & feature_bits[i].mask) {
552 if (sep)
553 *cp++ = sep;
554 sep = ',';
555 *cp++ = ' ';
556 strcpy(cp, feature_bits[i].feature_name);
557 cp += strlen(feature_bits[i].feature_name);
558 mask &= ~feature_bits[i].mask;
559 }
560 }
561 if (mask) {
562 /* print unknown features as a hex value: */
563 if (sep)
564 *cp++ = sep;
565 sprintf(cp, " 0x%lx", mask);
566 }
568 seq_printf(m,
569 "processor : %d\n"
570 "vendor : %s\n"
571 "arch : IA-64\n"
572 "family : %s\n"
573 "model : %u\n"
574 "revision : %u\n"
575 "archrev : %u\n"
576 "features :%s\n" /* don't change this---it _is_ right! */
577 "cpu number : %lu\n"
578 "cpu regs : %u\n"
579 "cpu MHz : %lu.%06lu\n"
580 "itc MHz : %lu.%06lu\n"
581 "BogoMIPS : %lu.%02lu\n",
582 cpunum, c->vendor, family, c->model, c->revision, c->archrev,
583 features, c->ppn, c->number,
584 c->proc_freq / 1000000, c->proc_freq % 1000000,
585 c->itc_freq / 1000000, c->itc_freq % 1000000,
586 lpj*HZ/500000, (lpj*HZ/5000) % 100);
587 #ifdef CONFIG_SMP
588 seq_printf(m, "siblings : %u\n", c->num_log);
589 if (c->threads_per_core > 1 || c->cores_per_socket > 1)
590 seq_printf(m,
591 "physical id: %u\n"
592 "core id : %u\n"
593 "thread id : %u\n",
594 c->socket_id, c->core_id, c->thread_id);
595 #endif
596 seq_printf(m,"\n");
598 return 0;
599 }
601 static void *
602 c_start (struct seq_file *m, loff_t *pos)
603 {
604 #ifdef CONFIG_SMP
605 while (*pos < NR_CPUS && !cpu_isset(*pos, cpu_online_map))
606 ++*pos;
607 #endif
608 return *pos < NR_CPUS ? cpu_data(*pos) : NULL;
609 }
611 static void *
612 c_next (struct seq_file *m, void *v, loff_t *pos)
613 {
614 ++*pos;
615 return c_start(m, pos);
616 }
618 static void
619 c_stop (struct seq_file *m, void *v)
620 {
621 }
623 struct seq_operations cpuinfo_op = {
624 .start = c_start,
625 .next = c_next,
626 .stop = c_stop,
627 .show = show_cpuinfo
628 };
629 #endif /* XEN */
631 void
632 identify_cpu (struct cpuinfo_ia64 *c)
633 {
634 union {
635 unsigned long bits[5];
636 struct {
637 /* id 0 & 1: */
638 char vendor[16];
640 /* id 2 */
641 u64 ppn; /* processor serial number */
643 /* id 3: */
644 unsigned number : 8;
645 unsigned revision : 8;
646 unsigned model : 8;
647 unsigned family : 8;
648 unsigned archrev : 8;
649 unsigned reserved : 24;
651 /* id 4: */
652 u64 features;
653 } field;
654 } cpuid;
655 pal_vm_info_1_u_t vm1;
656 pal_vm_info_2_u_t vm2;
657 pal_status_t status;
658 unsigned long impl_va_msb = 50, phys_addr_size = 44; /* Itanium defaults */
659 int i;
661 for (i = 0; i < 5; ++i)
662 cpuid.bits[i] = ia64_get_cpuid(i);
664 memcpy(c->vendor, cpuid.field.vendor, 16);
665 #ifdef CONFIG_SMP
666 c->cpu = smp_processor_id();
668 /* below default values will be overwritten by identify_siblings()
669 * for Multi-Threading/Multi-Core capable cpu's
670 */
671 c->threads_per_core = c->cores_per_socket = c->num_log = 1;
672 c->socket_id = -1;
674 identify_siblings(c);
675 #endif
676 c->ppn = cpuid.field.ppn;
677 c->number = cpuid.field.number;
678 c->revision = cpuid.field.revision;
679 c->model = cpuid.field.model;
680 c->family = cpuid.field.family;
681 c->archrev = cpuid.field.archrev;
682 c->features = cpuid.field.features;
684 status = ia64_pal_vm_summary(&vm1, &vm2);
685 if (status == PAL_STATUS_SUCCESS) {
686 impl_va_msb = vm2.pal_vm_info_2_s.impl_va_msb;
687 phys_addr_size = vm1.pal_vm_info_1_s.phys_add_size;
688 }
689 c->unimpl_va_mask = ~((7L<<61) | ((1L << (impl_va_msb + 1)) - 1));
690 c->unimpl_pa_mask = ~((1L<<63) | ((1L << phys_addr_size) - 1));
692 #ifdef XEN
693 /* If vmx feature is on, do necessary initialization for vmx */
694 if (vmx_enabled)
695 vmx_init_env();
696 #endif
697 }
699 void
700 setup_per_cpu_areas (void)
701 {
702 /* start_kernel() requires this... */
703 }
705 /*
706 * Calculate the max. cache line size.
707 *
708 * In addition, the minimum of the i-cache stride sizes is calculated for
709 * "flush_icache_range()".
710 */
711 static void
712 get_max_cacheline_size (void)
713 {
714 unsigned long line_size, max = 1;
715 u64 l, levels, unique_caches;
716 pal_cache_config_info_t cci;
717 s64 status;
719 status = ia64_pal_cache_summary(&levels, &unique_caches);
720 if (status != 0) {
721 printk(KERN_ERR "%s: ia64_pal_cache_summary() failed (status=%ld)\n",
722 __FUNCTION__, status);
723 max = SMP_CACHE_BYTES;
724 /* Safest setup for "flush_icache_range()" */
725 ia64_i_cache_stride_shift = I_CACHE_STRIDE_SHIFT;
726 #ifdef XEN
727 ia64_d_cache_stride_shift = D_CACHE_STRIDE_SHIFT;
728 #endif
729 goto out;
730 }
732 for (l = 0; l < levels; ++l) {
733 status = ia64_pal_cache_config_info(l, /* cache_type (data_or_unified)= */ 2,
734 &cci);
735 if (status != 0) {
736 printk(KERN_ERR
737 "%s: ia64_pal_cache_config_info(l=%lu, 2) failed (status=%ld)\n",
738 __FUNCTION__, l, status);
739 max = SMP_CACHE_BYTES;
740 /* The safest setup for "flush_icache_range()" */
741 cci.pcci_stride = I_CACHE_STRIDE_SHIFT;
742 cci.pcci_unified = 1;
743 }
744 #ifdef XEN
745 if (cci.pcci_stride < ia64_d_cache_stride_shift)
746 ia64_d_cache_stride_shift = cci.pcci_stride;
747 #endif
748 line_size = 1 << cci.pcci_line_size;
749 if (line_size > max)
750 max = line_size;
751 if (!cci.pcci_unified) {
752 status = ia64_pal_cache_config_info(l,
753 /* cache_type (instruction)= */ 1,
754 &cci);
755 if (status != 0) {
756 printk(KERN_ERR
757 "%s: ia64_pal_cache_config_info(l=%lu, 1) failed (status=%ld)\n",
758 __FUNCTION__, l, status);
759 /* The safest setup for "flush_icache_range()" */
760 cci.pcci_stride = I_CACHE_STRIDE_SHIFT;
761 }
762 }
763 if (cci.pcci_stride < ia64_i_cache_stride_shift)
764 ia64_i_cache_stride_shift = cci.pcci_stride;
765 }
766 out:
767 if (max > ia64_max_cacheline_size)
768 ia64_max_cacheline_size = max;
769 #ifdef XEN
770 if (ia64_d_cache_stride_shift > ia64_i_cache_stride_shift)
771 ia64_d_cache_stride_shift = ia64_i_cache_stride_shift;
772 #endif
774 }
776 /*
777 * cpu_init() initializes state that is per-CPU. This function acts
778 * as a 'CPU state barrier', nothing should get across.
779 */
780 void
781 cpu_init (void)
782 {
783 extern void __devinit ia64_mmu_init (void *);
784 unsigned long num_phys_stacked;
785 #ifndef XEN
786 pal_vm_info_2_u_t vmi;
787 unsigned int max_ctx;
788 #endif
789 struct cpuinfo_ia64 *cpu_info;
790 void *cpu_data;
792 cpu_data = per_cpu_init();
794 #ifdef XEN
795 printf ("cpu_init: current=%p, current->domain->arch.mm=%p\n",
796 current, current->domain->arch.mm);
797 #endif
799 /*
800 * We set ar.k3 so that assembly code in MCA handler can compute
801 * physical addresses of per cpu variables with a simple:
802 * phys = ar.k3 + &per_cpu_var
803 */
804 ia64_set_kr(IA64_KR_PER_CPU_DATA,
805 ia64_tpa(cpu_data) - (long) __per_cpu_start);
807 get_max_cacheline_size();
809 /*
810 * We can't pass "local_cpu_data" to identify_cpu() because we haven't called
811 * ia64_mmu_init() yet. And we can't call ia64_mmu_init() first because it
812 * depends on the data returned by identify_cpu(). We break the dependency by
813 * accessing cpu_data() through the canonical per-CPU address.
814 */
815 cpu_info = cpu_data + ((char *) &__ia64_per_cpu_var(cpu_info) - __per_cpu_start);
816 identify_cpu(cpu_info);
818 #ifdef CONFIG_MCKINLEY
819 {
820 # define FEATURE_SET 16
821 struct ia64_pal_retval iprv;
823 if (cpu_info->family == 0x1f) {
824 PAL_CALL_PHYS(iprv, PAL_PROC_GET_FEATURES, 0, FEATURE_SET, 0);
825 if ((iprv.status == 0) && (iprv.v0 & 0x80) && (iprv.v2 & 0x80))
826 PAL_CALL_PHYS(iprv, PAL_PROC_SET_FEATURES,
827 (iprv.v1 | 0x80), FEATURE_SET, 0);
828 }
829 }
830 #endif
832 /* Clear the stack memory reserved for pt_regs: */
833 memset(ia64_task_regs(current), 0, sizeof(struct pt_regs));
835 ia64_set_kr(IA64_KR_FPU_OWNER, 0);
837 /*
838 * Initialize the page-table base register to a global
839 * directory with all zeroes. This ensure that we can handle
840 * TLB-misses to user address-space even before we created the
841 * first user address-space. This may happen, e.g., due to
842 * aggressive use of lfetch.fault.
843 */
844 ia64_set_kr(IA64_KR_PT_BASE, __pa(ia64_imva(empty_zero_page)));
846 /*
847 * Initialize default control register to defer speculative faults except
848 * for those arising from TLB misses, which are not deferred. The
849 * kernel MUST NOT depend on a particular setting of these bits (in other words,
850 * the kernel must have recovery code for all speculative accesses). Turn on
851 * dcr.lc as per recommendation by the architecture team. Most IA-32 apps
852 * shouldn't be affected by this (moral: keep your ia32 locks aligned and you'll
853 * be fine).
854 */
855 #ifdef XEN
856 ia64_setreg(_IA64_REG_CR_DCR, ( IA64_DCR_DP | IA64_DCR_DK | IA64_DCR_DX | IA64_DCR_DR
857 | IA64_DCR_PP | IA64_DCR_DA | IA64_DCR_DD | IA64_DCR_LC));
858 #else
859 ia64_setreg(_IA64_REG_CR_DCR, ( IA64_DCR_DP | IA64_DCR_DK | IA64_DCR_DX | IA64_DCR_DR
860 | IA64_DCR_DA | IA64_DCR_DD | IA64_DCR_LC));
861 #endif
862 #ifndef XEN
863 atomic_inc(&init_mm.mm_count);
864 current->active_mm = &init_mm;
865 #endif
866 #ifdef XEN
867 if (current->domain->arch.mm)
868 #else
869 if (current->mm)
870 #endif
871 BUG();
873 ia64_mmu_init(ia64_imva(cpu_data));
874 ia64_mca_cpu_init(ia64_imva(cpu_data));
876 #ifdef CONFIG_IA32_SUPPORT
877 ia32_cpu_init();
878 #endif
880 /* Clear ITC to eliminiate sched_clock() overflows in human time. */
881 ia64_set_itc(0);
883 /* disable all local interrupt sources: */
884 ia64_set_itv(1 << 16);
885 ia64_set_lrr0(1 << 16);
886 ia64_set_lrr1(1 << 16);
887 ia64_setreg(_IA64_REG_CR_PMV, 1 << 16);
888 ia64_setreg(_IA64_REG_CR_CMCV, 1 << 16);
890 /* clear TPR & XTP to enable all interrupt classes: */
891 ia64_setreg(_IA64_REG_CR_TPR, 0);
892 #ifdef CONFIG_SMP
893 normal_xtp();
894 #endif
896 #ifndef XEN
897 /* set ia64_ctx.max_rid to the maximum RID that is supported by all CPUs: */
898 if (ia64_pal_vm_summary(NULL, &vmi) == 0)
899 max_ctx = (1U << (vmi.pal_vm_info_2_s.rid_size - 3)) - 1;
900 else {
901 printk(KERN_WARNING "cpu_init: PAL VM summary failed, assuming 18 RID bits\n");
902 max_ctx = (1U << 15) - 1; /* use architected minimum */
903 }
904 while (max_ctx < ia64_ctx.max_ctx) {
905 unsigned int old = ia64_ctx.max_ctx;
906 if (cmpxchg(&ia64_ctx.max_ctx, old, max_ctx) == old)
907 break;
908 }
909 #endif
911 if (ia64_pal_rse_info(&num_phys_stacked, NULL) != 0) {
912 printk(KERN_WARNING "cpu_init: PAL RSE info failed; assuming 96 physical "
913 "stacked regs\n");
914 num_phys_stacked = 96;
915 }
916 /* size of physical stacked register partition plus 8 bytes: */
917 __get_cpu_var(ia64_phys_stacked_size_p8) = num_phys_stacked*8 + 8;
918 platform_cpu_init();
919 #ifndef XEN
920 pm_idle = default_idle;
921 #endif
923 #ifdef XEN
924 /* surrender usage of kernel registers to domain, use percpu area instead */
925 __get_cpu_var(cpu_kr)._kr[IA64_KR_IO_BASE] = ia64_get_kr(IA64_KR_IO_BASE);
926 __get_cpu_var(cpu_kr)._kr[IA64_KR_PER_CPU_DATA] = ia64_get_kr(IA64_KR_PER_CPU_DATA);
927 __get_cpu_var(cpu_kr)._kr[IA64_KR_CURRENT_STACK] = ia64_get_kr(IA64_KR_CURRENT_STACK);
928 __get_cpu_var(cpu_kr)._kr[IA64_KR_FPU_OWNER] = ia64_get_kr(IA64_KR_FPU_OWNER);
929 __get_cpu_var(cpu_kr)._kr[IA64_KR_CURRENT] = ia64_get_kr(IA64_KR_CURRENT);
930 __get_cpu_var(cpu_kr)._kr[IA64_KR_PT_BASE] = ia64_get_kr(IA64_KR_PT_BASE);
931 #endif
932 }
934 void
935 check_bugs (void)
936 {
937 ia64_patch_mckinley_e9((unsigned long) __start___mckinley_e9_bundles,
938 (unsigned long) __end___mckinley_e9_bundles);
939 }