ia64/xen-unstable

view tools/ioemu/hw/vga_int.h @ 17571:b6aa55ca599e

shadow: track video RAM dirty bits

This adds a new HVM op that enables tracking dirty bits of a range of
video RAM. The idea is to optimize just for the most common case
(only one guest mapping, with sometimes some temporary other
mappings), which permits to keep the overhead on shadow as low as
possible.

Signed-off-by: Samuel Thibault <samuel.thibault@eu.citrix.com>
author Keir Fraser <keir.fraser@citrix.com>
date Fri May 02 15:08:27 2008 +0100 (2008-05-02)
parents baff5b3aaf13
children adf05a812edb
line source
1 /*
2 * QEMU internal VGA defines.
3 *
4 * Copyright (c) 2003-2004 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #define MSR_COLOR_EMULATION 0x01
25 #define MSR_PAGE_SELECT 0x20
27 #define ST01_V_RETRACE 0x08
28 #define ST01_DISP_ENABLE 0x01
30 /* bochs VBE support */
31 //#define CONFIG_BOCHS_VBE
33 #define VBE_DISPI_MAX_XRES 1600
34 #define VBE_DISPI_MAX_YRES 1200
35 #define VBE_DISPI_MAX_BPP 32
37 #define VBE_DISPI_INDEX_ID 0x0
38 #define VBE_DISPI_INDEX_XRES 0x1
39 #define VBE_DISPI_INDEX_YRES 0x2
40 #define VBE_DISPI_INDEX_BPP 0x3
41 #define VBE_DISPI_INDEX_ENABLE 0x4
42 #define VBE_DISPI_INDEX_BANK 0x5
43 #define VBE_DISPI_INDEX_VIRT_WIDTH 0x6
44 #define VBE_DISPI_INDEX_VIRT_HEIGHT 0x7
45 #define VBE_DISPI_INDEX_X_OFFSET 0x8
46 #define VBE_DISPI_INDEX_Y_OFFSET 0x9
47 #define VBE_DISPI_INDEX_NB 0xa
49 #define VBE_DISPI_ID0 0xB0C0
50 #define VBE_DISPI_ID1 0xB0C1
51 #define VBE_DISPI_ID2 0xB0C2
52 #define VBE_DISPI_ID3 0xB0C3
53 #define VBE_DISPI_ID4 0xB0C4
55 #define VBE_DISPI_DISABLED 0x00
56 #define VBE_DISPI_ENABLED 0x01
57 #define VBE_DISPI_GETCAPS 0x02
58 #define VBE_DISPI_8BIT_DAC 0x20
59 #define VBE_DISPI_LFB_ENABLED 0x40
60 #define VBE_DISPI_NOCLEARMEM 0x80
62 #define VBE_DISPI_LFB_PHYSICAL_ADDRESS 0xE0000000
64 #ifdef CONFIG_BOCHS_VBE
66 #define VGA_STATE_COMMON_BOCHS_VBE \
67 uint16_t vbe_index; \
68 uint16_t vbe_regs[VBE_DISPI_INDEX_NB]; \
69 uint32_t vbe_start_addr; \
70 uint32_t vbe_line_offset; \
71 uint32_t vbe_bank_mask;
73 #else
75 #define VGA_STATE_COMMON_BOCHS_VBE
77 #endif /* !CONFIG_BOCHS_VBE */
79 #define CH_ATTR_SIZE (160 * 100)
80 #define VGA_MAX_HEIGHT 2048
82 #define VGA_STATE_COMMON \
83 uint8_t *vram_alloc; \
84 uint8_t *vram_ptr; \
85 uint8_t *vram_shadow; \
86 unsigned long vram_offset; \
87 unsigned int vram_size; \
88 unsigned long bios_offset; \
89 unsigned int bios_size; \
90 unsigned long lfb_addr; \
91 unsigned long lfb_end; \
92 PCIDevice *pci_dev; \
93 uint32_t latch; \
94 uint8_t sr_index; \
95 uint8_t sr[256]; \
96 uint8_t gr_index; \
97 uint8_t gr[256]; \
98 uint8_t ar_index; \
99 uint8_t ar[21]; \
100 int ar_flip_flop; \
101 uint8_t cr_index; \
102 uint8_t cr[256]; /* CRT registers */ \
103 uint8_t msr; /* Misc Output Register */ \
104 uint8_t fcr; /* Feature Control Register */ \
105 uint8_t st00; /* status 0 */ \
106 uint8_t st01; /* status 1 */ \
107 uint8_t dac_state; \
108 uint8_t dac_sub_index; \
109 uint8_t dac_read_index; \
110 uint8_t dac_write_index; \
111 uint8_t dac_cache[3]; /* used when writing */ \
112 int dac_8bit; \
113 uint8_t palette[768]; \
114 int32_t bank_offset; \
115 int (*get_bpp)(struct VGAState *s); \
116 void (*get_offsets)(struct VGAState *s, \
117 uint32_t *pline_offset, \
118 uint32_t *pstart_addr, \
119 uint32_t *pline_compare); \
120 void (*get_resolution)(struct VGAState *s, \
121 int *pwidth, \
122 int *pheight); \
123 VGA_STATE_COMMON_BOCHS_VBE \
124 /* display refresh support */ \
125 DisplayState *ds; \
126 uint32_t font_offsets[2]; \
127 int graphic_mode; \
128 uint8_t shift_control; \
129 uint8_t double_scan; \
130 uint32_t line_offset; \
131 uint32_t line_compare; \
132 uint32_t start_addr; \
133 uint32_t plane_updated; \
134 uint32_t last_line_offset; \
135 uint8_t last_cw, last_ch; \
136 uint32_t last_width, last_height; /* in chars or pixels */ \
137 uint32_t last_scr_width, last_scr_height; /* in pixels */ \
138 uint8_t cursor_start, cursor_end; \
139 uint32_t cursor_offset; \
140 unsigned int (*rgb_to_pixel)(unsigned int r, \
141 unsigned int g, unsigned b); \
142 /* hardware mouse cursor support */ \
143 uint32_t invalidated_y_table[VGA_MAX_HEIGHT / 32]; \
144 void (*cursor_invalidate)(struct VGAState *s); \
145 void (*cursor_draw_line)(struct VGAState *s, uint8_t *d, int y); \
146 /* tell for each page if it has been updated since the last time */ \
147 uint32_t last_palette[256]; \
148 uint32_t last_ch_attr[CH_ATTR_SIZE]; /* XXX: make it dynamic */
151 typedef struct VGAState {
152 VGA_STATE_COMMON
153 } VGAState;
155 static inline int c6_to_8(int v)
156 {
157 int b;
158 v &= 0x3f;
159 b = v & 1;
160 return (v << 2) | (b << 1) | b;
161 }
163 void vga_common_init(VGAState *s, DisplayState *ds, uint8_t *vga_ram_base,
164 unsigned long vga_ram_offset, int vga_ram_size);
165 uint32_t vga_mem_readb(void *opaque, target_phys_addr_t addr);
166 void vga_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val);
167 void vga_invalidate_scanlines(VGAState *s, int y1, int y2);
169 void vga_draw_cursor_line_8(uint8_t *d1, const uint8_t *src1,
170 int poffset, int w,
171 unsigned int color0, unsigned int color1,
172 unsigned int color_xor);
173 void vga_draw_cursor_line_16(uint8_t *d1, const uint8_t *src1,
174 int poffset, int w,
175 unsigned int color0, unsigned int color1,
176 unsigned int color_xor);
177 void vga_draw_cursor_line_32(uint8_t *d1, const uint8_t *src1,
178 int poffset, int w,
179 unsigned int color0, unsigned int color1,
180 unsigned int color_xor);
182 void *vga_update_vram(VGAState *s, void *vga_ram_base, int vga_ram_size);
183 extern const uint8_t sr_mask[8];
184 extern const uint8_t gr_mask[16];