ia64/xen-unstable

view tools/ioemu/hw/vga.c @ 17571:b6aa55ca599e

shadow: track video RAM dirty bits

This adds a new HVM op that enables tracking dirty bits of a range of
video RAM. The idea is to optimize just for the most common case
(only one guest mapping, with sometimes some temporary other
mappings), which permits to keep the overhead on shadow as low as
possible.

Signed-off-by: Samuel Thibault <samuel.thibault@eu.citrix.com>
author Keir Fraser <keir.fraser@citrix.com>
date Fri May 02 15:08:27 2008 +0100 (2008-05-02)
parents e309f53f3f83
children 638811f870ba
line source
1 /*
2 * QEMU VGA Emulator.
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "vl.h"
25 #include "vga_int.h"
27 //#define DEBUG_VGA
28 //#define DEBUG_VGA_MEM
29 //#define DEBUG_VGA_REG
31 //#define DEBUG_BOCHS_VBE
33 /* force some bits to zero */
34 const uint8_t sr_mask[8] = {
35 (uint8_t)~0xfc,
36 (uint8_t)~0xc2,
37 (uint8_t)~0xf0,
38 (uint8_t)~0xc0,
39 (uint8_t)~0xf1,
40 (uint8_t)~0xff,
41 (uint8_t)~0xff,
42 (uint8_t)~0x00,
43 };
45 const uint8_t gr_mask[16] = {
46 (uint8_t)~0xf0, /* 0x00 */
47 (uint8_t)~0xf0, /* 0x01 */
48 (uint8_t)~0xf0, /* 0x02 */
49 (uint8_t)~0xe0, /* 0x03 */
50 (uint8_t)~0xfc, /* 0x04 */
51 (uint8_t)~0x84, /* 0x05 */
52 (uint8_t)~0xf0, /* 0x06 */
53 (uint8_t)~0xf0, /* 0x07 */
54 (uint8_t)~0x00, /* 0x08 */
55 (uint8_t)~0xff, /* 0x09 */
56 (uint8_t)~0xff, /* 0x0a */
57 (uint8_t)~0xff, /* 0x0b */
58 (uint8_t)~0xff, /* 0x0c */
59 (uint8_t)~0xff, /* 0x0d */
60 (uint8_t)~0xff, /* 0x0e */
61 (uint8_t)~0xff, /* 0x0f */
62 };
64 #define cbswap_32(__x) \
65 ((uint32_t)( \
66 (((uint32_t)(__x) & (uint32_t)0x000000ffUL) << 24) | \
67 (((uint32_t)(__x) & (uint32_t)0x0000ff00UL) << 8) | \
68 (((uint32_t)(__x) & (uint32_t)0x00ff0000UL) >> 8) | \
69 (((uint32_t)(__x) & (uint32_t)0xff000000UL) >> 24) ))
71 #ifdef WORDS_BIGENDIAN
72 #define PAT(x) cbswap_32(x)
73 #else
74 #define PAT(x) (x)
75 #endif
77 #ifdef WORDS_BIGENDIAN
78 #define BIG 1
79 #else
80 #define BIG 0
81 #endif
83 #ifdef WORDS_BIGENDIAN
84 #define GET_PLANE(data, p) (((data) >> (24 - (p) * 8)) & 0xff)
85 #else
86 #define GET_PLANE(data, p) (((data) >> ((p) * 8)) & 0xff)
87 #endif
89 static const uint32_t mask16[16] = {
90 PAT(0x00000000),
91 PAT(0x000000ff),
92 PAT(0x0000ff00),
93 PAT(0x0000ffff),
94 PAT(0x00ff0000),
95 PAT(0x00ff00ff),
96 PAT(0x00ffff00),
97 PAT(0x00ffffff),
98 PAT(0xff000000),
99 PAT(0xff0000ff),
100 PAT(0xff00ff00),
101 PAT(0xff00ffff),
102 PAT(0xffff0000),
103 PAT(0xffff00ff),
104 PAT(0xffffff00),
105 PAT(0xffffffff),
106 };
108 #undef PAT
110 #ifdef WORDS_BIGENDIAN
111 #define PAT(x) (x)
112 #else
113 #define PAT(x) cbswap_32(x)
114 #endif
116 static const uint32_t dmask16[16] = {
117 PAT(0x00000000),
118 PAT(0x000000ff),
119 PAT(0x0000ff00),
120 PAT(0x0000ffff),
121 PAT(0x00ff0000),
122 PAT(0x00ff00ff),
123 PAT(0x00ffff00),
124 PAT(0x00ffffff),
125 PAT(0xff000000),
126 PAT(0xff0000ff),
127 PAT(0xff00ff00),
128 PAT(0xff00ffff),
129 PAT(0xffff0000),
130 PAT(0xffff00ff),
131 PAT(0xffffff00),
132 PAT(0xffffffff),
133 };
135 static const uint32_t dmask4[4] = {
136 PAT(0x00000000),
137 PAT(0x0000ffff),
138 PAT(0xffff0000),
139 PAT(0xffffffff),
140 };
142 static uint32_t expand4[256];
143 static uint16_t expand2[256];
144 static uint8_t expand4to8[16];
146 static void vga_screen_dump(void *opaque, const char *filename);
148 static uint32_t vga_ioport_read(void *opaque, uint32_t addr)
149 {
150 VGAState *s = opaque;
151 int val, index;
153 /* check port range access depending on color/monochrome mode */
154 if ((addr >= 0x3b0 && addr <= 0x3bf && (s->msr & MSR_COLOR_EMULATION)) ||
155 (addr >= 0x3d0 && addr <= 0x3df && !(s->msr & MSR_COLOR_EMULATION))) {
156 val = 0xff;
157 } else {
158 switch(addr) {
159 case 0x3c0:
160 if (s->ar_flip_flop == 0) {
161 val = s->ar_index;
162 } else {
163 val = 0;
164 }
165 break;
166 case 0x3c1:
167 index = s->ar_index & 0x1f;
168 if (index < 21)
169 val = s->ar[index];
170 else
171 val = 0;
172 break;
173 case 0x3c2:
174 val = s->st00;
175 break;
176 case 0x3c4:
177 val = s->sr_index;
178 break;
179 case 0x3c5:
180 val = s->sr[s->sr_index];
181 #ifdef DEBUG_VGA_REG
182 printf("vga: read SR%x = 0x%02x\n", s->sr_index, val);
183 #endif
184 break;
185 case 0x3c7:
186 val = s->dac_state;
187 break;
188 case 0x3c8:
189 val = s->dac_write_index;
190 break;
191 case 0x3c9:
192 val = s->palette[s->dac_read_index * 3 + s->dac_sub_index];
193 if (++s->dac_sub_index == 3) {
194 s->dac_sub_index = 0;
195 s->dac_read_index++;
196 }
197 break;
198 case 0x3ca:
199 val = s->fcr;
200 break;
201 case 0x3cc:
202 val = s->msr;
203 break;
204 case 0x3ce:
205 val = s->gr_index;
206 break;
207 case 0x3cf:
208 val = s->gr[s->gr_index];
209 #ifdef DEBUG_VGA_REG
210 printf("vga: read GR%x = 0x%02x\n", s->gr_index, val);
211 #endif
212 break;
213 case 0x3b4:
214 case 0x3d4:
215 val = s->cr_index;
216 break;
217 case 0x3b5:
218 case 0x3d5:
219 val = s->cr[s->cr_index];
220 #ifdef DEBUG_VGA_REG
221 printf("vga: read CR%x = 0x%02x\n", s->cr_index, val);
222 #endif
223 break;
224 case 0x3ba:
225 case 0x3da:
226 /* just toggle to fool polling */
227 s->st01 ^= ST01_V_RETRACE | ST01_DISP_ENABLE;
228 val = s->st01;
229 s->ar_flip_flop = 0;
230 break;
231 default:
232 val = 0x00;
233 break;
234 }
235 }
236 #if defined(DEBUG_VGA)
237 printf("VGA: read addr=0x%04x data=0x%02x\n", addr, val);
238 #endif
239 return val;
240 }
242 static void vga_ioport_write(void *opaque, uint32_t addr, uint32_t val)
243 {
244 VGAState *s = opaque;
245 int index;
247 /* check port range access depending on color/monochrome mode */
248 if ((addr >= 0x3b0 && addr <= 0x3bf && (s->msr & MSR_COLOR_EMULATION)) ||
249 (addr >= 0x3d0 && addr <= 0x3df && !(s->msr & MSR_COLOR_EMULATION)))
250 return;
252 #ifdef DEBUG_VGA
253 printf("VGA: write addr=0x%04x data=0x%02x\n", addr, val);
254 #endif
256 switch(addr) {
257 case 0x3c0:
258 if (s->ar_flip_flop == 0) {
259 val &= 0x3f;
260 s->ar_index = val;
261 } else {
262 index = s->ar_index & 0x1f;
263 switch(index) {
264 case 0x00 ... 0x0f:
265 s->ar[index] = val & 0x3f;
266 break;
267 case 0x10:
268 s->ar[index] = val & ~0x10;
269 break;
270 case 0x11:
271 s->ar[index] = val;
272 break;
273 case 0x12:
274 s->ar[index] = val & ~0xc0;
275 break;
276 case 0x13:
277 s->ar[index] = val & ~0xf0;
278 break;
279 case 0x14:
280 s->ar[index] = val & ~0xf0;
281 break;
282 default:
283 break;
284 }
285 }
286 s->ar_flip_flop ^= 1;
287 break;
288 case 0x3c2:
289 s->msr = val & ~0x10;
290 break;
291 case 0x3c4:
292 s->sr_index = val & 7;
293 break;
294 case 0x3c5:
295 #ifdef DEBUG_VGA_REG
296 printf("vga: write SR%x = 0x%02x\n", s->sr_index, val);
297 #endif
298 s->sr[s->sr_index] = val & sr_mask[s->sr_index];
299 break;
300 case 0x3c7:
301 s->dac_read_index = val;
302 s->dac_sub_index = 0;
303 s->dac_state = 3;
304 break;
305 case 0x3c8:
306 s->dac_write_index = val;
307 s->dac_sub_index = 0;
308 s->dac_state = 0;
309 break;
310 case 0x3c9:
311 s->dac_cache[s->dac_sub_index] = val;
312 if (++s->dac_sub_index == 3) {
313 memcpy(&s->palette[s->dac_write_index * 3], s->dac_cache, 3);
314 s->dac_sub_index = 0;
315 s->dac_write_index++;
316 }
317 break;
318 case 0x3ce:
319 s->gr_index = val & 0x0f;
320 break;
321 case 0x3cf:
322 #ifdef DEBUG_VGA_REG
323 printf("vga: write GR%x = 0x%02x\n", s->gr_index, val);
324 #endif
325 s->gr[s->gr_index] = val & gr_mask[s->gr_index];
326 break;
327 case 0x3b4:
328 case 0x3d4:
329 s->cr_index = val;
330 break;
331 case 0x3b5:
332 case 0x3d5:
333 #ifdef DEBUG_VGA_REG
334 printf("vga: write CR%x = 0x%02x\n", s->cr_index, val);
335 #endif
336 /* handle CR0-7 protection */
337 if ((s->cr[0x11] & 0x80) && s->cr_index <= 7) {
338 /* can always write bit 4 of CR7 */
339 if (s->cr_index == 7)
340 s->cr[7] = (s->cr[7] & ~0x10) | (val & 0x10);
341 return;
342 }
343 switch(s->cr_index) {
344 case 0x01: /* horizontal display end */
345 case 0x07:
346 case 0x09:
347 case 0x0c:
348 case 0x0d:
349 case 0x12: /* veritcal display end */
350 s->cr[s->cr_index] = val;
351 break;
352 default:
353 s->cr[s->cr_index] = val;
354 break;
355 }
356 break;
357 case 0x3ba:
358 case 0x3da:
359 s->fcr = val & 0x10;
360 break;
361 }
362 }
364 #ifdef CONFIG_BOCHS_VBE
365 static uint32_t vbe_ioport_read_index(void *opaque, uint32_t addr)
366 {
367 VGAState *s = opaque;
368 uint32_t val;
369 val = s->vbe_index;
370 return val;
371 }
373 static uint32_t vbe_ioport_read_data(void *opaque, uint32_t addr)
374 {
375 VGAState *s = opaque;
376 uint32_t val;
378 if (s->vbe_index <= VBE_DISPI_INDEX_NB) {
379 if (s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_GETCAPS) {
380 switch(s->vbe_index) {
381 /* XXX: do not hardcode ? */
382 case VBE_DISPI_INDEX_XRES:
383 val = VBE_DISPI_MAX_XRES;
384 break;
385 case VBE_DISPI_INDEX_YRES:
386 val = VBE_DISPI_MAX_YRES;
387 break;
388 case VBE_DISPI_INDEX_BPP:
389 val = VBE_DISPI_MAX_BPP;
390 break;
391 default:
392 val = s->vbe_regs[s->vbe_index];
393 break;
394 }
395 } else {
396 val = s->vbe_regs[s->vbe_index];
397 }
398 } else {
399 val = 0;
400 }
401 #ifdef DEBUG_BOCHS_VBE
402 printf("VBE: read index=0x%x val=0x%x\n", s->vbe_index, val);
403 #endif
404 return val;
405 }
407 static void vbe_ioport_write_index(void *opaque, uint32_t addr, uint32_t val)
408 {
409 VGAState *s = opaque;
410 s->vbe_index = val;
411 }
413 static void vbe_ioport_write_data(void *opaque, uint32_t addr, uint32_t val)
414 {
415 VGAState *s = opaque;
417 if (s->vbe_index <= VBE_DISPI_INDEX_NB) {
418 #ifdef DEBUG_BOCHS_VBE
419 printf("VBE: write index=0x%x val=0x%x\n", s->vbe_index, val);
420 #endif
421 switch(s->vbe_index) {
422 case VBE_DISPI_INDEX_ID:
423 if (val == VBE_DISPI_ID0 ||
424 val == VBE_DISPI_ID1 ||
425 val == VBE_DISPI_ID2 ||
426 val == VBE_DISPI_ID3 ||
427 val == VBE_DISPI_ID4) {
428 s->vbe_regs[s->vbe_index] = val;
429 }
430 break;
431 case VBE_DISPI_INDEX_XRES:
432 if ((val <= VBE_DISPI_MAX_XRES) && ((val & 7) == 0)) {
433 s->vbe_regs[s->vbe_index] = val;
434 }
435 break;
436 case VBE_DISPI_INDEX_YRES:
437 if (val <= VBE_DISPI_MAX_YRES) {
438 s->vbe_regs[s->vbe_index] = val;
439 }
440 break;
441 case VBE_DISPI_INDEX_BPP:
442 if (val == 0)
443 val = 8;
444 if (val == 4 || val == 8 || val == 15 ||
445 val == 16 || val == 24 || val == 32) {
446 s->vbe_regs[s->vbe_index] = val;
447 }
448 break;
449 case VBE_DISPI_INDEX_BANK:
450 if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4) {
451 val &= (s->vbe_bank_mask >> 2);
452 } else {
453 val &= s->vbe_bank_mask;
454 }
455 s->vbe_regs[s->vbe_index] = val;
456 s->bank_offset = (val << 16);
457 break;
458 case VBE_DISPI_INDEX_ENABLE:
459 if ((val & VBE_DISPI_ENABLED) &&
460 !(s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED)) {
461 int h, shift_control;
463 s->vbe_regs[VBE_DISPI_INDEX_VIRT_WIDTH] =
464 s->vbe_regs[VBE_DISPI_INDEX_XRES];
465 s->vbe_regs[VBE_DISPI_INDEX_VIRT_HEIGHT] =
466 s->vbe_regs[VBE_DISPI_INDEX_YRES];
467 s->vbe_regs[VBE_DISPI_INDEX_X_OFFSET] = 0;
468 s->vbe_regs[VBE_DISPI_INDEX_Y_OFFSET] = 0;
470 if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4)
471 s->vbe_line_offset = s->vbe_regs[VBE_DISPI_INDEX_XRES] >> 1;
472 else
473 s->vbe_line_offset = s->vbe_regs[VBE_DISPI_INDEX_XRES] *
474 ((s->vbe_regs[VBE_DISPI_INDEX_BPP] + 7) >> 3);
475 s->vbe_start_addr = 0;
477 /* clear the screen (should be done in BIOS) */
478 if (!(val & VBE_DISPI_NOCLEARMEM)) {
479 memset(s->vram_ptr, 0,
480 s->vbe_regs[VBE_DISPI_INDEX_YRES] * s->vbe_line_offset);
481 }
483 /* we initialize the VGA graphic mode (should be done
484 in BIOS) */
485 s->gr[0x06] = (s->gr[0x06] & ~0x0c) | 0x05; /* graphic mode + memory map 1 */
486 s->cr[0x17] |= 3; /* no CGA modes */
487 s->cr[0x13] = s->vbe_line_offset >> 3;
488 /* width */
489 s->cr[0x01] = (s->vbe_regs[VBE_DISPI_INDEX_XRES] >> 3) - 1;
490 /* height (only meaningful if < 1024) */
491 h = s->vbe_regs[VBE_DISPI_INDEX_YRES] - 1;
492 s->cr[0x12] = h;
493 s->cr[0x07] = (s->cr[0x07] & ~0x42) |
494 ((h >> 7) & 0x02) | ((h >> 3) & 0x40);
495 /* line compare to 1023 */
496 s->cr[0x18] = 0xff;
497 s->cr[0x07] |= 0x10;
498 s->cr[0x09] |= 0x40;
500 if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4) {
501 shift_control = 0;
502 s->sr[0x01] &= ~8; /* no double line */
503 } else {
504 shift_control = 2;
505 s->sr[4] |= 0x08; /* set chain 4 mode */
506 s->sr[2] |= 0x0f; /* activate all planes */
507 }
508 s->gr[0x05] = (s->gr[0x05] & ~0x60) | (shift_control << 5);
509 s->cr[0x09] &= ~0x9f; /* no double scan */
510 } else {
511 /* XXX: the bios should do that */
512 s->bank_offset = 0;
513 }
514 s->dac_8bit = (val & VBE_DISPI_8BIT_DAC) > 0;
515 s->vbe_regs[s->vbe_index] = val;
516 break;
517 case VBE_DISPI_INDEX_VIRT_WIDTH:
518 {
519 int w, h, line_offset;
521 if (val < s->vbe_regs[VBE_DISPI_INDEX_XRES])
522 return;
523 w = val;
524 if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4)
525 line_offset = w >> 1;
526 else
527 line_offset = w * ((s->vbe_regs[VBE_DISPI_INDEX_BPP] + 7) >> 3);
528 h = s->vram_size / line_offset;
529 /* XXX: support weird bochs semantics ? */
530 if (h < s->vbe_regs[VBE_DISPI_INDEX_YRES])
531 return;
532 s->vbe_regs[VBE_DISPI_INDEX_VIRT_WIDTH] = w;
533 s->vbe_regs[VBE_DISPI_INDEX_VIRT_HEIGHT] = h;
534 s->vbe_line_offset = line_offset;
535 }
536 break;
537 case VBE_DISPI_INDEX_X_OFFSET:
538 case VBE_DISPI_INDEX_Y_OFFSET:
539 {
540 int x;
541 s->vbe_regs[s->vbe_index] = val;
542 s->vbe_start_addr = s->vbe_line_offset * s->vbe_regs[VBE_DISPI_INDEX_Y_OFFSET];
543 x = s->vbe_regs[VBE_DISPI_INDEX_X_OFFSET];
544 if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4)
545 s->vbe_start_addr += x >> 1;
546 else
547 s->vbe_start_addr += x * ((s->vbe_regs[VBE_DISPI_INDEX_BPP] + 7) >> 3);
548 s->vbe_start_addr >>= 2;
549 }
550 break;
551 default:
552 break;
553 }
554 }
555 }
556 #endif
558 /* called for accesses between 0xa0000 and 0xc0000 */
559 uint32_t vga_mem_readb(void *opaque, target_phys_addr_t addr)
560 {
561 VGAState *s = opaque;
562 int memory_map_mode, plane;
563 uint32_t ret;
565 /* convert to VGA memory offset */
566 memory_map_mode = (s->gr[6] >> 2) & 3;
567 addr &= 0x1ffff;
568 switch(memory_map_mode) {
569 case 0:
570 break;
571 case 1:
572 if (addr >= 0x10000)
573 return 0xff;
574 addr += s->bank_offset;
575 break;
576 case 2:
577 addr -= 0x10000;
578 if (addr >= 0x8000)
579 return 0xff;
580 break;
581 default:
582 case 3:
583 addr -= 0x18000;
584 if (addr >= 0x8000)
585 return 0xff;
586 break;
587 }
589 if (s->sr[4] & 0x08) {
590 /* chain 4 mode : simplest access */
591 ret = s->vram_ptr[addr];
592 } else if (s->gr[5] & 0x10) {
593 /* odd/even mode (aka text mode mapping) */
594 plane = (s->gr[4] & 2) | (addr & 1);
595 ret = s->vram_ptr[((addr & ~1) << 1) | plane];
596 } else {
597 /* standard VGA latched access */
598 s->latch = ((uint32_t *)s->vram_ptr)[addr];
600 if (!(s->gr[5] & 0x08)) {
601 /* read mode 0 */
602 plane = s->gr[4];
603 ret = GET_PLANE(s->latch, plane);
604 } else {
605 /* read mode 1 */
606 ret = (s->latch ^ mask16[s->gr[2]]) & mask16[s->gr[7]];
607 ret |= ret >> 16;
608 ret |= ret >> 8;
609 ret = (~ret) & 0xff;
610 }
611 }
612 return ret;
613 }
615 static uint32_t vga_mem_readw(void *opaque, target_phys_addr_t addr)
616 {
617 uint32_t v;
618 #ifdef TARGET_WORDS_BIGENDIAN
619 v = vga_mem_readb(opaque, addr) << 8;
620 v |= vga_mem_readb(opaque, addr + 1);
621 #else
622 v = vga_mem_readb(opaque, addr);
623 v |= vga_mem_readb(opaque, addr + 1) << 8;
624 #endif
625 return v;
626 }
628 static uint32_t vga_mem_readl(void *opaque, target_phys_addr_t addr)
629 {
630 uint32_t v;
631 #ifdef TARGET_WORDS_BIGENDIAN
632 v = vga_mem_readb(opaque, addr) << 24;
633 v |= vga_mem_readb(opaque, addr + 1) << 16;
634 v |= vga_mem_readb(opaque, addr + 2) << 8;
635 v |= vga_mem_readb(opaque, addr + 3);
636 #else
637 v = vga_mem_readb(opaque, addr);
638 v |= vga_mem_readb(opaque, addr + 1) << 8;
639 v |= vga_mem_readb(opaque, addr + 2) << 16;
640 v |= vga_mem_readb(opaque, addr + 3) << 24;
641 #endif
642 return v;
643 }
645 /* called for accesses between 0xa0000 and 0xc0000 */
646 void vga_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
647 {
648 VGAState *s = opaque;
649 int memory_map_mode, plane, write_mode, b, func_select, mask;
650 uint32_t write_mask, bit_mask, set_mask;
652 #ifdef DEBUG_VGA_MEM
653 printf("vga: [0x%x] = 0x%02x\n", addr, val);
654 #endif
655 /* convert to VGA memory offset */
656 memory_map_mode = (s->gr[6] >> 2) & 3;
657 addr &= 0x1ffff;
658 switch(memory_map_mode) {
659 case 0:
660 break;
661 case 1:
662 if (addr >= 0x10000)
663 return;
664 addr += s->bank_offset;
665 break;
666 case 2:
667 addr -= 0x10000;
668 if (addr >= 0x8000)
669 return;
670 break;
671 default:
672 case 3:
673 addr -= 0x18000;
674 if (addr >= 0x8000)
675 return;
676 break;
677 }
679 if (s->sr[4] & 0x08) {
680 /* chain 4 mode : simplest access */
681 plane = addr & 3;
682 mask = (1 << plane);
683 if (s->sr[2] & mask) {
684 s->vram_ptr[addr] = val;
685 #ifdef DEBUG_VGA_MEM
686 printf("vga: chain4: [0x%x]\n", addr);
687 #endif
688 s->plane_updated |= mask; /* only used to detect font change */
689 cpu_physical_memory_set_dirty(s->vram_offset + addr);
690 }
691 } else if (s->gr[5] & 0x10) {
692 /* odd/even mode (aka text mode mapping) */
693 plane = (s->gr[4] & 2) | (addr & 1);
694 mask = (1 << plane);
695 if (s->sr[2] & mask) {
696 addr = ((addr & ~1) << 1) | plane;
697 s->vram_ptr[addr] = val;
698 #ifdef DEBUG_VGA_MEM
699 printf("vga: odd/even: [0x%x]\n", addr);
700 #endif
701 s->plane_updated |= mask; /* only used to detect font change */
702 cpu_physical_memory_set_dirty(s->vram_offset + addr);
703 }
704 } else {
705 /* standard VGA latched access */
706 write_mode = s->gr[5] & 3;
707 switch(write_mode) {
708 default:
709 case 0:
710 /* rotate */
711 b = s->gr[3] & 7;
712 val = ((val >> b) | (val << (8 - b))) & 0xff;
713 val |= val << 8;
714 val |= val << 16;
716 /* apply set/reset mask */
717 set_mask = mask16[s->gr[1]];
718 val = (val & ~set_mask) | (mask16[s->gr[0]] & set_mask);
719 bit_mask = s->gr[8];
720 break;
721 case 1:
722 val = s->latch;
723 goto do_write;
724 case 2:
725 val = mask16[val & 0x0f];
726 bit_mask = s->gr[8];
727 break;
728 case 3:
729 /* rotate */
730 b = s->gr[3] & 7;
731 val = (val >> b) | (val << (8 - b));
733 bit_mask = s->gr[8] & val;
734 val = mask16[s->gr[0]];
735 break;
736 }
738 /* apply logical operation */
739 func_select = s->gr[3] >> 3;
740 switch(func_select) {
741 case 0:
742 default:
743 /* nothing to do */
744 break;
745 case 1:
746 /* and */
747 val &= s->latch;
748 break;
749 case 2:
750 /* or */
751 val |= s->latch;
752 break;
753 case 3:
754 /* xor */
755 val ^= s->latch;
756 break;
757 }
759 /* apply bit mask */
760 bit_mask |= bit_mask << 8;
761 bit_mask |= bit_mask << 16;
762 val = (val & bit_mask) | (s->latch & ~bit_mask);
764 do_write:
765 /* mask data according to sr[2] */
766 mask = s->sr[2];
767 s->plane_updated |= mask; /* only used to detect font change */
768 write_mask = mask16[mask];
769 ((uint32_t *)s->vram_ptr)[addr] =
770 (((uint32_t *)s->vram_ptr)[addr] & ~write_mask) |
771 (val & write_mask);
772 #ifdef DEBUG_VGA_MEM
773 printf("vga: latch: [0x%x] mask=0x%08x val=0x%08x\n",
774 addr * 4, write_mask, val);
775 #endif
776 cpu_physical_memory_set_dirty(s->vram_offset + (addr << 2));
777 }
778 }
780 static void vga_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
781 {
782 #ifdef TARGET_WORDS_BIGENDIAN
783 vga_mem_writeb(opaque, addr, (val >> 8) & 0xff);
784 vga_mem_writeb(opaque, addr + 1, val & 0xff);
785 #else
786 vga_mem_writeb(opaque, addr, val & 0xff);
787 vga_mem_writeb(opaque, addr + 1, (val >> 8) & 0xff);
788 #endif
789 }
791 static void vga_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
792 {
793 #ifdef TARGET_WORDS_BIGENDIAN
794 vga_mem_writeb(opaque, addr, (val >> 24) & 0xff);
795 vga_mem_writeb(opaque, addr + 1, (val >> 16) & 0xff);
796 vga_mem_writeb(opaque, addr + 2, (val >> 8) & 0xff);
797 vga_mem_writeb(opaque, addr + 3, val & 0xff);
798 #else
799 vga_mem_writeb(opaque, addr, val & 0xff);
800 vga_mem_writeb(opaque, addr + 1, (val >> 8) & 0xff);
801 vga_mem_writeb(opaque, addr + 2, (val >> 16) & 0xff);
802 vga_mem_writeb(opaque, addr + 3, (val >> 24) & 0xff);
803 #endif
804 }
806 typedef void vga_draw_glyph8_func(uint8_t *d, int linesize,
807 const uint8_t *font_ptr, int h,
808 uint32_t fgcol, uint32_t bgcol);
809 typedef void vga_draw_glyph9_func(uint8_t *d, int linesize,
810 const uint8_t *font_ptr, int h,
811 uint32_t fgcol, uint32_t bgcol, int dup9);
812 typedef void vga_draw_line_func(VGAState *s1, uint8_t *d,
813 const uint8_t *s, int width);
815 static inline unsigned int rgb_to_pixel8(unsigned int r, unsigned int g, unsigned b)
816 {
817 return ((r >> 5) << 5) | ((g >> 5) << 2) | (b >> 6);
818 }
820 static inline unsigned int rgb_to_pixel15(unsigned int r, unsigned int g, unsigned b)
821 {
822 return ((r >> 3) << 10) | ((g >> 3) << 5) | (b >> 3);
823 }
825 static inline unsigned int rgb_to_pixel16(unsigned int r, unsigned int g, unsigned b)
826 {
827 return ((r >> 3) << 11) | ((g >> 2) << 5) | (b >> 3);
828 }
830 static inline unsigned int rgb_to_pixel32(unsigned int r, unsigned int g, unsigned b)
831 {
832 return (r << 16) | (g << 8) | b;
833 }
835 static inline unsigned int rgb_to_pixel32bgr(unsigned int r, unsigned int g, unsigned b)
836 {
837 return (b << 16) | (g << 8) | r;
838 }
840 #define DEPTH 8
841 #include "vga_template.h"
843 #define DEPTH 15
844 #include "vga_template.h"
846 #define DEPTH 16
847 #include "vga_template.h"
849 #define DEPTH 32
850 #include "vga_template.h"
852 #define BGR_FORMAT
853 #define DEPTH 32
854 #include "vga_template.h"
856 static unsigned int rgb_to_pixel8_dup(unsigned int r, unsigned int g, unsigned b)
857 {
858 unsigned int col;
859 col = rgb_to_pixel8(r, g, b);
860 col |= col << 8;
861 col |= col << 16;
862 return col;
863 }
865 static unsigned int rgb_to_pixel15_dup(unsigned int r, unsigned int g, unsigned b)
866 {
867 unsigned int col;
868 col = rgb_to_pixel15(r, g, b);
869 col |= col << 16;
870 return col;
871 }
873 static unsigned int rgb_to_pixel16_dup(unsigned int r, unsigned int g, unsigned b)
874 {
875 unsigned int col;
876 col = rgb_to_pixel16(r, g, b);
877 col |= col << 16;
878 return col;
879 }
881 static unsigned int rgb_to_pixel32_dup(unsigned int r, unsigned int g, unsigned b)
882 {
883 unsigned int col;
884 col = rgb_to_pixel32(r, g, b);
885 return col;
886 }
888 static unsigned int rgb_to_pixel32bgr_dup(unsigned int r, unsigned int g, unsigned b)
889 {
890 unsigned int col;
891 col = rgb_to_pixel32bgr(r, g, b);
892 return col;
893 }
895 /* return true if the palette was modified */
896 static int update_palette16(VGAState *s)
897 {
898 int full_update, i;
899 uint32_t v, col, *palette;
901 full_update = 0;
902 palette = s->last_palette;
903 for(i = 0; i < 16; i++) {
904 v = s->ar[i];
905 if (s->ar[0x10] & 0x80)
906 v = ((s->ar[0x14] & 0xf) << 4) | (v & 0xf);
907 else
908 v = ((s->ar[0x14] & 0xc) << 4) | (v & 0x3f);
909 v = v * 3;
910 col = s->rgb_to_pixel(c6_to_8(s->palette[v]),
911 c6_to_8(s->palette[v + 1]),
912 c6_to_8(s->palette[v + 2]));
913 if (col != palette[i]) {
914 full_update = 1;
915 palette[i] = col;
916 }
917 }
918 return full_update;
919 }
921 /* return true if the palette was modified */
922 static int update_palette256(VGAState *s)
923 {
924 int full_update, i;
925 uint32_t v, col, *palette;
927 full_update = 0;
928 palette = s->last_palette;
929 v = 0;
930 for(i = 0; i < 256; i++) {
931 if (s->dac_8bit) {
932 col = s->rgb_to_pixel(s->palette[v],
933 s->palette[v + 1],
934 s->palette[v + 2]);
935 } else {
936 col = s->rgb_to_pixel(c6_to_8(s->palette[v]),
937 c6_to_8(s->palette[v + 1]),
938 c6_to_8(s->palette[v + 2]));
939 }
940 if (col != palette[i]) {
941 full_update = 1;
942 palette[i] = col;
943 }
944 v += 3;
945 }
946 return full_update;
947 }
949 static void vga_get_offsets(VGAState *s,
950 uint32_t *pline_offset,
951 uint32_t *pstart_addr,
952 uint32_t *pline_compare)
953 {
954 uint32_t start_addr, line_offset, line_compare;
955 #ifdef CONFIG_BOCHS_VBE
956 if (s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED) {
957 line_offset = s->vbe_line_offset;
958 start_addr = s->vbe_start_addr;
959 line_compare = 65535;
960 } else
961 #endif
962 {
963 /* compute line_offset in bytes */
964 line_offset = s->cr[0x13];
965 line_offset <<= 3;
967 /* starting address */
968 start_addr = s->cr[0x0d] | (s->cr[0x0c] << 8);
970 /* line compare */
971 line_compare = s->cr[0x18] |
972 ((s->cr[0x07] & 0x10) << 4) |
973 ((s->cr[0x09] & 0x40) << 3);
974 }
975 *pline_offset = line_offset;
976 *pstart_addr = start_addr;
977 *pline_compare = line_compare;
978 }
980 /* update start_addr and line_offset. Return TRUE if modified */
981 static int update_basic_params(VGAState *s)
982 {
983 int full_update;
984 uint32_t start_addr, line_offset, line_compare;
986 full_update = 0;
988 s->get_offsets(s, &line_offset, &start_addr, &line_compare);
990 if (line_offset != s->line_offset ||
991 start_addr != s->start_addr ||
992 line_compare != s->line_compare) {
993 s->line_offset = line_offset;
994 s->start_addr = start_addr;
995 s->line_compare = line_compare;
996 full_update = 1;
997 }
998 return full_update;
999 }
1001 #define NB_DEPTHS 5
1003 static inline int get_depth_index(DisplayState *s)
1005 switch(s->depth) {
1006 default:
1007 case 8:
1008 return 0;
1009 case 15:
1010 return 1;
1011 case 16:
1012 return 2;
1013 case 32:
1014 if (s->bgr)
1015 return 4;
1016 else
1017 return 3;
1021 static vga_draw_glyph8_func *vga_draw_glyph8_table[NB_DEPTHS] = {
1022 vga_draw_glyph8_8,
1023 vga_draw_glyph8_16,
1024 vga_draw_glyph8_16,
1025 vga_draw_glyph8_32,
1026 vga_draw_glyph8_32,
1027 };
1029 static vga_draw_glyph8_func *vga_draw_glyph16_table[NB_DEPTHS] = {
1030 vga_draw_glyph16_8,
1031 vga_draw_glyph16_16,
1032 vga_draw_glyph16_16,
1033 vga_draw_glyph16_32,
1034 vga_draw_glyph16_32,
1035 };
1037 static vga_draw_glyph9_func *vga_draw_glyph9_table[NB_DEPTHS] = {
1038 vga_draw_glyph9_8,
1039 vga_draw_glyph9_16,
1040 vga_draw_glyph9_16,
1041 vga_draw_glyph9_32,
1042 vga_draw_glyph9_32,
1043 };
1045 static const uint8_t cursor_glyph[32 * 4] = {
1046 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1047 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1048 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1049 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1050 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1051 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1052 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1053 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1054 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1055 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1056 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1057 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1058 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1059 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1060 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1061 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1062 };
1064 typedef unsigned int rgb_to_pixel_dup_func(unsigned int r, unsigned int g, unsigned b);
1066 static rgb_to_pixel_dup_func *rgb_to_pixel_dup_table[NB_DEPTHS];
1068 /*
1069 * Text mode update
1070 * Missing:
1071 * - double scan
1072 * - double width
1073 * - underline
1074 * - flashing
1075 */
1076 static void vga_draw_text(VGAState *s, int full_update)
1078 int cx, cy, cheight, cw, ch, cattr, height, width, ch_attr;
1079 int cx_min, cx_max, linesize, x_incr;
1080 uint32_t offset, fgcol, bgcol, v, cursor_offset;
1081 uint8_t *d1, *d, *src, *s1, *dest, *cursor_ptr;
1082 const uint8_t *font_ptr, *font_base[2];
1083 int dup9, line_offset, depth_index;
1084 uint32_t *palette;
1085 uint32_t *ch_attr_ptr;
1086 vga_draw_glyph8_func *vga_draw_glyph8;
1087 vga_draw_glyph9_func *vga_draw_glyph9;
1089 /* Disable dirty bit tracking */
1090 xc_hvm_track_dirty_vram(xc_handle, domid, 0, 0, NULL);
1092 if (s->ds->dpy_colourdepth != NULL && s->ds->depth != 0)
1093 s->ds->dpy_colourdepth(s->ds, 0);
1094 s->rgb_to_pixel =
1095 rgb_to_pixel_dup_table[get_depth_index(s->ds)];
1097 full_update |= update_palette16(s);
1098 palette = s->last_palette;
1100 /* compute font data address (in plane 2) */
1101 v = s->sr[3];
1102 offset = (((v >> 4) & 1) | ((v << 1) & 6)) * 8192 * 4 + 2;
1103 if (offset != s->font_offsets[0]) {
1104 s->font_offsets[0] = offset;
1105 full_update = 1;
1107 font_base[0] = s->vram_ptr + offset;
1109 offset = (((v >> 5) & 1) | ((v >> 1) & 6)) * 8192 * 4 + 2;
1110 font_base[1] = s->vram_ptr + offset;
1111 if (offset != s->font_offsets[1]) {
1112 s->font_offsets[1] = offset;
1113 full_update = 1;
1115 if (s->plane_updated & (1 << 2)) {
1116 /* if the plane 2 was modified since the last display, it
1117 indicates the font may have been modified */
1118 s->plane_updated = 0;
1119 full_update = 1;
1121 full_update |= update_basic_params(s);
1123 line_offset = s->line_offset;
1124 s1 = s->vram_ptr + (s->start_addr * 4);
1126 /* total width & height */
1127 cheight = (s->cr[9] & 0x1f) + 1;
1128 cw = 8;
1129 if (!(s->sr[1] & 0x01))
1130 cw = 9;
1131 if (s->sr[1] & 0x08)
1132 cw = 16; /* NOTE: no 18 pixel wide */
1133 x_incr = cw * ((s->ds->depth + 7) >> 3);
1134 width = (s->cr[0x01] + 1);
1135 if (s->cr[0x06] == 100) {
1136 /* ugly hack for CGA 160x100x16 - explain me the logic */
1137 height = 100;
1138 } else {
1139 height = s->cr[0x12] |
1140 ((s->cr[0x07] & 0x02) << 7) |
1141 ((s->cr[0x07] & 0x40) << 3);
1142 height = (height + 1) / cheight;
1144 if ((height * width) > CH_ATTR_SIZE) {
1145 /* better than nothing: exit if transient size is too big */
1146 return;
1149 if (width != s->last_width || height != s->last_height ||
1150 cw != s->last_cw || cheight != s->last_ch) {
1151 s->last_scr_width = width * cw;
1152 s->last_scr_height = height * cheight;
1153 dpy_resize(s->ds, s->last_scr_width, s->last_scr_height, s->last_scr_width * (s->ds->depth / 8));
1154 s->last_width = width;
1155 s->last_height = height;
1156 s->last_ch = cheight;
1157 s->last_cw = cw;
1158 full_update = 1;
1160 cursor_offset = ((s->cr[0x0e] << 8) | s->cr[0x0f]) - s->start_addr;
1161 if (cursor_offset != s->cursor_offset ||
1162 s->cr[0xa] != s->cursor_start ||
1163 s->cr[0xb] != s->cursor_end) {
1164 /* if the cursor position changed, we update the old and new
1165 chars */
1166 if (s->cursor_offset < CH_ATTR_SIZE)
1167 s->last_ch_attr[s->cursor_offset] = -1;
1168 if (cursor_offset < CH_ATTR_SIZE)
1169 s->last_ch_attr[cursor_offset] = -1;
1170 s->cursor_offset = cursor_offset;
1171 s->cursor_start = s->cr[0xa];
1172 s->cursor_end = s->cr[0xb];
1174 cursor_ptr = s->vram_ptr + (s->start_addr + cursor_offset) * 4;
1176 depth_index = get_depth_index(s->ds);
1177 if (cw == 16)
1178 vga_draw_glyph8 = vga_draw_glyph16_table[depth_index];
1179 else
1180 vga_draw_glyph8 = vga_draw_glyph8_table[depth_index];
1181 vga_draw_glyph9 = vga_draw_glyph9_table[depth_index];
1183 dest = s->ds->data;
1184 linesize = s->ds->linesize;
1185 ch_attr_ptr = s->last_ch_attr;
1186 for(cy = 0; cy < height; cy++) {
1187 d1 = dest;
1188 src = s1;
1189 cx_min = width;
1190 cx_max = -1;
1191 for(cx = 0; cx < width; cx++) {
1192 ch_attr = *(uint16_t *)src;
1193 if (full_update || ch_attr != *ch_attr_ptr) {
1194 if (cx < cx_min)
1195 cx_min = cx;
1196 if (cx > cx_max)
1197 cx_max = cx;
1198 *ch_attr_ptr = ch_attr;
1199 #ifdef WORDS_BIGENDIAN
1200 ch = ch_attr >> 8;
1201 cattr = ch_attr & 0xff;
1202 #else
1203 ch = ch_attr & 0xff;
1204 cattr = ch_attr >> 8;
1205 #endif
1206 font_ptr = font_base[(cattr >> 3) & 1];
1207 font_ptr += 32 * 4 * ch;
1208 bgcol = palette[cattr >> 4];
1209 fgcol = palette[cattr & 0x0f];
1210 if (cw != 9) {
1211 vga_draw_glyph8(d1, linesize,
1212 font_ptr, cheight, fgcol, bgcol);
1213 } else {
1214 dup9 = 0;
1215 if (ch >= 0xb0 && ch <= 0xdf && (s->ar[0x10] & 0x04))
1216 dup9 = 1;
1217 vga_draw_glyph9(d1, linesize,
1218 font_ptr, cheight, fgcol, bgcol, dup9);
1220 if (src == cursor_ptr &&
1221 !(s->cr[0x0a] & 0x20)) {
1222 int line_start, line_last, h;
1223 /* draw the cursor */
1224 line_start = s->cr[0x0a] & 0x1f;
1225 line_last = s->cr[0x0b] & 0x1f;
1226 /* XXX: check that */
1227 if (line_last > cheight - 1)
1228 line_last = cheight - 1;
1229 if (line_last >= line_start && line_start < cheight) {
1230 h = line_last - line_start + 1;
1231 d = d1 + linesize * line_start;
1232 if (cw != 9) {
1233 vga_draw_glyph8(d, linesize,
1234 cursor_glyph, h, fgcol, bgcol);
1235 } else {
1236 vga_draw_glyph9(d, linesize,
1237 cursor_glyph, h, fgcol, bgcol, 1);
1242 d1 += x_incr;
1243 src += 4;
1244 ch_attr_ptr++;
1246 if (cx_max != -1) {
1247 dpy_update(s->ds, cx_min * cw, cy * cheight,
1248 (cx_max - cx_min + 1) * cw, cheight);
1250 dest += linesize * cheight;
1251 s1 += line_offset;
1255 enum {
1256 VGA_DRAW_LINE2,
1257 VGA_DRAW_LINE2D2,
1258 VGA_DRAW_LINE4,
1259 VGA_DRAW_LINE4D2,
1260 VGA_DRAW_LINE8D2,
1261 VGA_DRAW_LINE8,
1262 VGA_DRAW_LINE15,
1263 VGA_DRAW_LINE16,
1264 VGA_DRAW_LINE24,
1265 VGA_DRAW_LINE32,
1266 VGA_DRAW_LINE_NB,
1267 };
1269 static vga_draw_line_func *vga_draw_line_table[NB_DEPTHS * VGA_DRAW_LINE_NB] = {
1270 vga_draw_line2_8,
1271 vga_draw_line2_16,
1272 vga_draw_line2_16,
1273 vga_draw_line2_32,
1274 vga_draw_line2_32,
1276 vga_draw_line2d2_8,
1277 vga_draw_line2d2_16,
1278 vga_draw_line2d2_16,
1279 vga_draw_line2d2_32,
1280 vga_draw_line2d2_32,
1282 vga_draw_line4_8,
1283 vga_draw_line4_16,
1284 vga_draw_line4_16,
1285 vga_draw_line4_32,
1286 vga_draw_line4_32,
1288 vga_draw_line4d2_8,
1289 vga_draw_line4d2_16,
1290 vga_draw_line4d2_16,
1291 vga_draw_line4d2_32,
1292 vga_draw_line4d2_32,
1294 vga_draw_line8d2_8,
1295 vga_draw_line8d2_16,
1296 vga_draw_line8d2_16,
1297 vga_draw_line8d2_32,
1298 vga_draw_line8d2_32,
1300 vga_draw_line8_8,
1301 vga_draw_line8_16,
1302 vga_draw_line8_16,
1303 vga_draw_line8_32,
1304 vga_draw_line8_32,
1306 vga_draw_line15_8,
1307 vga_draw_line15_15,
1308 vga_draw_line15_16,
1309 vga_draw_line15_32,
1310 vga_draw_line15_32bgr,
1312 vga_draw_line16_8,
1313 vga_draw_line16_15,
1314 vga_draw_line16_16,
1315 vga_draw_line16_32,
1316 vga_draw_line16_32bgr,
1318 vga_draw_line24_8,
1319 vga_draw_line24_15,
1320 vga_draw_line24_16,
1321 vga_draw_line24_32,
1322 vga_draw_line24_32bgr,
1324 vga_draw_line32_8,
1325 vga_draw_line32_15,
1326 vga_draw_line32_16,
1327 vga_draw_line32_32,
1328 vga_draw_line32_32bgr,
1329 };
1331 static rgb_to_pixel_dup_func *rgb_to_pixel_dup_table[NB_DEPTHS] = {
1332 rgb_to_pixel8_dup,
1333 rgb_to_pixel15_dup,
1334 rgb_to_pixel16_dup,
1335 rgb_to_pixel32_dup,
1336 rgb_to_pixel32bgr_dup,
1337 };
1339 static int vga_get_bpp(VGAState *s)
1341 int ret;
1342 #ifdef CONFIG_BOCHS_VBE
1343 if (s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED) {
1344 ret = s->vbe_regs[VBE_DISPI_INDEX_BPP];
1345 } else
1346 #endif
1348 ret = 0;
1350 return ret;
1353 static void vga_get_resolution(VGAState *s, int *pwidth, int *pheight)
1355 int width, height;
1357 #ifdef CONFIG_BOCHS_VBE
1358 if (s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED) {
1359 width = s->vbe_regs[VBE_DISPI_INDEX_XRES];
1360 height = s->vbe_regs[VBE_DISPI_INDEX_YRES];
1361 } else
1362 #endif
1364 width = (s->cr[0x01] + 1) * 8;
1365 height = s->cr[0x12] |
1366 ((s->cr[0x07] & 0x02) << 7) |
1367 ((s->cr[0x07] & 0x40) << 3);
1368 height = (height + 1);
1370 *pwidth = width;
1371 *pheight = height;
1374 void vga_invalidate_scanlines(VGAState *s, int y1, int y2)
1376 int y;
1377 if (y1 >= VGA_MAX_HEIGHT)
1378 return;
1379 if (y2 >= VGA_MAX_HEIGHT)
1380 y2 = VGA_MAX_HEIGHT;
1381 for(y = y1; y < y2; y++) {
1382 s->invalidated_y_table[y >> 5] |= 1 << (y & 0x1f);
1386 static inline int cmp_vram(VGAState *s, int offset, int n)
1388 long *vp, *sp;
1390 if (s->vram_shadow == NULL)
1391 return 1;
1392 vp = (long *)(s->vram_ptr + offset);
1393 sp = (long *)(s->vram_shadow + offset);
1394 while ((n -= sizeof(*vp)) >= 0) {
1395 if (*vp++ != *sp++) {
1396 memcpy(sp - 1, vp - 1, n + sizeof(*vp));
1397 return 1;
1400 return 0;
1403 #ifdef USE_SSE2
1405 #include <signal.h>
1406 #include <setjmp.h>
1407 #include <emmintrin.h>
1409 int sse2_ok = 1;
1411 static inline unsigned int cpuid_edx(unsigned int op)
1413 unsigned int eax, edx;
1415 #ifdef __x86_64__
1416 #define __bx "rbx"
1417 #else
1418 #define __bx "ebx"
1419 #endif
1420 __asm__("push %%"__bx"; cpuid; pop %%"__bx
1421 : "=a" (eax), "=d" (edx)
1422 : "0" (op)
1423 : "cx");
1424 #undef __bx
1426 return edx;
1429 jmp_buf sse_jbuf;
1431 void intr(int sig)
1433 sse2_ok = 0;
1434 longjmp(sse_jbuf, 1);
1437 void check_sse2(void)
1439 /* Check 1: What does CPUID say? */
1440 if ((cpuid_edx(1) & 0x4000000) == 0) {
1441 sse2_ok = 0;
1442 return;
1445 /* Check 2: Can we use SSE2 in anger? */
1446 signal(SIGILL, intr);
1447 if (setjmp(sse_jbuf) == 0)
1448 __asm__("xorps %xmm0,%xmm0\n");
1451 int vram_dirty(VGAState *s, int offset, int n)
1453 __m128i *sp, *vp;
1455 if (s->vram_shadow == NULL)
1456 return 1;
1457 if (sse2_ok == 0)
1458 return cmp_vram(s, offset, n);
1459 vp = (__m128i *)(s->vram_ptr + offset);
1460 sp = (__m128i *)(s->vram_shadow + offset);
1461 while ((n -= sizeof(*vp)) >= 0) {
1462 if (_mm_movemask_epi8(_mm_cmpeq_epi8(*sp, *vp)) != 0xffff) {
1463 while (n >= 0) {
1464 _mm_store_si128(sp++, _mm_load_si128(vp++));
1465 n -= sizeof(*vp);
1467 return 1;
1469 sp++;
1470 vp++;
1472 return 0;
1474 #else /* !USE_SSE2 */
1475 int vram_dirty(VGAState *s, int offset, int n)
1477 return cmp_vram(s, offset, n);
1480 void check_sse2(void)
1483 #endif /* !USE_SSE2 */
1485 /*
1486 * graphic modes
1487 */
1488 static void vga_draw_graphic(VGAState *s, int full_update)
1490 int y1, y, update, linesize, y_start, double_scan, mask, depth;
1491 int width, height, shift_control, line_offset, bwidth, ds_depth, bits;
1492 ram_addr_t page0, page1;
1493 int disp_width, multi_scan, multi_run;
1494 uint8_t *d;
1495 uint32_t v, addr1, addr;
1496 vga_draw_line_func *vga_draw_line;
1497 ram_addr_t page_min, page_max;
1499 full_update |= update_basic_params(s);
1501 s->get_resolution(s, &width, &height);
1502 disp_width = width;
1504 ds_depth = s->ds->depth;
1505 depth = s->get_bpp(s);
1506 if (s->ds->dpy_colourdepth != NULL &&
1507 (ds_depth != depth || !s->ds->shared_buf))
1508 s->ds->dpy_colourdepth(s->ds, depth);
1509 if (ds_depth != s->ds->depth) full_update = 1;
1511 s->rgb_to_pixel =
1512 rgb_to_pixel_dup_table[get_depth_index(s->ds)];
1514 shift_control = (s->gr[0x05] >> 5) & 3;
1515 double_scan = (s->cr[0x09] >> 7);
1516 if (shift_control != 1) {
1517 multi_scan = (((s->cr[0x09] & 0x1f) + 1) << double_scan) - 1;
1518 } else {
1519 /* in CGA modes, multi_scan is ignored */
1520 /* XXX: is it correct ? */
1521 multi_scan = double_scan;
1523 multi_run = multi_scan;
1524 if (shift_control != s->shift_control ||
1525 double_scan != s->double_scan) {
1526 full_update = 1;
1527 s->shift_control = shift_control;
1528 s->double_scan = double_scan;
1531 if (shift_control == 0) {
1532 full_update |= update_palette16(s);
1533 if (s->sr[0x01] & 8) {
1534 v = VGA_DRAW_LINE4D2;
1535 disp_width <<= 1;
1536 } else {
1537 v = VGA_DRAW_LINE4;
1539 bits = 4;
1540 } else if (shift_control == 1) {
1541 full_update |= update_palette16(s);
1542 if (s->sr[0x01] & 8) {
1543 v = VGA_DRAW_LINE2D2;
1544 disp_width <<= 1;
1545 } else {
1546 v = VGA_DRAW_LINE2;
1548 bits = 4;
1549 } else {
1550 switch(s->get_bpp(s)) {
1551 default:
1552 case 0:
1553 full_update |= update_palette256(s);
1554 v = VGA_DRAW_LINE8D2;
1555 bits = 4;
1556 break;
1557 case 8:
1558 full_update |= update_palette256(s);
1559 v = VGA_DRAW_LINE8;
1560 bits = 8;
1561 break;
1562 case 15:
1563 v = VGA_DRAW_LINE15;
1564 bits = 16;
1565 break;
1566 case 16:
1567 v = VGA_DRAW_LINE16;
1568 bits = 16;
1569 break;
1570 case 24:
1571 v = VGA_DRAW_LINE24;
1572 bits = 24;
1573 break;
1574 case 32:
1575 v = VGA_DRAW_LINE32;
1576 bits = 32;
1577 break;
1581 vga_draw_line = vga_draw_line_table[v * NB_DEPTHS + get_depth_index(s->ds)];
1582 if (s->line_offset != s->last_line_offset ||
1583 disp_width != s->last_width ||
1584 height != s->last_height) {
1585 dpy_resize(s->ds, disp_width, height, s->line_offset);
1586 s->last_scr_width = disp_width;
1587 s->last_scr_height = height;
1588 s->last_width = disp_width;
1589 s->last_height = height;
1590 s->last_line_offset = s->line_offset;
1591 full_update = 1;
1593 if (s->ds->shared_buf && (full_update || s->ds->data != s->vram_ptr + (s->start_addr * 4)))
1594 s->ds->dpy_setdata(s->ds, s->vram_ptr + (s->start_addr * 4));
1595 if (!s->ds->shared_buf && s->cursor_invalidate)
1596 s->cursor_invalidate(s);
1598 line_offset = s->line_offset;
1599 #if 0
1600 printf("w=%d h=%d v=%d line_offset=%d cr[0x09]=0x%02x cr[0x17]=0x%02x linecmp=%d sr[0x01]=0x%02x\n",
1601 width, height, v, line_offset, s->cr[9], s->cr[0x17], s->line_compare, s->sr[0x01]);
1602 #endif
1604 y = 0;
1606 if (height - 1 > s->line_compare || multi_run || (s->cr[0x17] & 3) != 3
1607 || !s->lfb_addr) {
1608 /* Tricky things happen, disable dirty bit tracking */
1609 xc_hvm_track_dirty_vram(xc_handle, domid, 0, 0, NULL);
1611 for ( ; y < s->vram_size; y += TARGET_PAGE_SIZE)
1612 if (vram_dirty(s, y, TARGET_PAGE_SIZE))
1613 cpu_physical_memory_set_dirty(s->vram_offset + y);
1614 } else {
1615 /* Tricky things won't have any effect, i.e. we are in the very simple
1616 * (and very usual) case of a linear buffer. */
1617 unsigned long end;
1619 for ( ; y < ((s->start_addr * 4) & TARGET_PAGE_MASK); y += TARGET_PAGE_SIZE)
1620 /* We will not read that anyway. */
1621 cpu_physical_memory_set_dirty(s->vram_offset + y);
1623 if (y < (s->start_addr * 4)) {
1624 /* start address not aligned on a page, track dirtyness by hand. */
1625 if (vram_dirty(s, y, TARGET_PAGE_SIZE))
1626 cpu_physical_memory_set_dirty(s->vram_offset + y);
1627 y += TARGET_PAGE_SIZE;
1630 /* use page table dirty bit tracking for the inner of the LFB */
1631 end = s->start_addr * 4 + height * line_offset;
1633 unsigned long npages = ((end & TARGET_PAGE_MASK) - y) / TARGET_PAGE_SIZE;
1634 const int width = sizeof(unsigned long) * 8;
1635 unsigned long bitmap[(npages + width - 1) / width];
1636 int err;
1638 if (!(err = xc_hvm_track_dirty_vram(xc_handle, domid,
1639 (s->lfb_addr + y) / TARGET_PAGE_SIZE, npages, bitmap))) {
1640 int i, j;
1641 for (i = 0; i < sizeof(bitmap) / sizeof(*bitmap); i++) {
1642 unsigned long map = bitmap[i];
1643 for (j = i * width; map && j < npages; map >>= 1, j++)
1644 if (map & 1)
1645 cpu_physical_memory_set_dirty(s->vram_offset + y
1646 + j * TARGET_PAGE_SIZE);
1648 y += npages * TARGET_PAGE_SIZE;
1649 } else {
1650 /* ENODATA just means we have changed mode and will succeed
1651 * next time */
1652 if (err != -ENODATA)
1653 fprintf(stderr, "track_dirty_vram(%lx, %lx) failed (%d)\n", s->lfb_addr + y, npages, err);
1657 for ( ; y < s->vram_size && y < end; y += TARGET_PAGE_SIZE)
1658 /* failed or end address not aligned on a page, track dirtyness by
1659 * hand. */
1660 if (vram_dirty(s, y, TARGET_PAGE_SIZE))
1661 cpu_physical_memory_set_dirty(s->vram_offset + y);
1663 for ( ; y < s->vram_size; y += TARGET_PAGE_SIZE)
1664 /* We will not read that anyway. */
1665 cpu_physical_memory_set_dirty(s->vram_offset + y);
1668 addr1 = (s->start_addr * 4);
1669 bwidth = (width * bits + 7) / 8;
1670 y_start = -1;
1671 page_min = 0;
1672 page_max = 0;
1673 d = s->ds->data;
1674 linesize = s->ds->linesize;
1675 y1 = 0;
1676 for(y = 0; y < height; y++) {
1677 addr = addr1;
1678 if (!(s->cr[0x17] & 1)) {
1679 int shift;
1680 /* CGA compatibility handling */
1681 shift = 14 + ((s->cr[0x17] >> 6) & 1);
1682 addr = (addr & ~(1 << shift)) | ((y1 & 1) << shift);
1684 if (!(s->cr[0x17] & 2)) {
1685 addr = (addr & ~0x8000) | ((y1 & 2) << 14);
1687 page0 = s->vram_offset + (addr & TARGET_PAGE_MASK);
1688 page1 = s->vram_offset + ((addr + bwidth - 1) & TARGET_PAGE_MASK);
1689 update = full_update |
1690 cpu_physical_memory_get_dirty(page0, VGA_DIRTY_FLAG) |
1691 cpu_physical_memory_get_dirty(page1, VGA_DIRTY_FLAG);
1692 if ((page1 - page0) > TARGET_PAGE_SIZE) {
1693 /* if wide line, can use another page */
1694 update |= cpu_physical_memory_get_dirty(page0 + TARGET_PAGE_SIZE,
1695 VGA_DIRTY_FLAG);
1697 /* explicit invalidation for the hardware cursor */
1698 update |= (s->invalidated_y_table[y >> 5] >> (y & 0x1f)) & 1;
1699 if (update) {
1700 if (y_start < 0)
1701 y_start = y;
1702 if (page_min == 0 || page0 < page_min)
1703 page_min = page0;
1704 if (page_max == 0 || page1 > page_max)
1705 page_max = page1;
1706 if (!s->ds->shared_buf) {
1707 vga_draw_line(s, d, s->vram_ptr + addr, width);
1708 if (s->cursor_draw_line)
1709 s->cursor_draw_line(s, d, y);
1711 } else {
1712 if (y_start >= 0) {
1713 /* flush to display */
1714 dpy_update(s->ds, 0, y_start,
1715 disp_width, y - y_start);
1716 y_start = -1;
1719 if (!multi_run) {
1720 mask = (s->cr[0x17] & 3) ^ 3;
1721 if ((y1 & mask) == mask)
1722 addr1 += line_offset;
1723 y1++;
1724 multi_run = multi_scan;
1725 } else {
1726 multi_run--;
1728 /* line compare acts on the displayed lines */
1729 if (y == s->line_compare)
1730 addr1 = 0;
1731 d += linesize;
1733 if (y_start >= 0) {
1734 /* flush to display */
1735 dpy_update(s->ds, 0, y_start,
1736 disp_width, y - y_start);
1738 /* reset modified pages */
1739 if (page_max != -1) {
1740 cpu_physical_memory_reset_dirty(page_min, page_max + TARGET_PAGE_SIZE,
1741 VGA_DIRTY_FLAG);
1743 memset(s->invalidated_y_table, 0, ((height + 31) >> 5) * 4);
1746 static void vga_draw_blank(VGAState *s, int full_update)
1748 int i, w, val;
1749 uint8_t *d;
1751 if (!full_update)
1752 return;
1753 if (s->last_scr_width <= 0 || s->last_scr_height <= 0)
1754 return;
1756 /* Disable dirty bit tracking */
1757 xc_hvm_track_dirty_vram(xc_handle, domid, 0, 0, NULL);
1759 s->rgb_to_pixel =
1760 rgb_to_pixel_dup_table[get_depth_index(s->ds)];
1761 if (s->ds->depth == 8)
1762 val = s->rgb_to_pixel(0, 0, 0);
1763 else
1764 val = 0;
1765 w = s->last_scr_width * ((s->ds->depth + 7) >> 3);
1766 d = s->ds->data;
1767 for(i = 0; i < s->last_scr_height; i++) {
1768 memset(d, val, w);
1769 d += s->ds->linesize;
1771 dpy_update(s->ds, 0, 0,
1772 s->last_scr_width, s->last_scr_height);
1775 #define GMODE_TEXT 0
1776 #define GMODE_GRAPH 1
1777 #define GMODE_BLANK 2
1779 static void vga_update_display(void *opaque)
1781 VGAState *s = (VGAState *)opaque;
1782 int full_update, graphic_mode;
1784 if (s->ds->depth == 0) {
1785 /* nothing to do */
1786 } else {
1787 full_update = 0;
1788 if (!(s->ar_index & 0x20)) {
1789 graphic_mode = GMODE_BLANK;
1790 } else {
1791 graphic_mode = s->gr[6] & 1;
1793 if (graphic_mode != s->graphic_mode) {
1794 s->graphic_mode = graphic_mode;
1795 full_update = 1;
1797 switch(graphic_mode) {
1798 case GMODE_TEXT:
1799 vga_draw_text(s, full_update);
1800 break;
1801 case GMODE_GRAPH:
1802 vga_draw_graphic(s, full_update);
1803 break;
1804 case GMODE_BLANK:
1805 default:
1806 vga_draw_blank(s, full_update);
1807 break;
1812 /* force a full display refresh */
1813 static void vga_invalidate_display(void *opaque)
1815 VGAState *s = (VGAState *)opaque;
1817 s->last_width = -1;
1818 s->last_height = -1;
1821 static void vga_reset(VGAState *s)
1823 memset(s, 0, sizeof(VGAState));
1824 s->graphic_mode = -1; /* force full update */
1827 static CPUReadMemoryFunc *vga_mem_read[3] = {
1828 vga_mem_readb,
1829 vga_mem_readw,
1830 vga_mem_readl,
1831 };
1833 static CPUWriteMemoryFunc *vga_mem_write[3] = {
1834 vga_mem_writeb,
1835 vga_mem_writew,
1836 vga_mem_writel,
1837 };
1839 static void vga_save(QEMUFile *f, void *opaque)
1841 VGAState *s = opaque;
1842 uint32_t vram_size;
1843 #ifdef CONFIG_BOCHS_VBE
1844 int i;
1845 #endif
1847 if (s->pci_dev)
1848 pci_device_save(s->pci_dev, f);
1850 qemu_put_be32s(f, &s->latch);
1851 qemu_put_8s(f, &s->sr_index);
1852 qemu_put_buffer(f, s->sr, 8);
1853 qemu_put_8s(f, &s->gr_index);
1854 qemu_put_buffer(f, s->gr, 16);
1855 qemu_put_8s(f, &s->ar_index);
1856 qemu_put_buffer(f, s->ar, 21);
1857 qemu_put_be32s(f, &s->ar_flip_flop);
1858 qemu_put_8s(f, &s->cr_index);
1859 qemu_put_buffer(f, s->cr, 256);
1860 qemu_put_8s(f, &s->msr);
1861 qemu_put_8s(f, &s->fcr);
1862 qemu_put_8s(f, &s->st00);
1863 qemu_put_8s(f, &s->st01);
1865 qemu_put_8s(f, &s->dac_state);
1866 qemu_put_8s(f, &s->dac_sub_index);
1867 qemu_put_8s(f, &s->dac_read_index);
1868 qemu_put_8s(f, &s->dac_write_index);
1869 qemu_put_buffer(f, s->dac_cache, 3);
1870 qemu_put_buffer(f, s->palette, 768);
1872 qemu_put_be32s(f, &s->bank_offset);
1873 #ifdef CONFIG_BOCHS_VBE
1874 qemu_put_byte(f, 1);
1875 qemu_put_be16s(f, &s->vbe_index);
1876 for(i = 0; i < VBE_DISPI_INDEX_NB; i++)
1877 qemu_put_be16s(f, &s->vbe_regs[i]);
1878 qemu_put_be32s(f, &s->vbe_start_addr);
1879 qemu_put_be32s(f, &s->vbe_line_offset);
1880 qemu_put_be32s(f, &s->vbe_bank_mask);
1881 #else
1882 qemu_put_byte(f, 0);
1883 #endif
1884 vram_size = s->vram_size;
1885 qemu_put_be32s(f, &vram_size);
1886 qemu_put_buffer(f, s->vram_ptr, s->vram_size);
1889 static int vga_load(QEMUFile *f, void *opaque, int version_id)
1891 VGAState *s = opaque;
1892 int is_vbe, ret;
1893 uint32_t vram_size;
1894 #ifdef CONFIG_BOCHS_VBE
1895 int i;
1896 #endif
1898 if (version_id > 3)
1899 return -EINVAL;
1901 if (s->pci_dev && version_id >= 2) {
1902 ret = pci_device_load(s->pci_dev, f);
1903 if (ret < 0)
1904 return ret;
1907 qemu_get_be32s(f, &s->latch);
1908 qemu_get_8s(f, &s->sr_index);
1909 qemu_get_buffer(f, s->sr, 8);
1910 qemu_get_8s(f, &s->gr_index);
1911 qemu_get_buffer(f, s->gr, 16);
1912 qemu_get_8s(f, &s->ar_index);
1913 qemu_get_buffer(f, s->ar, 21);
1914 qemu_get_be32s(f, &s->ar_flip_flop);
1915 qemu_get_8s(f, &s->cr_index);
1916 qemu_get_buffer(f, s->cr, 256);
1917 qemu_get_8s(f, &s->msr);
1918 qemu_get_8s(f, &s->fcr);
1919 qemu_get_8s(f, &s->st00);
1920 qemu_get_8s(f, &s->st01);
1922 qemu_get_8s(f, &s->dac_state);
1923 qemu_get_8s(f, &s->dac_sub_index);
1924 qemu_get_8s(f, &s->dac_read_index);
1925 qemu_get_8s(f, &s->dac_write_index);
1926 qemu_get_buffer(f, s->dac_cache, 3);
1927 qemu_get_buffer(f, s->palette, 768);
1929 qemu_get_be32s(f, &s->bank_offset);
1930 is_vbe = qemu_get_byte(f);
1931 #ifdef CONFIG_BOCHS_VBE
1932 if (!is_vbe)
1933 return -EINVAL;
1934 qemu_get_be16s(f, &s->vbe_index);
1935 for(i = 0; i < VBE_DISPI_INDEX_NB; i++)
1936 qemu_get_be16s(f, &s->vbe_regs[i]);
1937 qemu_get_be32s(f, &s->vbe_start_addr);
1938 qemu_get_be32s(f, &s->vbe_line_offset);
1939 qemu_get_be32s(f, &s->vbe_bank_mask);
1940 #else
1941 if (is_vbe)
1942 return -EINVAL;
1943 #endif
1944 if (version_id >= 3) {
1945 /* people who restore old images may be lucky ... */
1946 qemu_get_be32s(f, &vram_size);
1947 if (vram_size != s->vram_size)
1948 return -EINVAL;
1949 qemu_get_buffer(f, s->vram_ptr, s->vram_size);
1952 /* force refresh */
1953 s->graphic_mode = -1;
1954 return 0;
1957 typedef struct PCIVGAState {
1958 PCIDevice dev;
1959 VGAState vga_state;
1960 } PCIVGAState;
1962 static void vga_map(PCIDevice *pci_dev, int region_num,
1963 uint32_t addr, uint32_t size, int type)
1965 PCIVGAState *d = (PCIVGAState *)pci_dev;
1966 VGAState *s = &d->vga_state;
1967 if (region_num == PCI_ROM_SLOT) {
1968 cpu_register_physical_memory(addr, s->bios_size, s->bios_offset);
1969 } else {
1970 cpu_register_physical_memory(addr, s->vram_size, s->vram_offset);
1974 /* do the same job as vgabios before vgabios get ready - yeah */
1975 void vga_bios_init(VGAState *s)
1977 uint8_t palette_model[192] = {
1978 0, 0, 0, 0, 0, 170, 0, 170,
1979 0, 0, 170, 170, 170, 0, 0, 170,
1980 0, 170, 170, 85, 0, 170, 170, 170,
1981 85, 85, 85, 85, 85, 255, 85, 255,
1982 85, 85, 255, 255, 255, 85, 85, 255,
1983 85, 255, 255, 255, 85, 255, 255, 255,
1984 0, 21, 0, 0, 21, 42, 0, 63,
1985 0, 0, 63, 42, 42, 21, 0, 42,
1986 21, 42, 42, 63, 0, 42, 63, 42,
1987 0, 21, 21, 0, 21, 63, 0, 63,
1988 21, 0, 63, 63, 42, 21, 21, 42,
1989 21, 63, 42, 63, 21, 42, 63, 63,
1990 21, 0, 0, 21, 0, 42, 21, 42,
1991 0, 21, 42, 42, 63, 0, 0, 63,
1992 0, 42, 63, 42, 0, 63, 42, 42,
1993 21, 0, 21, 21, 0, 63, 21, 42,
1994 21, 21, 42, 63, 63, 0, 21, 63,
1995 0, 63, 63, 42, 21, 63, 42, 63,
1996 21, 21, 0, 21, 21, 42, 21, 63,
1997 0, 21, 63, 42, 63, 21, 0, 63,
1998 21, 42, 63, 63, 0, 63, 63, 42,
1999 21, 21, 21, 21, 21, 63, 21, 63,
2000 21, 21, 63, 63, 63, 21, 21, 63,
2001 21, 63, 63, 63, 21, 63, 63, 63
2002 };
2004 s->latch = 0;
2006 s->sr_index = 3;
2007 s->sr[0] = 3;
2008 s->sr[1] = 0;
2009 s->sr[2] = 3;
2010 s->sr[3] = 0;
2011 s->sr[4] = 2;
2012 s->sr[5] = 0;
2013 s->sr[6] = 0;
2014 s->sr[7] = 0;
2016 s->gr_index = 5;
2017 s->gr[0] = 0;
2018 s->gr[1] = 0;
2019 s->gr[2] = 0;
2020 s->gr[3] = 0;
2021 s->gr[4] = 0;
2022 s->gr[5] = 16;
2023 s->gr[6] = 14;
2024 s->gr[7] = 15;
2025 s->gr[8] = 255;
2027 /* changed by out 0x03c0 */
2028 s->ar_index = 32;
2029 s->ar[0] = 0;
2030 s->ar[1] = 1;
2031 s->ar[2] = 2;
2032 s->ar[3] = 3;
2033 s->ar[4] = 4;
2034 s->ar[5] = 5;
2035 s->ar[6] = 6;
2036 s->ar[7] = 7;
2037 s->ar[8] = 8;
2038 s->ar[9] = 9;
2039 s->ar[10] = 10;
2040 s->ar[11] = 11;
2041 s->ar[12] = 12;
2042 s->ar[13] = 13;
2043 s->ar[14] = 14;
2044 s->ar[15] = 15;
2045 s->ar[16] = 12;
2046 s->ar[17] = 0;
2047 s->ar[18] = 15;
2048 s->ar[19] = 8;
2049 s->ar[20] = 0;
2051 s->ar_flip_flop = 1;
2053 s->cr_index = 15;
2054 s->cr[0] = 95;
2055 s->cr[1] = 79;
2056 s->cr[2] = 80;
2057 s->cr[3] = 130;
2058 s->cr[4] = 85;
2059 s->cr[5] = 129;
2060 s->cr[6] = 191;
2061 s->cr[7] = 31;
2062 s->cr[8] = 0;
2063 s->cr[9] = 79;
2064 s->cr[10] = 14;
2065 s->cr[11] = 15;
2066 s->cr[12] = 0;
2067 s->cr[13] = 0;
2068 s->cr[14] = 5;
2069 s->cr[15] = 160;
2070 s->cr[16] = 156;
2071 s->cr[17] = 142;
2072 s->cr[18] = 143;
2073 s->cr[19] = 40;
2074 s->cr[20] = 31;
2075 s->cr[21] = 150;
2076 s->cr[22] = 185;
2077 s->cr[23] = 163;
2078 s->cr[24] = 255;
2080 s->msr = 103;
2081 s->fcr = 0;
2082 s->st00 = 0;
2083 s->st01 = 0;
2085 /* dac_* & palette will be initialized by os through out 0x03c8 &
2086 * out 0c03c9(1:3) */
2087 s->dac_state = 0;
2088 s->dac_sub_index = 0;
2089 s->dac_read_index = 0;
2090 s->dac_write_index = 16;
2091 s->dac_cache[0] = 255;
2092 s->dac_cache[1] = 255;
2093 s->dac_cache[2] = 255;
2095 /* palette */
2096 memcpy(s->palette, palette_model, 192);
2098 s->bank_offset = 0;
2099 s->graphic_mode = -1;
2101 /* TODO: add vbe support if enabled */
2104 /* when used on xen environment, the vga_ram_base is not used */
2105 void vga_common_init(VGAState *s, DisplayState *ds, uint8_t *vga_ram_base,
2106 unsigned long vga_ram_offset, int vga_ram_size)
2108 int i, j, v, b;
2110 for(i = 0;i < 256; i++) {
2111 v = 0;
2112 for(j = 0; j < 8; j++) {
2113 v |= ((i >> j) & 1) << (j * 4);
2115 expand4[i] = v;
2117 v = 0;
2118 for(j = 0; j < 4; j++) {
2119 v |= ((i >> (2 * j)) & 3) << (j * 4);
2121 expand2[i] = v;
2123 for(i = 0; i < 16; i++) {
2124 v = 0;
2125 for(j = 0; j < 4; j++) {
2126 b = ((i >> j) & 1);
2127 v |= b << (2 * j);
2128 v |= b << (2 * j + 1);
2130 expand4to8[i] = v;
2133 vga_reset(s);
2135 check_sse2();
2136 s->vram_shadow = qemu_malloc(vga_ram_size+TARGET_PAGE_SIZE+1);
2137 if (s->vram_shadow == NULL)
2138 fprintf(stderr, "Cannot allocate %d bytes for VRAM shadow, "
2139 "mouse will be slow\n", vga_ram_size);
2140 s->vram_shadow = (uint8_t *)((long)(s->vram_shadow + TARGET_PAGE_SIZE - 1)
2141 & ~(TARGET_PAGE_SIZE - 1));
2143 /* Video RAM must be 128-bit aligned for SSE optimizations later */
2144 /* and page-aligned for PVFB memory sharing */
2145 s->vram_ptr = s->vram_alloc = qemu_memalign(TARGET_PAGE_SIZE, vga_ram_size);
2147 s->vram_offset = vga_ram_offset;
2148 s->vram_size = vga_ram_size;
2149 s->ds = ds;
2150 ds->palette = s->last_palette;
2151 s->get_bpp = vga_get_bpp;
2152 s->get_offsets = vga_get_offsets;
2153 s->get_resolution = vga_get_resolution;
2154 graphic_console_init(s->ds, vga_update_display, vga_invalidate_display,
2155 vga_screen_dump, s);
2157 vga_bios_init(s);
2160 /* used by both ISA and PCI */
2161 static void vga_init(VGAState *s)
2163 int vga_io_memory;
2165 register_savevm("vga", 0, 3, vga_save, vga_load, s);
2167 register_ioport_write(0x3c0, 16, 1, vga_ioport_write, s);
2169 register_ioport_write(0x3b4, 2, 1, vga_ioport_write, s);
2170 register_ioport_write(0x3d4, 2, 1, vga_ioport_write, s);
2171 register_ioport_write(0x3ba, 1, 1, vga_ioport_write, s);
2172 register_ioport_write(0x3da, 1, 1, vga_ioport_write, s);
2174 register_ioport_read(0x3c0, 16, 1, vga_ioport_read, s);
2176 register_ioport_read(0x3b4, 2, 1, vga_ioport_read, s);
2177 register_ioport_read(0x3d4, 2, 1, vga_ioport_read, s);
2178 register_ioport_read(0x3ba, 1, 1, vga_ioport_read, s);
2179 register_ioport_read(0x3da, 1, 1, vga_ioport_read, s);
2180 s->bank_offset = 0;
2182 #ifdef CONFIG_BOCHS_VBE
2183 s->vbe_regs[VBE_DISPI_INDEX_ID] = VBE_DISPI_ID0;
2184 s->vbe_bank_mask = ((s->vram_size >> 16) - 1);
2185 #if defined (TARGET_I386)
2186 register_ioport_read(0x1ce, 1, 2, vbe_ioport_read_index, s);
2187 register_ioport_read(0x1cf, 1, 2, vbe_ioport_read_data, s);
2189 register_ioport_write(0x1ce, 1, 2, vbe_ioport_write_index, s);
2190 register_ioport_write(0x1cf, 1, 2, vbe_ioport_write_data, s);
2192 /* old Bochs IO ports */
2193 register_ioport_read(0xff80, 1, 2, vbe_ioport_read_index, s);
2194 register_ioport_read(0xff81, 1, 2, vbe_ioport_read_data, s);
2196 register_ioport_write(0xff80, 1, 2, vbe_ioport_write_index, s);
2197 register_ioport_write(0xff81, 1, 2, vbe_ioport_write_data, s);
2198 #else
2199 register_ioport_read(0x1ce, 1, 2, vbe_ioport_read_index, s);
2200 register_ioport_read(0x1d0, 1, 2, vbe_ioport_read_data, s);
2202 register_ioport_write(0x1ce, 1, 2, vbe_ioport_write_index, s);
2203 register_ioport_write(0x1d0, 1, 2, vbe_ioport_write_data, s);
2204 #endif
2205 #endif /* CONFIG_BOCHS_VBE */
2207 vga_io_memory = cpu_register_io_memory(0, vga_mem_read, vga_mem_write, s);
2208 cpu_register_physical_memory(isa_mem_base + 0x000a0000, 0x20000,
2209 vga_io_memory);
2212 int isa_vga_init(DisplayState *ds, uint8_t *vga_ram_base,
2213 unsigned long vga_ram_offset, int vga_ram_size)
2215 VGAState *s;
2217 s = qemu_mallocz(sizeof(VGAState));
2218 if (!s)
2219 return -1;
2221 vga_common_init(s, ds, vga_ram_base, vga_ram_offset, vga_ram_size);
2222 vga_init(s);
2224 #ifdef CONFIG_BOCHS_VBE
2225 /* XXX: use optimized standard vga accesses */
2226 cpu_register_physical_memory(VBE_DISPI_LFB_PHYSICAL_ADDRESS,
2227 vga_ram_size, vga_ram_offset);
2228 #endif
2229 return 0;
2232 int pci_vga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
2233 unsigned long vga_ram_offset, int vga_ram_size,
2234 unsigned long vga_bios_offset, int vga_bios_size)
2236 PCIVGAState *d;
2237 VGAState *s;
2238 uint8_t *pci_conf;
2240 d = (PCIVGAState *)pci_register_device(bus, "VGA",
2241 sizeof(PCIVGAState),
2242 -1, NULL, NULL);
2243 if (!d)
2244 return -1;
2245 s = &d->vga_state;
2247 vga_common_init(s, ds, vga_ram_base, vga_ram_offset, vga_ram_size);
2248 vga_init(s);
2249 s->pci_dev = &d->dev;
2251 pci_conf = d->dev.config;
2252 pci_conf[0x00] = 0x34; // dummy VGA (same as Bochs ID)
2253 pci_conf[0x01] = 0x12;
2254 pci_conf[0x02] = 0x11;
2255 pci_conf[0x03] = 0x11;
2256 pci_conf[0x0a] = 0x00; // VGA controller
2257 pci_conf[0x0b] = 0x03;
2258 pci_conf[0x0e] = 0x00; // header_type
2260 /* XXX: vga_ram_size must be a power of two */
2261 pci_register_io_region(&d->dev, 0, vga_ram_size,
2262 PCI_ADDRESS_SPACE_MEM_PREFETCH, vga_map);
2263 if (vga_bios_size != 0) {
2264 unsigned int bios_total_size;
2265 s->bios_offset = vga_bios_offset;
2266 s->bios_size = vga_bios_size;
2267 /* must be a power of two */
2268 bios_total_size = 1;
2269 while (bios_total_size < vga_bios_size)
2270 bios_total_size <<= 1;
2271 pci_register_io_region(&d->dev, PCI_ROM_SLOT, bios_total_size,
2272 PCI_ADDRESS_SPACE_MEM_PREFETCH, vga_map);
2274 return 0;
2277 void *vga_update_vram(VGAState *s, void *vga_ram_base, int vga_ram_size)
2279 uint8_t *old_pointer;
2281 if (s->vram_size != vga_ram_size) {
2282 fprintf(stderr, "No support to change vga_ram_size\n");
2283 return NULL;
2286 if (!vga_ram_base) {
2287 vga_ram_base = qemu_memalign(TARGET_PAGE_SIZE, vga_ram_size + TARGET_PAGE_SIZE + 1);
2288 if (!vga_ram_base) {
2289 fprintf(stderr, "reallocate error\n");
2290 return NULL;
2294 /* XXX lock needed? */
2295 old_pointer = s->vram_alloc;
2296 s->vram_alloc = vga_ram_base;
2297 vga_ram_base = (uint8_t *)((long)(vga_ram_base + 15) & ~15L);
2298 memcpy(vga_ram_base, s->vram_ptr, vga_ram_size);
2299 s->vram_ptr = vga_ram_base;
2301 return old_pointer;
2304 /********************************************************/
2305 /* vga screen dump */
2307 static int vga_save_w, vga_save_h;
2309 static void vga_save_dpy_update(DisplayState *s,
2310 int x, int y, int w, int h)
2314 static void vga_save_dpy_resize(DisplayState *s, int w, int h, int linesize)
2316 s->linesize = w * 4;
2317 s->data = qemu_malloc(h * s->linesize);
2318 vga_save_w = w;
2319 vga_save_h = h;
2322 static void vga_save_dpy_refresh(DisplayState *s)
2326 static int ppm_save(const char *filename, uint8_t *data,
2327 int w, int h, int linesize)
2329 FILE *f;
2330 uint8_t *d, *d1;
2331 unsigned int v;
2332 int y, x;
2334 f = fopen(filename, "wb");
2335 if (!f)
2336 return -1;
2337 fprintf(f, "P6\n%d %d\n%d\n",
2338 w, h, 255);
2339 d1 = data;
2340 for(y = 0; y < h; y++) {
2341 d = d1;
2342 for(x = 0; x < w; x++) {
2343 v = *(uint32_t *)d;
2344 fputc((v >> 16) & 0xff, f);
2345 fputc((v >> 8) & 0xff, f);
2346 fputc((v) & 0xff, f);
2347 d += 4;
2349 d1 += linesize;
2351 fclose(f);
2352 return 0;
2355 /* save the vga display in a PPM image even if no display is
2356 available */
2357 static void vga_screen_dump(void *opaque, const char *filename)
2359 VGAState *s = (VGAState *)opaque;
2360 DisplayState *saved_ds, ds1, *ds = &ds1;
2362 /* XXX: this is a little hackish */
2363 vga_invalidate_display(s);
2364 saved_ds = s->ds;
2366 memset(ds, 0, sizeof(DisplayState));
2367 ds->dpy_update = vga_save_dpy_update;
2368 ds->dpy_resize = vga_save_dpy_resize;
2369 ds->dpy_refresh = vga_save_dpy_refresh;
2370 ds->depth = 32;
2372 s->ds = ds;
2373 s->graphic_mode = -1;
2374 vga_update_display(s);
2376 if (ds->data) {
2377 ppm_save(filename, ds->data, vga_save_w, vga_save_h,
2378 s->ds->linesize);
2379 qemu_free(ds->data);
2381 s->ds = saved_ds;