ia64/xen-unstable

view xen/arch/x86/smpboot.c @ 18345:b5396a87a64a

x86: APs enable x2APIC only when BSP did so.
Signed-off-by: Jun Nakajima <jun.nakajikma@intel.com>
author Keir Fraser <keir.fraser@citrix.com>
date Wed Aug 20 09:04:33 2008 +0100 (2008-08-20)
parents b38bceff087a
children 4ffc70556000
line source
1 /*
2 * x86 SMP booting functions
3 *
4 * (c) 1995 Alan Cox, Building #3 <alan@redhat.com>
5 * (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com>
6 *
7 * Much of the core SMP work is based on previous work by Thomas Radke, to
8 * whom a great many thanks are extended.
9 *
10 * Thanks to Intel for making available several different Pentium,
11 * Pentium Pro and Pentium-II/Xeon MP machines.
12 * Original development of Linux SMP code supported by Caldera.
13 *
14 * This code is released under the GNU General Public License version 2 or
15 * later.
16 *
17 * Fixes
18 * Felix Koop : NR_CPUS used properly
19 * Jose Renau : Handle single CPU case.
20 * Alan Cox : By repeated request 8) - Total BogoMIPS report.
21 * Greg Wright : Fix for kernel stacks panic.
22 * Erich Boleyn : MP v1.4 and additional changes.
23 * Matthias Sattler : Changes for 2.1 kernel map.
24 * Michel Lespinasse : Changes for 2.1 kernel map.
25 * Michael Chastain : Change trampoline.S to gnu as.
26 * Alan Cox : Dumb bug: 'B' step PPro's are fine
27 * Ingo Molnar : Added APIC timers, based on code
28 * from Jose Renau
29 * Ingo Molnar : various cleanups and rewrites
30 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug.
31 * Maciej W. Rozycki : Bits for genuine 82489DX APICs
32 * Martin J. Bligh : Added support for multi-quad systems
33 * Dave Jones : Report invalid combinations of Athlon CPUs.
34 * Rusty Russell : Hacked into shape for new "hotplug" boot process. */
36 #include <xen/config.h>
37 #include <xen/init.h>
38 #include <xen/kernel.h>
39 #include <xen/mm.h>
40 #include <xen/domain.h>
41 #include <xen/sched.h>
42 #include <xen/irq.h>
43 #include <xen/delay.h>
44 #include <xen/softirq.h>
45 #include <xen/serial.h>
46 #include <xen/numa.h>
47 #include <asm/current.h>
48 #include <asm/mc146818rtc.h>
49 #include <asm/desc.h>
50 #include <asm/div64.h>
51 #include <asm/flushtlb.h>
52 #include <asm/msr.h>
53 #include <asm/mtrr.h>
54 #include <mach_apic.h>
55 #include <mach_wakecpu.h>
56 #include <smpboot_hooks.h>
57 #include <xen/stop_machine.h>
59 #define set_kernel_exec(x, y) (0)
60 #define setup_trampoline() (bootsym_phys(trampoline_realmode_entry))
62 /* Set if we find a B stepping CPU */
63 static int __devinitdata smp_b_stepping;
65 /* Number of siblings per CPU package */
66 int smp_num_siblings = 1;
67 #ifdef CONFIG_X86_HT
68 EXPORT_SYMBOL(smp_num_siblings);
69 #endif
71 /* Package ID of each logical CPU */
72 int phys_proc_id[NR_CPUS] __read_mostly = {[0 ... NR_CPUS-1] = BAD_APICID};
74 /* Core ID of each logical CPU */
75 int cpu_core_id[NR_CPUS] __read_mostly = {[0 ... NR_CPUS-1] = BAD_APICID};
77 /* representing HT siblings of each logical CPU */
78 cpumask_t cpu_sibling_map[NR_CPUS] __read_mostly;
79 EXPORT_SYMBOL(cpu_sibling_map);
81 /* representing HT and core siblings of each logical CPU */
82 cpumask_t cpu_core_map[NR_CPUS] __read_mostly;
83 EXPORT_SYMBOL(cpu_core_map);
85 /* bitmap of online cpus */
86 cpumask_t cpu_online_map __read_mostly;
87 EXPORT_SYMBOL(cpu_online_map);
89 cpumask_t cpu_callin_map;
90 cpumask_t cpu_callout_map;
91 EXPORT_SYMBOL(cpu_callout_map);
92 cpumask_t cpu_possible_map;
93 EXPORT_SYMBOL(cpu_possible_map);
94 static cpumask_t smp_commenced_mask;
96 /* TSC's upper 32 bits can't be written in eariler CPU (before prescott), there
97 * is no way to resync one AP against BP. TBD: for prescott and above, we
98 * should use IA64's algorithm
99 */
100 static int __devinitdata tsc_sync_disabled;
102 /* Per CPU bogomips and other parameters */
103 struct cpuinfo_x86 cpu_data[NR_CPUS] __cacheline_aligned;
104 EXPORT_SYMBOL(cpu_data);
106 u32 x86_cpu_to_apicid[NR_CPUS] __read_mostly =
107 { [0 ... NR_CPUS-1] = -1U };
108 EXPORT_SYMBOL(x86_cpu_to_apicid);
110 static void map_cpu_to_logical_apicid(void);
111 /* State of each CPU. */
112 DEFINE_PER_CPU(int, cpu_state) = { 0 };
114 static void *stack_base[NR_CPUS] __cacheline_aligned;
115 static DEFINE_SPINLOCK(cpu_add_remove_lock);
117 /*
118 * The bootstrap kernel entry code has set these up. Save them for
119 * a given CPU
120 */
122 static void __devinit smp_store_cpu_info(int id)
123 {
124 struct cpuinfo_x86 *c = cpu_data + id;
126 *c = boot_cpu_data;
127 if (id!=0)
128 identify_cpu(c);
129 /*
130 * Mask B, Pentium, but not Pentium MMX
131 */
132 if (c->x86_vendor == X86_VENDOR_INTEL &&
133 c->x86 == 5 &&
134 c->x86_mask >= 1 && c->x86_mask <= 4 &&
135 c->x86_model <= 3)
136 /*
137 * Remember we have B step Pentia with bugs
138 */
139 smp_b_stepping = 1;
141 /*
142 * Certain Athlons might work (for various values of 'work') in SMP
143 * but they are not certified as MP capable.
144 */
145 if ((c->x86_vendor == X86_VENDOR_AMD) && (c->x86 == 6)) {
147 /* Athlon 660/661 is valid. */
148 if ((c->x86_model==6) && ((c->x86_mask==0) || (c->x86_mask==1)))
149 goto valid_k7;
151 /* Duron 670 is valid */
152 if ((c->x86_model==7) && (c->x86_mask==0))
153 goto valid_k7;
155 /*
156 * Athlon 662, Duron 671, and Athlon >model 7 have capability bit.
157 * It's worth noting that the A5 stepping (662) of some Athlon XP's
158 * have the MP bit set.
159 * See http://www.heise.de/newsticker/data/jow-18.10.01-000 for more.
160 */
161 if (((c->x86_model==6) && (c->x86_mask>=2)) ||
162 ((c->x86_model==7) && (c->x86_mask>=1)) ||
163 (c->x86_model> 7))
164 if (cpu_has_mp)
165 goto valid_k7;
167 /* If we get here, it's not a certified SMP capable AMD system. */
168 add_taint(TAINT_UNSAFE_SMP);
169 }
171 valid_k7:
172 ;
173 }
175 /*
176 * TSC synchronization.
177 *
178 * We first check whether all CPUs have their TSC's synchronized,
179 * then we print a warning if not, and always resync.
180 */
182 static atomic_t tsc_start_flag = ATOMIC_INIT(0);
183 static atomic_t tsc_count_start = ATOMIC_INIT(0);
184 static atomic_t tsc_count_stop = ATOMIC_INIT(0);
185 static unsigned long long tsc_values[NR_CPUS];
187 #define NR_LOOPS 5
189 static void __init synchronize_tsc_bp (void)
190 {
191 int i;
192 unsigned long long t0;
193 unsigned long long sum, avg;
194 long long delta;
195 unsigned int one_usec;
196 int buggy = 0;
198 printk("checking TSC synchronization across %u CPUs: ", num_booting_cpus());
200 /* convert from kcyc/sec to cyc/usec */
201 one_usec = cpu_khz / 1000;
203 atomic_set(&tsc_start_flag, 1);
204 wmb();
206 /*
207 * We loop a few times to get a primed instruction cache,
208 * then the last pass is more or less synchronized and
209 * the BP and APs set their cycle counters to zero all at
210 * once. This reduces the chance of having random offsets
211 * between the processors, and guarantees that the maximum
212 * delay between the cycle counters is never bigger than
213 * the latency of information-passing (cachelines) between
214 * two CPUs.
215 */
216 for (i = 0; i < NR_LOOPS; i++) {
217 /*
218 * all APs synchronize but they loop on '== num_cpus'
219 */
220 while (atomic_read(&tsc_count_start) != num_booting_cpus()-1)
221 mb();
222 atomic_set(&tsc_count_stop, 0);
223 wmb();
224 /*
225 * this lets the APs save their current TSC:
226 */
227 atomic_inc(&tsc_count_start);
229 rdtscll(tsc_values[smp_processor_id()]);
230 /*
231 * We clear the TSC in the last loop:
232 */
233 if (i == NR_LOOPS-1)
234 write_tsc(0, 0);
236 /*
237 * Wait for all APs to leave the synchronization point:
238 */
239 while (atomic_read(&tsc_count_stop) != num_booting_cpus()-1)
240 mb();
241 atomic_set(&tsc_count_start, 0);
242 wmb();
243 atomic_inc(&tsc_count_stop);
244 }
246 sum = 0;
247 for (i = 0; i < NR_CPUS; i++) {
248 if (cpu_isset(i, cpu_callout_map)) {
249 t0 = tsc_values[i];
250 sum += t0;
251 }
252 }
253 avg = sum;
254 do_div(avg, num_booting_cpus());
256 sum = 0;
257 for (i = 0; i < NR_CPUS; i++) {
258 if (!cpu_isset(i, cpu_callout_map))
259 continue;
260 delta = tsc_values[i] - avg;
261 if (delta < 0)
262 delta = -delta;
263 /*
264 * We report bigger than 2 microseconds clock differences.
265 */
266 if (delta > 2*one_usec) {
267 long realdelta;
268 if (!buggy) {
269 buggy = 1;
270 printk("\n");
271 }
272 realdelta = delta;
273 do_div(realdelta, one_usec);
274 if (tsc_values[i] < avg)
275 realdelta = -realdelta;
277 printk("CPU#%d had %ld usecs TSC skew, fixed it up.\n", i, realdelta);
278 }
280 sum += delta;
281 }
282 if (!buggy)
283 printk("passed.\n");
284 }
286 static void __init synchronize_tsc_ap (void)
287 {
288 int i;
290 /*
291 * Not every cpu is online at the time
292 * this gets called, so we first wait for the BP to
293 * finish SMP initialization:
294 */
295 while (!atomic_read(&tsc_start_flag)) mb();
297 for (i = 0; i < NR_LOOPS; i++) {
298 atomic_inc(&tsc_count_start);
299 while (atomic_read(&tsc_count_start) != num_booting_cpus())
300 mb();
302 rdtscll(tsc_values[smp_processor_id()]);
303 if (i == NR_LOOPS-1)
304 write_tsc(0, 0);
306 atomic_inc(&tsc_count_stop);
307 while (atomic_read(&tsc_count_stop) != num_booting_cpus()) mb();
308 }
309 }
310 #undef NR_LOOPS
312 extern void calibrate_delay(void);
314 static atomic_t init_deasserted;
316 void __devinit smp_callin(void)
317 {
318 int cpuid, phys_id, i;
320 /*
321 * If waken up by an INIT in an 82489DX configuration
322 * we may get here before an INIT-deassert IPI reaches
323 * our local APIC. We have to wait for the IPI or we'll
324 * lock up on an APIC access.
325 */
326 wait_for_init_deassert(&init_deasserted);
328 if ( x2apic_enabled )
329 enable_x2apic();
331 /*
332 * (This works even if the APIC is not enabled.)
333 */
334 phys_id = get_apic_id();
335 cpuid = smp_processor_id();
336 if (cpu_isset(cpuid, cpu_callin_map)) {
337 printk("huh, phys CPU#%d, CPU#%d already present??\n",
338 phys_id, cpuid);
339 BUG();
340 }
341 Dprintk("CPU#%d (phys ID: %d) waiting for CALLOUT\n", cpuid, phys_id);
343 /*
344 * STARTUP IPIs are fragile beasts as they might sometimes
345 * trigger some glue motherboard logic. Complete APIC bus
346 * silence for 1 second, this overestimates the time the
347 * boot CPU is spending to send the up to 2 STARTUP IPIs
348 * by a factor of two. This should be enough.
349 */
351 /*
352 * Waiting 2s total for startup
353 */
354 for (i = 0; i < 200; i++) {
355 /*
356 * Has the boot CPU finished it's STARTUP sequence?
357 */
358 if (cpu_isset(cpuid, cpu_callout_map))
359 break;
360 rep_nop();
361 mdelay(10);
362 }
364 if (!cpu_isset(cpuid, cpu_callout_map)) {
365 printk("BUG: CPU%d started up but did not get a callout!\n",
366 cpuid);
367 BUG();
368 }
370 /*
371 * the boot CPU has finished the init stage and is spinning
372 * on callin_map until we finish. We are free to set up this
373 * CPU, first the APIC. (this is probably redundant on most
374 * boards)
375 */
377 Dprintk("CALLIN, before setup_local_APIC().\n");
378 smp_callin_clear_local_apic();
379 setup_local_APIC();
380 map_cpu_to_logical_apicid();
382 #if 0
383 /*
384 * Get our bogomips.
385 */
386 calibrate_delay();
387 Dprintk("Stack at about %p\n",&cpuid);
388 #endif
390 /*
391 * Save our processor parameters
392 */
393 smp_store_cpu_info(cpuid);
395 disable_APIC_timer();
397 /*
398 * Allow the master to continue.
399 */
400 cpu_set(cpuid, cpu_callin_map);
402 /*
403 * Synchronize the TSC with the BP
404 */
405 if (cpu_has_tsc && cpu_khz && !tsc_sync_disabled) {
406 synchronize_tsc_ap();
407 /* No sync for same reason as above */
408 calibrate_tsc_ap();
409 }
410 }
412 static int cpucount, booting_cpu;
414 /* representing cpus for which sibling maps can be computed */
415 static cpumask_t cpu_sibling_setup_map;
417 static inline void
418 set_cpu_sibling_map(int cpu)
419 {
420 int i;
421 struct cpuinfo_x86 *c = cpu_data;
423 cpu_set(cpu, cpu_sibling_setup_map);
425 if (smp_num_siblings > 1) {
426 for_each_cpu_mask(i, cpu_sibling_setup_map) {
427 if (phys_proc_id[cpu] == phys_proc_id[i] &&
428 cpu_core_id[cpu] == cpu_core_id[i]) {
429 cpu_set(i, cpu_sibling_map[cpu]);
430 cpu_set(cpu, cpu_sibling_map[i]);
431 cpu_set(i, cpu_core_map[cpu]);
432 cpu_set(cpu, cpu_core_map[i]);
433 }
434 }
435 } else {
436 cpu_set(cpu, cpu_sibling_map[cpu]);
437 }
439 if (current_cpu_data.x86_max_cores == 1) {
440 cpu_core_map[cpu] = cpu_sibling_map[cpu];
441 c[cpu].booted_cores = 1;
442 return;
443 }
445 for_each_cpu_mask(i, cpu_sibling_setup_map) {
446 if (phys_proc_id[cpu] == phys_proc_id[i]) {
447 cpu_set(i, cpu_core_map[cpu]);
448 cpu_set(cpu, cpu_core_map[i]);
449 /*
450 * Does this new cpu bringup a new core?
451 */
452 if (cpus_weight(cpu_sibling_map[cpu]) == 1) {
453 /*
454 * for each core in package, increment
455 * the booted_cores for this new cpu
456 */
457 if (first_cpu(cpu_sibling_map[i]) == i)
458 c[cpu].booted_cores++;
459 /*
460 * increment the core count for all
461 * the other cpus in this package
462 */
463 if (i != cpu)
464 c[i].booted_cores++;
465 } else if (i != cpu && !c[cpu].booted_cores)
466 c[cpu].booted_cores = c[i].booted_cores;
467 }
468 }
469 }
471 static void construct_percpu_idt(unsigned int cpu)
472 {
473 unsigned char idt_load[10];
475 /* If IDT table exists since last hotplug, reuse it */
476 if (!idt_tables[cpu]) {
477 idt_tables[cpu] = xmalloc_array(idt_entry_t, IDT_ENTRIES);
478 memcpy(idt_tables[cpu], idt_table,
479 IDT_ENTRIES*sizeof(idt_entry_t));
480 }
482 *(unsigned short *)(&idt_load[0]) = (IDT_ENTRIES*sizeof(idt_entry_t))-1;
483 *(unsigned long *)(&idt_load[2]) = (unsigned long)idt_tables[cpu];
484 __asm__ __volatile__ ( "lidt %0" : "=m" (idt_load) );
485 }
487 /*
488 * Activate a secondary processor.
489 */
490 void __devinit start_secondary(void *unused)
491 {
492 /*
493 * Dont put anything before smp_callin(), SMP
494 * booting is too fragile that we want to limit the
495 * things done here to the most necessary things.
496 */
497 unsigned int cpu = booting_cpu;
499 set_processor_id(cpu);
500 set_current(idle_vcpu[cpu]);
501 this_cpu(curr_vcpu) = idle_vcpu[cpu];
502 if ( cpu_has_efer )
503 rdmsrl(MSR_EFER, this_cpu(efer));
504 asm volatile ( "mov %%cr4,%0" : "=r" (this_cpu(cr4)) );
506 percpu_traps_init();
508 cpu_init();
509 /*preempt_disable();*/
510 smp_callin();
511 while (!cpu_isset(smp_processor_id(), smp_commenced_mask))
512 rep_nop();
514 /*
515 * At this point, boot CPU has fully initialised the IDT. It is
516 * now safe to make ourselves a private copy.
517 */
518 construct_percpu_idt(cpu);
520 setup_secondary_APIC_clock();
521 enable_APIC_timer();
522 /*
523 * low-memory mappings have been cleared, flush them from
524 * the local TLBs too.
525 */
526 flush_tlb_local();
528 /* This must be done before setting cpu_online_map */
529 set_cpu_sibling_map(raw_smp_processor_id());
530 wmb();
532 cpu_set(smp_processor_id(), cpu_online_map);
533 per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE;
535 init_percpu_time();
537 /* We can take interrupts now: we're officially "up". */
538 local_irq_enable();
540 wmb();
541 startup_cpu_idle_loop();
542 }
544 extern struct {
545 void * esp;
546 unsigned short ss;
547 } stack_start;
549 u32 cpu_2_logical_apicid[NR_CPUS] __read_mostly = { [0 ... NR_CPUS-1] = BAD_APICID };
551 static void map_cpu_to_logical_apicid(void)
552 {
553 int cpu = smp_processor_id();
554 int apicid = logical_smp_processor_id();
556 cpu_2_logical_apicid[cpu] = apicid;
557 }
559 static void unmap_cpu_to_logical_apicid(int cpu)
560 {
561 cpu_2_logical_apicid[cpu] = BAD_APICID;
562 }
564 #if APIC_DEBUG
565 static inline void __inquire_remote_apic(int apicid)
566 {
567 int i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 };
568 char *names[] = { "ID", "VERSION", "SPIV" };
569 int timeout, status;
571 printk("Inquiring remote APIC #%d...\n", apicid);
573 for (i = 0; i < ARRAY_SIZE(regs); i++) {
574 printk("... APIC #%d %s: ", apicid, names[i]);
576 /*
577 * Wait for idle.
578 */
579 apic_wait_icr_idle();
581 apic_icr_write(APIC_DM_REMRD | regs[i], apicid);
583 timeout = 0;
584 do {
585 udelay(100);
586 status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK;
587 } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000);
589 switch (status) {
590 case APIC_ICR_RR_VALID:
591 status = apic_read(APIC_RRR);
592 printk("%08x\n", status);
593 break;
594 default:
595 printk("failed\n");
596 }
597 }
598 }
599 #endif
601 #ifdef WAKE_SECONDARY_VIA_NMI
603 static int logical_apicid_to_cpu(int logical_apicid)
604 {
605 int i;
607 for ( i = 0; i < sizeof(cpu_2_logical_apicid); i++ )
608 if ( cpu_2_logical_apicid[i] == logical_apicid )
609 break;
611 if ( i == sizeof(cpu_2_logical_apicid) );
612 i = -1; /* not found */
614 return i;
615 }
617 /*
618 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal
619 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this
620 * won't ... remember to clear down the APIC, etc later.
621 */
622 static int __devinit
623 wakeup_secondary_cpu(int logical_apicid, unsigned long start_eip)
624 {
625 unsigned long send_status = 0, accept_status = 0;
626 int timeout, maxlvt;
627 int dest_cpu;
628 u32 dest;
630 dest_cpu = logical_apicid_to_cpu(logical_apicid);
631 BUG_ON(dest_cpu == -1);
633 dest = cpu_physical_id(dest_cpu);
635 /* Boot on the stack */
636 apic_icr_write(APIC_DM_NMI | APIC_DEST_PHYSICAL, dest_cpu);
638 Dprintk("Waiting for send to finish...\n");
639 timeout = 0;
640 do {
641 Dprintk("+");
642 udelay(100);
643 if ( !x2apic_enabled )
644 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
645 else
646 send_status = 0; /* We go out of the loop directly. */
647 } while (send_status && (timeout++ < 1000));
649 /*
650 * Give the other CPU some time to accept the IPI.
651 */
652 udelay(200);
653 /*
654 * Due to the Pentium erratum 3AP.
655 */
656 maxlvt = get_maxlvt();
657 if (maxlvt > 3) {
658 apic_read_around(APIC_SPIV);
659 apic_write(APIC_ESR, 0);
660 }
661 accept_status = (apic_read(APIC_ESR) & 0xEF);
662 Dprintk("NMI sent.\n");
664 if (send_status)
665 printk("APIC never delivered???\n");
666 if (accept_status)
667 printk("APIC delivery error (%lx).\n", accept_status);
669 return (send_status | accept_status);
670 }
671 #endif /* WAKE_SECONDARY_VIA_NMI */
673 #ifdef WAKE_SECONDARY_VIA_INIT
674 static int __devinit
675 wakeup_secondary_cpu(int phys_apicid, unsigned long start_eip)
676 {
677 unsigned long send_status = 0, accept_status = 0;
678 int maxlvt, timeout, num_starts, j;
680 /*
681 * Be paranoid about clearing APIC errors.
682 */
683 if (APIC_INTEGRATED(apic_version[phys_apicid])) {
684 apic_read_around(APIC_SPIV);
685 apic_write(APIC_ESR, 0);
686 apic_read(APIC_ESR);
687 }
689 Dprintk("Asserting INIT.\n");
691 /*
692 * Turn INIT on target chip via IPI
693 */
694 apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT,
695 phys_apicid);
697 Dprintk("Waiting for send to finish...\n");
698 timeout = 0;
699 do {
700 Dprintk("+");
701 udelay(100);
702 if ( !x2apic_enabled )
703 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
704 else
705 send_status = 0; /* We go out of the loop dirctly. */
706 } while (send_status && (timeout++ < 1000));
708 mdelay(10);
710 Dprintk("Deasserting INIT.\n");
712 apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid);
714 Dprintk("Waiting for send to finish...\n");
715 timeout = 0;
716 do {
717 Dprintk("+");
718 udelay(100);
719 if ( !x2apic_enabled )
720 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
721 else
722 send_status = 0; /* We go out of the loop dirctly. */
723 } while (send_status && (timeout++ < 1000));
725 atomic_set(&init_deasserted, 1);
727 /*
728 * Should we send STARTUP IPIs ?
729 *
730 * Determine this based on the APIC version.
731 * If we don't have an integrated APIC, don't send the STARTUP IPIs.
732 */
733 if (APIC_INTEGRATED(apic_version[phys_apicid]))
734 num_starts = 2;
735 else
736 num_starts = 0;
738 /*
739 * Run STARTUP IPI loop.
740 */
741 Dprintk("#startup loops: %d.\n", num_starts);
743 maxlvt = get_maxlvt();
745 for (j = 1; j <= num_starts; j++) {
746 Dprintk("Sending STARTUP #%d.\n",j);
747 apic_read_around(APIC_SPIV);
748 apic_write(APIC_ESR, 0);
749 apic_read(APIC_ESR);
750 Dprintk("After apic_write.\n");
752 /*
753 * STARTUP IPI
754 * Boot on the stack
755 */
756 apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12), phys_apicid);
758 /*
759 * Give the other CPU some time to accept the IPI.
760 */
761 udelay(300);
763 Dprintk("Startup point 1.\n");
765 Dprintk("Waiting for send to finish...\n");
766 timeout = 0;
767 do {
768 Dprintk("+");
769 udelay(100);
770 if ( !x2apic_enabled )
771 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
772 else
773 send_status = 0; /* We go out of the loop dirctly. */
774 } while (send_status && (timeout++ < 1000));
776 /*
777 * Give the other CPU some time to accept the IPI.
778 */
779 udelay(200);
780 /*
781 * Due to the Pentium erratum 3AP.
782 */
783 if (maxlvt > 3) {
784 apic_read_around(APIC_SPIV);
785 apic_write(APIC_ESR, 0);
786 }
787 accept_status = (apic_read(APIC_ESR) & 0xEF);
788 if (send_status || accept_status)
789 break;
790 }
791 Dprintk("After Startup.\n");
793 if (send_status)
794 printk("APIC never delivered???\n");
795 if (accept_status)
796 printk("APIC delivery error (%lx).\n", accept_status);
798 return (send_status | accept_status);
799 }
800 #endif /* WAKE_SECONDARY_VIA_INIT */
802 extern cpumask_t cpu_initialized;
803 static inline int alloc_cpu_id(void)
804 {
805 cpumask_t tmp_map;
806 int cpu;
807 cpus_complement(tmp_map, cpu_present_map);
808 cpu = first_cpu(tmp_map);
809 if (cpu >= NR_CPUS)
810 return -ENODEV;
811 return cpu;
812 }
814 static struct vcpu *prepare_idle_vcpu(unsigned int cpu)
815 {
816 if (idle_vcpu[cpu])
817 return idle_vcpu[cpu];
819 return alloc_idle_vcpu(cpu);
820 }
822 static void *prepare_idle_stack(unsigned int cpu)
823 {
824 if (!stack_base[cpu])
825 stack_base[cpu] = alloc_xenheap_pages(STACK_ORDER);
827 return stack_base[cpu];
828 }
830 static int __devinit do_boot_cpu(int apicid, int cpu)
831 /*
832 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad
833 * (ie clustered apic addressing mode), this is a LOGICAL apic ID.
834 * Returns zero if CPU booted OK, else error code from wakeup_secondary_cpu.
835 */
836 {
837 unsigned long boot_error;
838 int timeout;
839 unsigned long start_eip;
840 unsigned short nmi_high = 0, nmi_low = 0;
841 struct vcpu *v;
843 /*
844 * Save current MTRR state in case it was changed since early boot
845 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync:
846 */
847 mtrr_save_state();
849 ++cpucount;
851 booting_cpu = cpu;
853 v = prepare_idle_vcpu(cpu);
854 BUG_ON(v == NULL);
856 /* start_eip had better be page-aligned! */
857 start_eip = setup_trampoline();
859 /* So we see what's up */
860 printk("Booting processor %d/%d eip %lx\n", cpu, apicid, start_eip);
862 stack_start.esp = prepare_idle_stack(cpu);
864 /* Debug build: detect stack overflow by setting up a guard page. */
865 memguard_guard_stack(stack_start.esp);
867 /*
868 * This grunge runs the startup process for
869 * the targeted processor.
870 */
872 atomic_set(&init_deasserted, 0);
874 Dprintk("Setting warm reset code and vector.\n");
876 store_NMI_vector(&nmi_high, &nmi_low);
878 smpboot_setup_warm_reset_vector(start_eip);
880 /*
881 * Starting actual IPI sequence...
882 */
883 boot_error = wakeup_secondary_cpu(apicid, start_eip);
885 if (!boot_error) {
886 /*
887 * allow APs to start initializing.
888 */
889 Dprintk("Before Callout %d.\n", cpu);
890 cpu_set(cpu, cpu_callout_map);
891 Dprintk("After Callout %d.\n", cpu);
893 /*
894 * Wait 5s total for a response
895 */
896 for (timeout = 0; timeout < 50000; timeout++) {
897 if (cpu_isset(cpu, cpu_callin_map))
898 break; /* It has booted */
899 udelay(100);
900 }
902 if (cpu_isset(cpu, cpu_callin_map)) {
903 /* number CPUs logically, starting from 1 (BSP is 0) */
904 Dprintk("OK.\n");
905 printk("CPU%d: ", cpu);
906 print_cpu_info(&cpu_data[cpu]);
907 Dprintk("CPU has booted.\n");
908 } else {
909 boot_error = 1;
910 mb();
911 if (bootsym(trampoline_cpu_started) == 0xA5)
912 /* trampoline started but...? */
913 printk("Stuck ??\n");
914 else
915 /* trampoline code not run */
916 printk("Not responding.\n");
917 inquire_remote_apic(apicid);
918 }
919 }
921 if (boot_error) {
922 /* Try to put things back the way they were before ... */
923 unmap_cpu_to_logical_apicid(cpu);
924 cpu_clear(cpu, cpu_callout_map); /* was set here (do_boot_cpu()) */
925 cpu_clear(cpu, cpu_initialized); /* was set by cpu_init() */
926 cpucount--;
927 } else {
928 x86_cpu_to_apicid[cpu] = apicid;
929 cpu_set(cpu, cpu_present_map);
930 }
932 /* mark "stuck" area as not stuck */
933 bootsym(trampoline_cpu_started) = 0;
934 mb();
936 return boot_error;
937 }
939 #ifdef CONFIG_HOTPLUG_CPU
940 static void idle_task_exit(void)
941 {
942 /* Give up lazy state borrowed by this idle vcpu */
943 __sync_lazy_execstate();
944 }
946 void cpu_exit_clear(void)
947 {
948 int cpu = raw_smp_processor_id();
950 idle_task_exit();
952 cpucount --;
953 cpu_uninit();
955 cpu_clear(cpu, cpu_callout_map);
956 cpu_clear(cpu, cpu_callin_map);
958 cpu_clear(cpu, smp_commenced_mask);
959 unmap_cpu_to_logical_apicid(cpu);
960 }
962 static int __cpuinit __smp_prepare_cpu(int cpu)
963 {
964 int apicid, ret;
966 apicid = x86_cpu_to_apicid[cpu];
967 if (apicid == BAD_APICID) {
968 ret = -ENODEV;
969 goto exit;
970 }
972 tsc_sync_disabled = 1;
974 do_boot_cpu(apicid, cpu);
976 tsc_sync_disabled = 0;
978 ret = 0;
979 exit:
980 return ret;
981 }
982 #endif
984 /*
985 * Cycle through the processors sending APIC IPIs to boot each.
986 */
988 /* Where the IO area was mapped on multiquad, always 0 otherwise */
989 void *xquad_portio;
990 #ifdef CONFIG_X86_NUMAQ
991 EXPORT_SYMBOL(xquad_portio);
992 #endif
994 static void __init smp_boot_cpus(unsigned int max_cpus)
995 {
996 int apicid, cpu, bit, kicked;
997 #ifdef BOGOMIPS
998 unsigned long bogosum = 0;
999 #endif
1001 /*
1002 * Setup boot CPU information
1003 */
1004 smp_store_cpu_info(0); /* Final full version of the data */
1005 printk("CPU%d: ", 0);
1006 print_cpu_info(&cpu_data[0]);
1008 boot_cpu_physical_apicid = get_apic_id();
1009 x86_cpu_to_apicid[0] = boot_cpu_physical_apicid;
1011 stack_base[0] = stack_start.esp;
1013 /*current_thread_info()->cpu = 0;*/
1014 /*smp_tune_scheduling();*/
1016 set_cpu_sibling_map(0);
1018 /*
1019 * If we couldn't find an SMP configuration at boot time,
1020 * get out of here now!
1021 */
1022 if (!smp_found_config && !acpi_lapic) {
1023 printk(KERN_NOTICE "SMP motherboard not detected.\n");
1024 init_uniprocessor:
1025 phys_cpu_present_map = physid_mask_of_physid(0);
1026 if (APIC_init_uniprocessor())
1027 printk(KERN_NOTICE "Local APIC not detected."
1028 " Using dummy APIC emulation.\n");
1029 map_cpu_to_logical_apicid();
1030 cpu_set(0, cpu_sibling_map[0]);
1031 cpu_set(0, cpu_core_map[0]);
1032 return;
1035 /*
1036 * Should not be necessary because the MP table should list the boot
1037 * CPU too, but we do it for the sake of robustness anyway.
1038 * Makes no sense to do this check in clustered apic mode, so skip it
1039 */
1040 if (!check_phys_apicid_present(boot_cpu_physical_apicid)) {
1041 printk("weird, boot CPU (#%d) not listed by the BIOS.\n",
1042 boot_cpu_physical_apicid);
1043 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
1046 /*
1047 * If we couldn't find a local APIC, then get out of here now!
1048 */
1049 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid]) && !cpu_has_apic) {
1050 printk(KERN_ERR "BIOS bug, local APIC #%d not detected!...\n",
1051 boot_cpu_physical_apicid);
1052 goto init_uniprocessor;
1055 verify_local_APIC();
1057 /*
1058 * If SMP should be disabled, then really disable it!
1059 */
1060 if (!max_cpus)
1061 goto init_uniprocessor;
1063 connect_bsp_APIC();
1064 setup_local_APIC();
1065 map_cpu_to_logical_apicid();
1068 setup_portio_remap();
1070 /*
1071 * Scan the CPU present map and fire up the other CPUs via do_boot_cpu
1073 * In clustered apic mode, phys_cpu_present_map is a constructed thus:
1074 * bits 0-3 are quad0, 4-7 are quad1, etc. A perverse twist on the
1075 * clustered apic ID.
1076 */
1077 Dprintk("CPU present map: %lx\n", physids_coerce(phys_cpu_present_map));
1079 kicked = 1;
1080 for (bit = 0; kicked < NR_CPUS && bit < MAX_APICS; bit++) {
1081 apicid = cpu_present_to_apicid(bit);
1082 /*
1083 * Don't even attempt to start the boot CPU!
1084 */
1085 if ((apicid == boot_cpu_apicid) || (apicid == BAD_APICID))
1086 continue;
1088 if (!check_apicid_present(apicid))
1089 continue;
1090 if (max_cpus <= cpucount+1)
1091 continue;
1093 if (((cpu = alloc_cpu_id()) <= 0) || do_boot_cpu(apicid, cpu))
1094 printk("CPU #%d not responding - cannot use it.\n",
1095 apicid);
1096 else
1097 ++kicked;
1100 /*
1101 * Cleanup possible dangling ends...
1102 */
1103 smpboot_restore_warm_reset_vector();
1105 #ifdef BOGOMIPS
1106 /*
1107 * Allow the user to impress friends.
1108 */
1109 Dprintk("Before bogomips.\n");
1110 for (cpu = 0; cpu < NR_CPUS; cpu++)
1111 if (cpu_isset(cpu, cpu_callout_map))
1112 bogosum += cpu_data[cpu].loops_per_jiffy;
1113 printk(KERN_INFO
1114 "Total of %d processors activated (%lu.%02lu BogoMIPS).\n",
1115 cpucount+1,
1116 bogosum/(500000/HZ),
1117 (bogosum/(5000/HZ))%100);
1118 #else
1119 printk("Total of %d processors activated.\n", cpucount+1);
1120 #endif
1122 Dprintk("Before bogocount - setting activated=1.\n");
1124 if (smp_b_stepping)
1125 printk(KERN_WARNING "WARNING: SMP operation may be unreliable with B stepping processors.\n");
1127 /*
1128 * Don't taint if we are running SMP kernel on a single non-MP
1129 * approved Athlon
1130 */
1131 if (tainted & TAINT_UNSAFE_SMP) {
1132 if (cpucount)
1133 printk (KERN_INFO "WARNING: This combination of AMD processors is not suitable for SMP.\n");
1134 else
1135 tainted &= ~TAINT_UNSAFE_SMP;
1138 Dprintk("Boot done.\n");
1140 /*
1141 * construct cpu_sibling_map[], so that we can tell sibling CPUs
1142 * efficiently.
1143 */
1144 for (cpu = 0; cpu < NR_CPUS; cpu++) {
1145 cpus_clear(cpu_sibling_map[cpu]);
1146 cpus_clear(cpu_core_map[cpu]);
1149 cpu_set(0, cpu_sibling_map[0]);
1150 cpu_set(0, cpu_core_map[0]);
1152 if (nmi_watchdog == NMI_LOCAL_APIC)
1153 check_nmi_watchdog();
1155 smpboot_setup_io_apic();
1157 setup_boot_APIC_clock();
1159 /*
1160 * Synchronize the TSC with the AP
1161 */
1162 if (cpu_has_tsc && cpucount && cpu_khz)
1163 synchronize_tsc_bp();
1164 calibrate_tsc_bp();
1167 /* These are wrappers to interface to the new boot process. Someone
1168 who understands all this stuff should rewrite it properly. --RR 15/Jul/02 */
1169 void __init smp_prepare_cpus(unsigned int max_cpus)
1171 smp_commenced_mask = cpumask_of_cpu(0);
1172 cpu_callin_map = cpumask_of_cpu(0);
1173 mb();
1174 smp_boot_cpus(max_cpus);
1177 void __devinit smp_prepare_boot_cpu(void)
1179 cpu_set(smp_processor_id(), cpu_online_map);
1180 cpu_set(smp_processor_id(), cpu_callout_map);
1181 cpu_set(smp_processor_id(), cpu_present_map);
1182 cpu_set(smp_processor_id(), cpu_possible_map);
1183 per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE;
1186 #ifdef CONFIG_HOTPLUG_CPU
1187 static void
1188 remove_siblinginfo(int cpu)
1190 int sibling;
1191 struct cpuinfo_x86 *c = cpu_data;
1193 for_each_cpu_mask(sibling, cpu_core_map[cpu]) {
1194 cpu_clear(cpu, cpu_core_map[sibling]);
1195 /*
1196 * last thread sibling in this cpu core going down
1197 */
1198 if (cpus_weight(cpu_sibling_map[cpu]) == 1)
1199 c[sibling].booted_cores--;
1202 for_each_cpu_mask(sibling, cpu_sibling_map[cpu])
1203 cpu_clear(cpu, cpu_sibling_map[sibling]);
1204 cpus_clear(cpu_sibling_map[cpu]);
1205 cpus_clear(cpu_core_map[cpu]);
1206 phys_proc_id[cpu] = BAD_APICID;
1207 cpu_core_id[cpu] = BAD_APICID;
1208 cpu_clear(cpu, cpu_sibling_setup_map);
1211 extern void fixup_irqs(cpumask_t map);
1212 int __cpu_disable(void)
1214 cpumask_t map = cpu_online_map;
1215 int cpu = smp_processor_id();
1217 /*
1218 * Perhaps use cpufreq to drop frequency, but that could go
1219 * into generic code.
1221 * We won't take down the boot processor on i386 due to some
1222 * interrupts only being able to be serviced by the BSP.
1223 * Especially so if we're not using an IOAPIC -zwane
1224 */
1225 if (cpu == 0)
1226 return -EBUSY;
1228 /*
1229 * Only S3 is using this path, and thus idle vcpus are running on all
1230 * APs when we are called. To support full cpu hotplug, other
1231 * notification mechanisms should be introduced (e.g., migrate vcpus
1232 * off this physical cpu before rendezvous point).
1233 */
1234 if (!is_idle_vcpu(current))
1235 return -EINVAL;
1237 local_irq_disable();
1238 clear_local_APIC();
1239 /* Allow any queued timer interrupts to get serviced */
1240 local_irq_enable();
1241 mdelay(1);
1242 local_irq_disable();
1244 time_suspend();
1246 remove_siblinginfo(cpu);
1248 cpu_clear(cpu, map);
1249 fixup_irqs(map);
1250 /* It's now safe to remove this processor from the online map */
1251 cpu_clear(cpu, cpu_online_map);
1252 return 0;
1255 void __cpu_die(unsigned int cpu)
1257 /* We don't do anything here: idle task is faking death itself. */
1258 unsigned int i;
1260 for (i = 0; i < 10; i++) {
1261 /* They ack this in play_dead by setting CPU_DEAD */
1262 if (per_cpu(cpu_state, cpu) == CPU_DEAD) {
1263 printk ("CPU %d is now offline\n", cpu);
1264 return;
1266 mdelay(100);
1267 mb();
1268 process_pending_timers();
1270 printk(KERN_ERR "CPU %u didn't die...\n", cpu);
1273 static int take_cpu_down(void *unused)
1275 return __cpu_disable();
1278 /*
1279 * XXX: One important thing missed here is to migrate vcpus
1280 * from dead cpu to other online ones and then put whole
1281 * system into a stop state. It assures a safe environment
1282 * for a cpu hotplug/remove at normal running state.
1284 * However for xen PM case, at this point:
1285 * -> All other domains should be notified with PM event,
1286 * and then in following states:
1287 * * Suspend state, or
1288 * * Paused state, which is a force step to all
1289 * domains if they do nothing to suspend
1290 * -> All vcpus of dom0 (except vcpu0) have already beem
1291 * hot removed
1292 * with the net effect that all other cpus only have idle vcpu
1293 * running. In this special case, we can avoid vcpu migration
1294 * then and system can be considered in a stop state.
1296 * So current cpu hotplug is a special version for PM specific
1297 * usage, and need more effort later for full cpu hotplug.
1298 * (ktian1)
1299 */
1300 int cpu_down(unsigned int cpu)
1302 int err = 0;
1304 spin_lock(&cpu_add_remove_lock);
1305 if (num_online_cpus() == 1) {
1306 err = -EBUSY;
1307 goto out;
1310 if (!cpu_online(cpu)) {
1311 err = -EINVAL;
1312 goto out;
1315 printk("Prepare to bring CPU%d down...\n", cpu);
1317 err = stop_machine_run(take_cpu_down, NULL, cpu);
1318 if ( err < 0 )
1319 goto out;
1321 __cpu_die(cpu);
1323 if (cpu_online(cpu)) {
1324 printk("Bad state (DEAD, but in online map) on CPU%d\n", cpu);
1325 err = -EBUSY;
1327 out:
1328 spin_unlock(&cpu_add_remove_lock);
1329 return err;
1332 int cpu_up(unsigned int cpu)
1334 int err = 0;
1336 spin_lock(&cpu_add_remove_lock);
1337 if (cpu_online(cpu)) {
1338 printk("Bring up a online cpu. Bogus!\n");
1339 err = -EBUSY;
1340 goto out;
1343 err = __cpu_up(cpu);
1344 if (err < 0)
1345 goto out;
1347 out:
1348 spin_unlock(&cpu_add_remove_lock);
1349 return err;
1352 /* From kernel/power/main.c */
1353 /* This is protected by pm_sem semaphore */
1354 static cpumask_t frozen_cpus;
1356 void disable_nonboot_cpus(void)
1358 int cpu, error;
1360 error = 0;
1361 cpus_clear(frozen_cpus);
1362 printk("Freezing cpus ...\n");
1363 for_each_online_cpu(cpu) {
1364 if (cpu == 0)
1365 continue;
1366 error = cpu_down(cpu);
1367 if (!error) {
1368 cpu_set(cpu, frozen_cpus);
1369 printk("CPU%d is down\n", cpu);
1370 continue;
1372 printk("Error taking cpu %d down: %d\n", cpu, error);
1374 BUG_ON(raw_smp_processor_id() != 0);
1375 if (error)
1376 panic("cpus not sleeping");
1379 void enable_nonboot_cpus(void)
1381 int cpu, error;
1383 printk("Thawing cpus ...\n");
1384 for_each_cpu_mask(cpu, frozen_cpus) {
1385 error = cpu_up(cpu);
1386 if (!error) {
1387 printk("CPU%d is up\n", cpu);
1388 continue;
1390 printk("Error taking cpu %d up: %d\n", cpu, error);
1391 panic("Not enough cpus");
1393 cpus_clear(frozen_cpus);
1395 /*
1396 * Cleanup possible dangling ends after sleep...
1397 */
1398 smpboot_restore_warm_reset_vector();
1400 #else /* ... !CONFIG_HOTPLUG_CPU */
1401 int __cpu_disable(void)
1403 return -ENOSYS;
1406 void __cpu_die(unsigned int cpu)
1408 /* We said "no" in __cpu_disable */
1409 BUG();
1411 #endif /* CONFIG_HOTPLUG_CPU */
1413 int __devinit __cpu_up(unsigned int cpu)
1415 #ifdef CONFIG_HOTPLUG_CPU
1416 int ret=0;
1418 /*
1419 * We do warm boot only on cpus that had booted earlier
1420 * Otherwise cold boot is all handled from smp_boot_cpus().
1421 * cpu_callin_map is set during AP kickstart process. Its reset
1422 * when a cpu is taken offline from cpu_exit_clear().
1423 */
1424 if (!cpu_isset(cpu, cpu_callin_map))
1425 ret = __smp_prepare_cpu(cpu);
1427 if (ret)
1428 return -EIO;
1429 #endif
1431 /* In case one didn't come up */
1432 if (!cpu_isset(cpu, cpu_callin_map)) {
1433 printk(KERN_DEBUG "skipping cpu%d, didn't come online\n", cpu);
1434 local_irq_enable();
1435 return -EIO;
1438 local_irq_enable();
1439 /*per_cpu(cpu_state, cpu) = CPU_UP_PREPARE;*/
1440 /* Unleash the CPU! */
1441 cpu_set(cpu, smp_commenced_mask);
1442 while (!cpu_isset(cpu, cpu_online_map)) {
1443 mb();
1444 process_pending_timers();
1446 return 0;
1450 void __init smp_cpus_done(unsigned int max_cpus)
1452 #ifdef CONFIG_X86_IO_APIC
1453 setup_ioapic_dest();
1454 #endif
1455 #ifndef CONFIG_HOTPLUG_CPU
1456 /*
1457 * Disable executability of the SMP trampoline:
1458 */
1459 set_kernel_exec((unsigned long)trampoline_base, trampoline_exec);
1460 #endif
1463 void __init smp_intr_init(void)
1465 int irq, seridx;
1467 /*
1468 * IRQ0 must be given a fixed assignment and initialized,
1469 * because it's used before the IO-APIC is set up.
1470 */
1471 irq_vector[0] = FIRST_HIPRIORITY_VECTOR;
1472 vector_irq[FIRST_HIPRIORITY_VECTOR] = 0;
1474 /*
1475 * Also ensure serial interrupts are high priority. We do not
1476 * want them to be blocked by unacknowledged guest-bound interrupts.
1477 */
1478 for (seridx = 0; seridx < 2; seridx++) {
1479 if ((irq = serial_irq(seridx)) < 0)
1480 continue;
1481 irq_vector[irq] = FIRST_HIPRIORITY_VECTOR + seridx + 1;
1482 vector_irq[FIRST_HIPRIORITY_VECTOR + seridx + 1] = irq;
1485 /* IPI for event checking. */
1486 set_intr_gate(EVENT_CHECK_VECTOR, event_check_interrupt);
1488 /* IPI for invalidation */
1489 set_intr_gate(INVALIDATE_TLB_VECTOR, invalidate_interrupt);
1491 /* IPI for generic function call */
1492 set_intr_gate(CALL_FUNCTION_VECTOR, call_function_interrupt);