ia64/xen-unstable

view tools/ioemu/hw/ide.c @ 6529:b5196e075602

Enable multi-word DMA mode 2 for the PIIX3 chipset

Without this patch, Linux PIIX3 driver would see ultra DMA and get confused
and ended up disabling DMA.

With the patch, we're able to see 3x increase in disk read throughput.

Signed-off-by: Winston Wang <winston.l.wang@intel.com>
Signed-off-by: Arun Sharma <arun.sharma@intel.com>
author adsharma@los-vmm.sc.intel.com
date Mon Aug 15 12:28:07 2005 -0800 (2005-08-15)
parents e3dcc10765ea
children 60d20acf8928
line source
1 /*
2 * QEMU IDE disk and CD-ROM Emulator
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "vl.h"
26 /* debug IDE devices */
27 //#define DEBUG_IDE
28 //#define DEBUG_IDE_ATAPI
30 /* Bits of HD_STATUS */
31 #define ERR_STAT 0x01
32 #define INDEX_STAT 0x02
33 #define ECC_STAT 0x04 /* Corrected error */
34 #define DRQ_STAT 0x08
35 #define SEEK_STAT 0x10
36 #define SRV_STAT 0x10
37 #define WRERR_STAT 0x20
38 #define READY_STAT 0x40
39 #define BUSY_STAT 0x80
41 /* Bits for HD_ERROR */
42 #define MARK_ERR 0x01 /* Bad address mark */
43 #define TRK0_ERR 0x02 /* couldn't find track 0 */
44 #define ABRT_ERR 0x04 /* Command aborted */
45 #define MCR_ERR 0x08 /* media change request */
46 #define ID_ERR 0x10 /* ID field not found */
47 #define MC_ERR 0x20 /* media changed */
48 #define ECC_ERR 0x40 /* Uncorrectable ECC error */
49 #define BBD_ERR 0x80 /* pre-EIDE meaning: block marked bad */
50 #define ICRC_ERR 0x80 /* new meaning: CRC error during transfer */
52 /* Bits of HD_NSECTOR */
53 #define CD 0x01
54 #define IO 0x02
55 #define REL 0x04
56 #define TAG_MASK 0xf8
58 #define IDE_CMD_RESET 0x04
59 #define IDE_CMD_DISABLE_IRQ 0x02
61 /* ATA/ATAPI Commands pre T13 Spec */
62 #define WIN_NOP 0x00
63 /*
64 * 0x01->0x02 Reserved
65 */
66 #define CFA_REQ_EXT_ERROR_CODE 0x03 /* CFA Request Extended Error Code */
67 /*
68 * 0x04->0x07 Reserved
69 */
70 #define WIN_SRST 0x08 /* ATAPI soft reset command */
71 #define WIN_DEVICE_RESET 0x08
72 /*
73 * 0x09->0x0F Reserved
74 */
75 #define WIN_RECAL 0x10
76 #define WIN_RESTORE WIN_RECAL
77 /*
78 * 0x10->0x1F Reserved
79 */
80 #define WIN_READ 0x20 /* 28-Bit */
81 #define WIN_READ_ONCE 0x21 /* 28-Bit without retries */
82 #define WIN_READ_LONG 0x22 /* 28-Bit */
83 #define WIN_READ_LONG_ONCE 0x23 /* 28-Bit without retries */
84 #define WIN_READ_EXT 0x24 /* 48-Bit */
85 #define WIN_READDMA_EXT 0x25 /* 48-Bit */
86 #define WIN_READDMA_QUEUED_EXT 0x26 /* 48-Bit */
87 #define WIN_READ_NATIVE_MAX_EXT 0x27 /* 48-Bit */
88 /*
89 * 0x28
90 */
91 #define WIN_MULTREAD_EXT 0x29 /* 48-Bit */
92 /*
93 * 0x2A->0x2F Reserved
94 */
95 #define WIN_WRITE 0x30 /* 28-Bit */
96 #define WIN_WRITE_ONCE 0x31 /* 28-Bit without retries */
97 #define WIN_WRITE_LONG 0x32 /* 28-Bit */
98 #define WIN_WRITE_LONG_ONCE 0x33 /* 28-Bit without retries */
99 #define WIN_WRITE_EXT 0x34 /* 48-Bit */
100 #define WIN_WRITEDMA_EXT 0x35 /* 48-Bit */
101 #define WIN_WRITEDMA_QUEUED_EXT 0x36 /* 48-Bit */
102 #define WIN_SET_MAX_EXT 0x37 /* 48-Bit */
103 #define CFA_WRITE_SECT_WO_ERASE 0x38 /* CFA Write Sectors without erase */
104 #define WIN_MULTWRITE_EXT 0x39 /* 48-Bit */
105 /*
106 * 0x3A->0x3B Reserved
107 */
108 #define WIN_WRITE_VERIFY 0x3C /* 28-Bit */
109 /*
110 * 0x3D->0x3F Reserved
111 */
112 #define WIN_VERIFY 0x40 /* 28-Bit - Read Verify Sectors */
113 #define WIN_VERIFY_ONCE 0x41 /* 28-Bit - without retries */
114 #define WIN_VERIFY_EXT 0x42 /* 48-Bit */
115 /*
116 * 0x43->0x4F Reserved
117 */
118 #define WIN_FORMAT 0x50
119 /*
120 * 0x51->0x5F Reserved
121 */
122 #define WIN_INIT 0x60
123 /*
124 * 0x61->0x5F Reserved
125 */
126 #define WIN_SEEK 0x70 /* 0x70-0x7F Reserved */
127 #define CFA_TRANSLATE_SECTOR 0x87 /* CFA Translate Sector */
128 #define WIN_DIAGNOSE 0x90
129 #define WIN_SPECIFY 0x91 /* set drive geometry translation */
130 #define WIN_DOWNLOAD_MICROCODE 0x92
131 #define WIN_STANDBYNOW2 0x94
132 #define WIN_STANDBY2 0x96
133 #define WIN_SETIDLE2 0x97
134 #define WIN_CHECKPOWERMODE2 0x98
135 #define WIN_SLEEPNOW2 0x99
136 /*
137 * 0x9A VENDOR
138 */
139 #define WIN_PACKETCMD 0xA0 /* Send a packet command. */
140 #define WIN_PIDENTIFY 0xA1 /* identify ATAPI device */
141 #define WIN_QUEUED_SERVICE 0xA2
142 #define WIN_SMART 0xB0 /* self-monitoring and reporting */
143 #define CFA_ERASE_SECTORS 0xC0
144 #define WIN_MULTREAD 0xC4 /* read sectors using multiple mode*/
145 #define WIN_MULTWRITE 0xC5 /* write sectors using multiple mode */
146 #define WIN_SETMULT 0xC6 /* enable/disable multiple mode */
147 #define WIN_READDMA_QUEUED 0xC7 /* read sectors using Queued DMA transfers */
148 #define WIN_READDMA 0xC8 /* read sectors using DMA transfers */
149 #define WIN_READDMA_ONCE 0xC9 /* 28-Bit - without retries */
150 #define WIN_WRITEDMA 0xCA /* write sectors using DMA transfers */
151 #define WIN_WRITEDMA_ONCE 0xCB /* 28-Bit - without retries */
152 #define WIN_WRITEDMA_QUEUED 0xCC /* write sectors using Queued DMA transfers */
153 #define CFA_WRITE_MULTI_WO_ERASE 0xCD /* CFA Write multiple without erase */
154 #define WIN_GETMEDIASTATUS 0xDA
155 #define WIN_ACKMEDIACHANGE 0xDB /* ATA-1, ATA-2 vendor */
156 #define WIN_POSTBOOT 0xDC
157 #define WIN_PREBOOT 0xDD
158 #define WIN_DOORLOCK 0xDE /* lock door on removable drives */
159 #define WIN_DOORUNLOCK 0xDF /* unlock door on removable drives */
160 #define WIN_STANDBYNOW1 0xE0
161 #define WIN_IDLEIMMEDIATE 0xE1 /* force drive to become "ready" */
162 #define WIN_STANDBY 0xE2 /* Set device in Standby Mode */
163 #define WIN_SETIDLE1 0xE3
164 #define WIN_READ_BUFFER 0xE4 /* force read only 1 sector */
165 #define WIN_CHECKPOWERMODE1 0xE5
166 #define WIN_SLEEPNOW1 0xE6
167 #define WIN_FLUSH_CACHE 0xE7
168 #define WIN_WRITE_BUFFER 0xE8 /* force write only 1 sector */
169 #define WIN_WRITE_SAME 0xE9 /* read ata-2 to use */
170 /* SET_FEATURES 0x22 or 0xDD */
171 #define WIN_FLUSH_CACHE_EXT 0xEA /* 48-Bit */
172 #define WIN_IDENTIFY 0xEC /* ask drive to identify itself */
173 #define WIN_MEDIAEJECT 0xED
174 #define WIN_IDENTIFY_DMA 0xEE /* same as WIN_IDENTIFY, but DMA */
175 #define WIN_SETFEATURES 0xEF /* set special drive features */
176 #define EXABYTE_ENABLE_NEST 0xF0
177 #define WIN_SECURITY_SET_PASS 0xF1
178 #define WIN_SECURITY_UNLOCK 0xF2
179 #define WIN_SECURITY_ERASE_PREPARE 0xF3
180 #define WIN_SECURITY_ERASE_UNIT 0xF4
181 #define WIN_SECURITY_FREEZE_LOCK 0xF5
182 #define WIN_SECURITY_DISABLE 0xF6
183 #define WIN_READ_NATIVE_MAX 0xF8 /* return the native maximum address */
184 #define WIN_SET_MAX 0xF9
185 #define DISABLE_SEAGATE 0xFB
187 /* set to 1 set disable mult support */
188 #define MAX_MULT_SECTORS 16
190 /* ATAPI defines */
192 #define ATAPI_PACKET_SIZE 12
194 /* The generic packet command opcodes for CD/DVD Logical Units,
195 * From Table 57 of the SFF8090 Ver. 3 (Mt. Fuji) draft standard. */
196 #define GPCMD_BLANK 0xa1
197 #define GPCMD_CLOSE_TRACK 0x5b
198 #define GPCMD_FLUSH_CACHE 0x35
199 #define GPCMD_FORMAT_UNIT 0x04
200 #define GPCMD_GET_CONFIGURATION 0x46
201 #define GPCMD_GET_EVENT_STATUS_NOTIFICATION 0x4a
202 #define GPCMD_GET_PERFORMANCE 0xac
203 #define GPCMD_INQUIRY 0x12
204 #define GPCMD_LOAD_UNLOAD 0xa6
205 #define GPCMD_MECHANISM_STATUS 0xbd
206 #define GPCMD_MODE_SELECT_10 0x55
207 #define GPCMD_MODE_SENSE_10 0x5a
208 #define GPCMD_PAUSE_RESUME 0x4b
209 #define GPCMD_PLAY_AUDIO_10 0x45
210 #define GPCMD_PLAY_AUDIO_MSF 0x47
211 #define GPCMD_PLAY_AUDIO_TI 0x48
212 #define GPCMD_PLAY_CD 0xbc
213 #define GPCMD_PREVENT_ALLOW_MEDIUM_REMOVAL 0x1e
214 #define GPCMD_READ_10 0x28
215 #define GPCMD_READ_12 0xa8
216 #define GPCMD_READ_CDVD_CAPACITY 0x25
217 #define GPCMD_READ_CD 0xbe
218 #define GPCMD_READ_CD_MSF 0xb9
219 #define GPCMD_READ_DISC_INFO 0x51
220 #define GPCMD_READ_DVD_STRUCTURE 0xad
221 #define GPCMD_READ_FORMAT_CAPACITIES 0x23
222 #define GPCMD_READ_HEADER 0x44
223 #define GPCMD_READ_TRACK_RZONE_INFO 0x52
224 #define GPCMD_READ_SUBCHANNEL 0x42
225 #define GPCMD_READ_TOC_PMA_ATIP 0x43
226 #define GPCMD_REPAIR_RZONE_TRACK 0x58
227 #define GPCMD_REPORT_KEY 0xa4
228 #define GPCMD_REQUEST_SENSE 0x03
229 #define GPCMD_RESERVE_RZONE_TRACK 0x53
230 #define GPCMD_SCAN 0xba
231 #define GPCMD_SEEK 0x2b
232 #define GPCMD_SEND_DVD_STRUCTURE 0xad
233 #define GPCMD_SEND_EVENT 0xa2
234 #define GPCMD_SEND_KEY 0xa3
235 #define GPCMD_SEND_OPC 0x54
236 #define GPCMD_SET_READ_AHEAD 0xa7
237 #define GPCMD_SET_STREAMING 0xb6
238 #define GPCMD_START_STOP_UNIT 0x1b
239 #define GPCMD_STOP_PLAY_SCAN 0x4e
240 #define GPCMD_TEST_UNIT_READY 0x00
241 #define GPCMD_VERIFY_10 0x2f
242 #define GPCMD_WRITE_10 0x2a
243 #define GPCMD_WRITE_AND_VERIFY_10 0x2e
244 /* This is listed as optional in ATAPI 2.6, but is (curiously)
245 * missing from Mt. Fuji, Table 57. It _is_ mentioned in Mt. Fuji
246 * Table 377 as an MMC command for SCSi devices though... Most ATAPI
247 * drives support it. */
248 #define GPCMD_SET_SPEED 0xbb
249 /* This seems to be a SCSI specific CD-ROM opcode
250 * to play data at track/index */
251 #define GPCMD_PLAYAUDIO_TI 0x48
252 /*
253 * From MS Media Status Notification Support Specification. For
254 * older drives only.
255 */
256 #define GPCMD_GET_MEDIA_STATUS 0xda
258 /* Mode page codes for mode sense/set */
259 #define GPMODE_R_W_ERROR_PAGE 0x01
260 #define GPMODE_WRITE_PARMS_PAGE 0x05
261 #define GPMODE_AUDIO_CTL_PAGE 0x0e
262 #define GPMODE_POWER_PAGE 0x1a
263 #define GPMODE_FAULT_FAIL_PAGE 0x1c
264 #define GPMODE_TO_PROTECT_PAGE 0x1d
265 #define GPMODE_CAPABILITIES_PAGE 0x2a
266 #define GPMODE_ALL_PAGES 0x3f
267 /* Not in Mt. Fuji, but in ATAPI 2.6 -- depricated now in favor
268 * of MODE_SENSE_POWER_PAGE */
269 #define GPMODE_CDROM_PAGE 0x0d
271 #define ATAPI_INT_REASON_CD 0x01 /* 0 = data transfer */
272 #define ATAPI_INT_REASON_IO 0x02 /* 1 = transfer to the host */
273 #define ATAPI_INT_REASON_REL 0x04
274 #define ATAPI_INT_REASON_TAG 0xf8
276 /* same constants as bochs */
277 #define ASC_ILLEGAL_OPCODE 0x20
278 #define ASC_LOGICAL_BLOCK_OOR 0x21
279 #define ASC_INV_FIELD_IN_CMD_PACKET 0x24
280 #define ASC_MEDIUM_NOT_PRESENT 0x3a
281 #define ASC_SAVING_PARAMETERS_NOT_SUPPORTED 0x39
283 #define SENSE_NONE 0
284 #define SENSE_NOT_READY 2
285 #define SENSE_ILLEGAL_REQUEST 5
286 #define SENSE_UNIT_ATTENTION 6
288 struct IDEState;
290 typedef void EndTransferFunc(struct IDEState *);
292 /* NOTE: IDEState represents in fact one drive */
293 typedef struct IDEState {
294 /* ide config */
295 int is_cdrom;
296 int cylinders, heads, sectors;
297 int64_t nb_sectors;
298 int mult_sectors;
299 int irq;
300 openpic_t *openpic;
301 PCIDevice *pci_dev;
302 struct BMDMAState *bmdma;
303 int drive_serial;
304 /* ide regs */
305 uint8_t feature;
306 uint8_t error;
307 uint16_t nsector; /* 0 is 256 to ease computations */
308 uint8_t sector;
309 uint8_t lcyl;
310 uint8_t hcyl;
311 uint8_t select;
312 uint8_t status;
313 /* 0x3f6 command, only meaningful for drive 0 */
314 uint8_t cmd;
315 /* depends on bit 4 in select, only meaningful for drive 0 */
316 struct IDEState *cur_drive;
317 BlockDriverState *bs;
318 /* ATAPI specific */
319 uint8_t sense_key;
320 uint8_t asc;
321 int packet_transfer_size;
322 int elementary_transfer_size;
323 int io_buffer_index;
324 int lba;
325 int cd_sector_size;
326 int atapi_dma; /* true if dma is requested for the packet cmd */
327 /* ATA DMA state */
328 int io_buffer_size;
329 /* PIO transfer handling */
330 int req_nb_sectors; /* number of sectors per interrupt */
331 EndTransferFunc *end_transfer_func;
332 uint8_t *data_ptr;
333 uint8_t *data_end;
334 uint8_t io_buffer[MAX_MULT_SECTORS*512 + 4];
335 } IDEState;
337 #define BM_STATUS_DMAING 0x01
338 #define BM_STATUS_ERROR 0x02
339 #define BM_STATUS_INT 0x04
341 #define BM_CMD_START 0x01
342 #define BM_CMD_READ 0x08
344 typedef int IDEDMAFunc(IDEState *s,
345 target_phys_addr_t phys_addr,
346 int transfer_size1);
348 typedef struct BMDMAState {
349 uint8_t cmd;
350 uint8_t status;
351 uint32_t addr;
352 /* current transfer state */
353 IDEState *ide_if;
354 IDEDMAFunc *dma_cb;
355 } BMDMAState;
357 typedef struct PCIIDEState {
358 PCIDevice dev;
359 IDEState ide_if[4];
360 BMDMAState bmdma[2];
361 } PCIIDEState;
363 static void ide_dma_start(IDEState *s, IDEDMAFunc *dma_cb);
365 static void padstr(char *str, const char *src, int len)
366 {
367 int i, v;
368 for(i = 0; i < len; i++) {
369 if (*src)
370 v = *src++;
371 else
372 v = ' ';
373 *(char *)((long)str ^ 1) = v;
374 str++;
375 }
376 }
378 static void padstr8(uint8_t *buf, int buf_size, const char *src)
379 {
380 int i;
381 for(i = 0; i < buf_size; i++) {
382 if (*src)
383 buf[i] = *src++;
384 else
385 buf[i] = ' ';
386 }
387 }
389 static void put_le16(uint16_t *p, unsigned int v)
390 {
391 *p = cpu_to_le16(v);
392 }
394 static void ide_identify(IDEState *s)
395 {
396 uint16_t *p;
397 unsigned int oldsize;
398 char buf[20];
400 memset(s->io_buffer, 0, 512);
401 p = (uint16_t *)s->io_buffer;
402 put_le16(p + 0, 0x0040);
403 put_le16(p + 1, s->cylinders);
404 put_le16(p + 3, s->heads);
405 put_le16(p + 4, 512 * s->sectors); /* XXX: retired, remove ? */
406 put_le16(p + 5, 512); /* XXX: retired, remove ? */
407 put_le16(p + 6, s->sectors);
408 snprintf(buf, sizeof(buf), "QM%05d", s->drive_serial);
409 padstr((uint8_t *)(p + 10), buf, 20); /* serial number */
410 put_le16(p + 20, 3); /* XXX: retired, remove ? */
411 put_le16(p + 21, 512); /* cache size in sectors */
412 put_le16(p + 22, 4); /* ecc bytes */
413 padstr((uint8_t *)(p + 23), QEMU_VERSION, 8); /* firmware version */
414 padstr((uint8_t *)(p + 27), "QEMU HARDDISK", 40); /* model */
415 #if MAX_MULT_SECTORS > 1
416 put_le16(p + 47, 0x8000 | MAX_MULT_SECTORS);
417 #endif
418 put_le16(p + 48, 1); /* dword I/O */
419 put_le16(p + 49, 1 << 9 | 1 << 8); /* DMA and LBA supported */
420 put_le16(p + 51, 0x200); /* PIO transfer cycle */
421 put_le16(p + 52, 0x200); /* DMA transfer cycle */
422 put_le16(p + 53, 1 | 1 << 2); /* words 54-58,88 are valid */
423 put_le16(p + 54, s->cylinders);
424 put_le16(p + 55, s->heads);
425 put_le16(p + 56, s->sectors);
426 oldsize = s->cylinders * s->heads * s->sectors;
427 put_le16(p + 57, oldsize);
428 put_le16(p + 58, oldsize >> 16);
429 if (s->mult_sectors)
430 put_le16(p + 59, 0x100 | s->mult_sectors);
431 put_le16(p + 60, s->nb_sectors);
432 put_le16(p + 61, s->nb_sectors >> 16);
433 put_le16(p + 63, 0x07);
434 put_le16(p + 80, (1 << 1) | (1 << 2));
435 put_le16(p + 82, (1 << 14));
436 put_le16(p + 83, (1 << 14));
437 put_le16(p + 84, (1 << 14));
438 put_le16(p + 85, (1 << 14));
439 put_le16(p + 86, 0);
440 put_le16(p + 87, (1 << 14));
441 put_le16(p + 88, 0x1f | (1 << 13));
442 put_le16(p + 93, 1 | (1 << 14) | 0x2000 | 0x4000);
443 }
445 static void ide_atapi_identify(IDEState *s)
446 {
447 uint16_t *p;
448 char buf[20];
450 memset(s->io_buffer, 0, 512);
451 p = (uint16_t *)s->io_buffer;
452 /* Removable CDROM, 50us response, 12 byte packets */
453 put_le16(p + 0, (2 << 14) | (5 << 8) | (1 << 7) | (2 << 5) | (0 << 0));
454 snprintf(buf, sizeof(buf), "QM%05d", s->drive_serial);
455 padstr((uint8_t *)(p + 10), buf, 20); /* serial number */
456 put_le16(p + 20, 3); /* buffer type */
457 put_le16(p + 21, 512); /* cache size in sectors */
458 put_le16(p + 22, 4); /* ecc bytes */
459 padstr((uint8_t *)(p + 23), QEMU_VERSION, 8); /* firmware version */
460 padstr((uint8_t *)(p + 27), "QEMU CD-ROM", 40); /* model */
461 put_le16(p + 48, 1); /* dword I/O (XXX: should not be set on CDROM) */
462 put_le16(p + 49, 1 << 9); /* LBA supported, no DMA */
463 put_le16(p + 53, 3); /* words 64-70, 54-58 valid */
464 put_le16(p + 63, 0x07); /* Multi-word DMA mode 2 */
465 put_le16(p + 64, 1); /* PIO modes */
466 put_le16(p + 65, 0xb4); /* minimum DMA multiword tx cycle time */
467 put_le16(p + 66, 0xb4); /* recommended DMA multiword tx cycle time */
468 put_le16(p + 67, 0x12c); /* minimum PIO cycle time without flow control */
469 put_le16(p + 68, 0xb4); /* minimum PIO cycle time with IORDY flow control */
471 put_le16(p + 71, 30); /* in ns */
472 put_le16(p + 72, 30); /* in ns */
474 put_le16(p + 80, 0x1e); /* support up to ATA/ATAPI-4 */
475 }
477 static void ide_set_signature(IDEState *s)
478 {
479 s->select &= 0xf0; /* clear head */
480 /* put signature */
481 s->nsector = 1;
482 s->sector = 1;
483 if (s->is_cdrom) {
484 s->lcyl = 0x14;
485 s->hcyl = 0xeb;
486 } else if (s->bs) {
487 s->lcyl = 0;
488 s->hcyl = 0;
489 } else {
490 s->lcyl = 0xff;
491 s->hcyl = 0xff;
492 }
493 }
495 static inline void ide_abort_command(IDEState *s)
496 {
497 s->status = READY_STAT | ERR_STAT;
498 s->error = ABRT_ERR;
499 }
501 static inline void ide_set_irq(IDEState *s)
502 {
503 if (!(s->cmd & IDE_CMD_DISABLE_IRQ)) {
504 #ifdef TARGET_PPC
505 if (s->openpic)
506 openpic_set_irq(s->openpic, s->irq, 1);
507 else
508 #endif
509 if (s->irq == 16)
510 pci_set_irq(s->pci_dev, 0, 1);
511 else
512 pic_set_irq(s->irq, 1);
513 }
514 }
516 /* prepare data transfer and tell what to do after */
517 static void ide_transfer_start(IDEState *s, uint8_t *buf, int size,
518 EndTransferFunc *end_transfer_func)
519 {
520 s->end_transfer_func = end_transfer_func;
521 s->data_ptr = buf;
522 s->data_end = buf + size;
523 s->status |= DRQ_STAT;
524 }
526 static void ide_transfer_stop(IDEState *s)
527 {
528 s->end_transfer_func = ide_transfer_stop;
529 s->data_ptr = s->io_buffer;
530 s->data_end = s->io_buffer;
531 s->status &= ~DRQ_STAT;
532 }
534 static int64_t ide_get_sector(IDEState *s)
535 {
536 int64_t sector_num;
537 if (s->select & 0x40) {
538 /* lba */
539 sector_num = ((s->select & 0x0f) << 24) | (s->hcyl << 16) |
540 (s->lcyl << 8) | s->sector;
541 } else {
542 sector_num = ((s->hcyl << 8) | s->lcyl) * s->heads * s->sectors +
543 (s->select & 0x0f) * s->sectors +
544 (s->sector - 1);
545 }
546 return sector_num;
547 }
549 static void ide_set_sector(IDEState *s, int64_t sector_num)
550 {
551 unsigned int cyl, r;
552 if (s->select & 0x40) {
553 s->select = (s->select & 0xf0) | (sector_num >> 24);
554 s->hcyl = (sector_num >> 16);
555 s->lcyl = (sector_num >> 8);
556 s->sector = (sector_num);
557 } else {
558 cyl = sector_num / (s->heads * s->sectors);
559 r = sector_num % (s->heads * s->sectors);
560 s->hcyl = cyl >> 8;
561 s->lcyl = cyl;
562 s->select = (s->select & 0xf0) | ((r / s->sectors) & 0x0f);
563 s->sector = (r % s->sectors) + 1;
564 }
565 }
567 static void ide_sector_read(IDEState *s)
568 {
569 int64_t sector_num;
570 int ret, n;
572 s->status = READY_STAT | SEEK_STAT;
573 s->error = 0; /* not needed by IDE spec, but needed by Windows */
574 sector_num = ide_get_sector(s);
575 n = s->nsector;
576 if (n == 0) {
577 /* no more sector to read from disk */
578 ide_transfer_stop(s);
579 } else {
580 #if defined(DEBUG_IDE)
581 printf("read sector=%Ld\n", sector_num);
582 #endif
583 if (n > s->req_nb_sectors)
584 n = s->req_nb_sectors;
585 ret = bdrv_read(s->bs, sector_num, s->io_buffer, n);
586 ide_transfer_start(s, s->io_buffer, 512 * n, ide_sector_read);
587 ide_set_irq(s);
588 ide_set_sector(s, sector_num + n);
589 s->nsector -= n;
590 }
591 }
593 static int ide_read_dma_cb(IDEState *s,
594 target_phys_addr_t phys_addr,
595 int transfer_size1)
596 {
597 int len, transfer_size, n;
598 int64_t sector_num;
600 transfer_size = transfer_size1;
601 while (transfer_size > 0) {
602 len = s->io_buffer_size - s->io_buffer_index;
603 if (len <= 0) {
604 /* transfert next data */
605 n = s->nsector;
606 if (n == 0)
607 break;
608 if (n > MAX_MULT_SECTORS)
609 n = MAX_MULT_SECTORS;
610 sector_num = ide_get_sector(s);
611 bdrv_read(s->bs, sector_num, s->io_buffer, n);
612 s->io_buffer_index = 0;
613 s->io_buffer_size = n * 512;
614 len = s->io_buffer_size;
615 sector_num += n;
616 ide_set_sector(s, sector_num);
617 s->nsector -= n;
618 }
619 if (len > transfer_size)
620 len = transfer_size;
621 cpu_physical_memory_write(phys_addr,
622 s->io_buffer + s->io_buffer_index, len);
623 s->io_buffer_index += len;
624 transfer_size -= len;
625 phys_addr += len;
626 }
627 if (s->io_buffer_index >= s->io_buffer_size && s->nsector == 0) {
628 s->status = READY_STAT | SEEK_STAT;
629 ide_set_irq(s);
630 #ifdef DEBUG_IDE_ATAPI
631 printf("dma status=0x%x\n", s->status);
632 #endif
633 return 0;
634 }
635 return transfer_size1 - transfer_size;
636 }
638 static void ide_sector_read_dma(IDEState *s)
639 {
640 s->status = READY_STAT | SEEK_STAT | DRQ_STAT;
641 s->io_buffer_index = 0;
642 s->io_buffer_size = 0;
643 ide_dma_start(s, ide_read_dma_cb);
644 }
646 static void ide_sector_write(IDEState *s)
647 {
648 int64_t sector_num;
649 int ret, n, n1;
651 s->status = READY_STAT | SEEK_STAT;
652 sector_num = ide_get_sector(s);
653 #if defined(DEBUG_IDE)
654 printf("write sector=%Ld\n", sector_num);
655 #endif
656 n = s->nsector;
657 if (n > s->req_nb_sectors)
658 n = s->req_nb_sectors;
659 ret = bdrv_write(s->bs, sector_num, s->io_buffer, n);
660 s->nsector -= n;
661 if (s->nsector == 0) {
662 /* no more sector to write */
663 ide_transfer_stop(s);
664 } else {
665 n1 = s->nsector;
666 if (n1 > s->req_nb_sectors)
667 n1 = s->req_nb_sectors;
668 ide_transfer_start(s, s->io_buffer, 512 * n1, ide_sector_write);
669 }
670 ide_set_sector(s, sector_num + n);
671 ide_set_irq(s);
672 }
674 static int ide_write_dma_cb(IDEState *s,
675 target_phys_addr_t phys_addr,
676 int transfer_size1)
677 {
678 int len, transfer_size, n;
679 int64_t sector_num;
681 transfer_size = transfer_size1;
682 for(;;) {
683 len = s->io_buffer_size - s->io_buffer_index;
684 if (len == 0) {
685 n = s->io_buffer_size >> 9;
686 sector_num = ide_get_sector(s);
687 bdrv_write(s->bs, sector_num, s->io_buffer,
688 s->io_buffer_size >> 9);
689 sector_num += n;
690 ide_set_sector(s, sector_num);
691 s->nsector -= n;
692 n = s->nsector;
693 if (n == 0) {
694 /* end of transfer */
695 s->status = READY_STAT | SEEK_STAT;
696 ide_set_irq(s);
697 return 0;
698 }
699 if (n > MAX_MULT_SECTORS)
700 n = MAX_MULT_SECTORS;
701 s->io_buffer_index = 0;
702 s->io_buffer_size = n * 512;
703 len = s->io_buffer_size;
704 }
705 if (transfer_size <= 0)
706 break;
707 if (len > transfer_size)
708 len = transfer_size;
709 cpu_physical_memory_read(phys_addr,
710 s->io_buffer + s->io_buffer_index, len);
711 s->io_buffer_index += len;
712 transfer_size -= len;
713 phys_addr += len;
714 }
715 return transfer_size1 - transfer_size;
716 }
718 static void ide_sector_write_dma(IDEState *s)
719 {
720 int n;
721 s->status = READY_STAT | SEEK_STAT | DRQ_STAT;
722 n = s->nsector;
723 if (n > MAX_MULT_SECTORS)
724 n = MAX_MULT_SECTORS;
725 s->io_buffer_index = 0;
726 s->io_buffer_size = n * 512;
727 ide_dma_start(s, ide_write_dma_cb);
728 }
730 static void ide_atapi_cmd_ok(IDEState *s)
731 {
732 s->error = 0;
733 s->status = READY_STAT;
734 s->nsector = (s->nsector & ~7) | ATAPI_INT_REASON_IO | ATAPI_INT_REASON_CD;
735 ide_set_irq(s);
736 }
738 static void ide_atapi_cmd_error(IDEState *s, int sense_key, int asc)
739 {
740 #ifdef DEBUG_IDE_ATAPI
741 printf("atapi_cmd_error: sense=0x%x asc=0x%x\n", sense_key, asc);
742 #endif
743 s->error = sense_key << 4;
744 s->status = READY_STAT | ERR_STAT;
745 s->nsector = (s->nsector & ~7) | ATAPI_INT_REASON_IO | ATAPI_INT_REASON_CD;
746 s->sense_key = sense_key;
747 s->asc = asc;
748 ide_set_irq(s);
749 }
751 static inline void cpu_to_ube16(uint8_t *buf, int val)
752 {
753 buf[0] = val >> 8;
754 buf[1] = val;
755 }
757 static inline void cpu_to_ube32(uint8_t *buf, unsigned int val)
758 {
759 buf[0] = val >> 24;
760 buf[1] = val >> 16;
761 buf[2] = val >> 8;
762 buf[3] = val;
763 }
765 static inline int ube16_to_cpu(const uint8_t *buf)
766 {
767 return (buf[0] << 8) | buf[1];
768 }
770 static inline int ube32_to_cpu(const uint8_t *buf)
771 {
772 return (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3];
773 }
775 static void lba_to_msf(uint8_t *buf, int lba)
776 {
777 lba += 150;
778 buf[0] = (lba / 75) / 60;
779 buf[1] = (lba / 75) % 60;
780 buf[2] = lba % 75;
781 }
783 static void cd_read_sector(BlockDriverState *bs, int lba, uint8_t *buf,
784 int sector_size)
785 {
786 switch(sector_size) {
787 case 2048:
788 bdrv_read(bs, (int64_t)lba << 2, buf, 4);
789 break;
790 case 2352:
791 /* sync bytes */
792 buf[0] = 0x00;
793 memset(buf + 1, 0xff, 11);
794 buf += 12;
795 /* MSF */
796 lba_to_msf(buf, lba);
797 buf[3] = 0x01; /* mode 1 data */
798 buf += 4;
799 /* data */
800 bdrv_read(bs, (int64_t)lba << 2, buf, 4);
801 buf += 2048;
802 /* ECC */
803 memset(buf, 0, 288);
804 break;
805 default:
806 break;
807 }
808 }
810 /* The whole ATAPI transfer logic is handled in this function */
811 static void ide_atapi_cmd_reply_end(IDEState *s)
812 {
813 int byte_count_limit, size;
814 #ifdef DEBUG_IDE_ATAPI
815 printf("reply: tx_size=%d elem_tx_size=%d index=%d\n",
816 s->packet_transfer_size,
817 s->elementary_transfer_size,
818 s->io_buffer_index);
819 #endif
820 if (s->packet_transfer_size <= 0) {
821 /* end of transfer */
822 ide_transfer_stop(s);
823 s->status = READY_STAT;
824 s->nsector = (s->nsector & ~7) | ATAPI_INT_REASON_IO | ATAPI_INT_REASON_CD;
825 ide_set_irq(s);
826 #ifdef DEBUG_IDE_ATAPI
827 printf("status=0x%x\n", s->status);
828 #endif
829 } else {
830 /* see if a new sector must be read */
831 if (s->lba != -1 && s->io_buffer_index >= s->cd_sector_size) {
832 cd_read_sector(s->bs, s->lba, s->io_buffer, s->cd_sector_size);
833 s->lba++;
834 s->io_buffer_index = 0;
835 }
836 if (s->elementary_transfer_size > 0) {
837 /* there are some data left to transmit in this elementary
838 transfer */
839 size = s->cd_sector_size - s->io_buffer_index;
840 if (size > s->elementary_transfer_size)
841 size = s->elementary_transfer_size;
842 ide_transfer_start(s, s->io_buffer + s->io_buffer_index,
843 size, ide_atapi_cmd_reply_end);
844 s->packet_transfer_size -= size;
845 s->elementary_transfer_size -= size;
846 s->io_buffer_index += size;
847 } else {
848 /* a new transfer is needed */
849 s->nsector = (s->nsector & ~7) | ATAPI_INT_REASON_IO;
850 byte_count_limit = s->lcyl | (s->hcyl << 8);
851 #ifdef DEBUG_IDE_ATAPI
852 printf("byte_count_limit=%d\n", byte_count_limit);
853 #endif
854 if (byte_count_limit == 0xffff)
855 byte_count_limit--;
856 size = s->packet_transfer_size;
857 if (size > byte_count_limit) {
858 /* byte count limit must be even if this case */
859 if (byte_count_limit & 1)
860 byte_count_limit--;
861 size = byte_count_limit;
862 }
863 s->lcyl = size;
864 s->hcyl = size >> 8;
865 s->elementary_transfer_size = size;
866 /* we cannot transmit more than one sector at a time */
867 if (s->lba != -1) {
868 if (size > (s->cd_sector_size - s->io_buffer_index))
869 size = (s->cd_sector_size - s->io_buffer_index);
870 }
871 ide_transfer_start(s, s->io_buffer + s->io_buffer_index,
872 size, ide_atapi_cmd_reply_end);
873 s->packet_transfer_size -= size;
874 s->elementary_transfer_size -= size;
875 s->io_buffer_index += size;
876 ide_set_irq(s);
877 #ifdef DEBUG_IDE_ATAPI
878 printf("status=0x%x\n", s->status);
879 #endif
880 }
881 }
882 }
884 /* send a reply of 'size' bytes in s->io_buffer to an ATAPI command */
885 static void ide_atapi_cmd_reply(IDEState *s, int size, int max_size)
886 {
887 if (size > max_size)
888 size = max_size;
889 s->lba = -1; /* no sector read */
890 s->packet_transfer_size = size;
891 s->elementary_transfer_size = 0;
892 s->io_buffer_index = 0;
894 s->status = READY_STAT;
895 ide_atapi_cmd_reply_end(s);
896 }
898 /* start a CD-CDROM read command */
899 static void ide_atapi_cmd_read_pio(IDEState *s, int lba, int nb_sectors,
900 int sector_size)
901 {
902 s->lba = lba;
903 s->packet_transfer_size = nb_sectors * sector_size;
904 s->elementary_transfer_size = 0;
905 s->io_buffer_index = sector_size;
906 s->cd_sector_size = sector_size;
908 s->status = READY_STAT;
909 ide_atapi_cmd_reply_end(s);
910 }
912 /* ATAPI DMA support */
913 static int ide_atapi_cmd_read_dma_cb(IDEState *s,
914 target_phys_addr_t phys_addr,
915 int transfer_size1)
916 {
917 int len, transfer_size;
919 transfer_size = transfer_size1;
920 while (transfer_size > 0) {
921 if (s->packet_transfer_size <= 0)
922 break;
923 len = s->cd_sector_size - s->io_buffer_index;
924 if (len <= 0) {
925 /* transfert next data */
926 cd_read_sector(s->bs, s->lba, s->io_buffer, s->cd_sector_size);
927 s->lba++;
928 s->io_buffer_index = 0;
929 len = s->cd_sector_size;
930 }
931 if (len > transfer_size)
932 len = transfer_size;
933 cpu_physical_memory_write(phys_addr,
934 s->io_buffer + s->io_buffer_index, len);
935 s->packet_transfer_size -= len;
936 s->io_buffer_index += len;
937 transfer_size -= len;
938 phys_addr += len;
939 }
940 if (s->packet_transfer_size <= 0) {
941 s->status = READY_STAT;
942 s->nsector = (s->nsector & ~7) | ATAPI_INT_REASON_IO | ATAPI_INT_REASON_CD;
943 ide_set_irq(s);
944 #ifdef DEBUG_IDE_ATAPI
945 printf("dma status=0x%x\n", s->status);
946 #endif
947 return 0;
948 }
949 return transfer_size1 - transfer_size;
950 }
952 /* start a CD-CDROM read command with DMA */
953 /* XXX: test if DMA is available */
954 static void ide_atapi_cmd_read_dma(IDEState *s, int lba, int nb_sectors,
955 int sector_size)
956 {
957 s->lba = lba;
958 s->packet_transfer_size = nb_sectors * sector_size;
959 s->io_buffer_index = sector_size;
960 s->cd_sector_size = sector_size;
962 s->status = READY_STAT | DRQ_STAT;
963 ide_dma_start(s, ide_atapi_cmd_read_dma_cb);
964 }
966 static void ide_atapi_cmd_read(IDEState *s, int lba, int nb_sectors,
967 int sector_size)
968 {
969 #ifdef DEBUG_IDE_ATAPI
970 printf("read: LBA=%d nb_sectors=%d\n", lba, nb_sectors);
971 #endif
972 if (s->atapi_dma) {
973 ide_atapi_cmd_read_dma(s, lba, nb_sectors, sector_size);
974 } else {
975 ide_atapi_cmd_read_pio(s, lba, nb_sectors, sector_size);
976 }
977 }
979 /* same toc as bochs. Return -1 if error or the toc length */
980 /* XXX: check this */
981 static int cdrom_read_toc(IDEState *s, uint8_t *buf, int msf, int start_track)
982 {
983 uint8_t *q;
984 int nb_sectors, len;
986 if (start_track > 1 && start_track != 0xaa)
987 return -1;
988 q = buf + 2;
989 *q++ = 1; /* first session */
990 *q++ = 1; /* last session */
991 if (start_track <= 1) {
992 *q++ = 0; /* reserved */
993 *q++ = 0x14; /* ADR, control */
994 *q++ = 1; /* track number */
995 *q++ = 0; /* reserved */
996 if (msf) {
997 *q++ = 0; /* reserved */
998 *q++ = 0; /* minute */
999 *q++ = 2; /* second */
1000 *q++ = 0; /* frame */
1001 } else {
1002 /* sector 0 */
1003 cpu_to_ube32(q, 0);
1004 q += 4;
1007 /* lead out track */
1008 *q++ = 0; /* reserved */
1009 *q++ = 0x16; /* ADR, control */
1010 *q++ = 0xaa; /* track number */
1011 *q++ = 0; /* reserved */
1012 nb_sectors = s->nb_sectors >> 2;
1013 if (msf) {
1014 *q++ = 0; /* reserved */
1015 lba_to_msf(q, nb_sectors);
1016 q += 3;
1017 } else {
1018 cpu_to_ube32(q, nb_sectors);
1019 q += 4;
1021 len = q - buf;
1022 cpu_to_ube16(buf, len - 2);
1023 return len;
1026 /* mostly same info as PearPc */
1027 static int cdrom_read_toc_raw(IDEState *s, uint8_t *buf, int msf,
1028 int session_num)
1030 uint8_t *q;
1031 int nb_sectors, len;
1033 q = buf + 2;
1034 *q++ = 1; /* first session */
1035 *q++ = 1; /* last session */
1037 *q++ = 1; /* session number */
1038 *q++ = 0x14; /* data track */
1039 *q++ = 0; /* track number */
1040 *q++ = 0xa0; /* lead-in */
1041 *q++ = 0; /* min */
1042 *q++ = 0; /* sec */
1043 *q++ = 0; /* frame */
1044 *q++ = 0;
1045 *q++ = 1; /* first track */
1046 *q++ = 0x00; /* disk type */
1047 *q++ = 0x00;
1049 *q++ = 1; /* session number */
1050 *q++ = 0x14; /* data track */
1051 *q++ = 0; /* track number */
1052 *q++ = 0xa1;
1053 *q++ = 0; /* min */
1054 *q++ = 0; /* sec */
1055 *q++ = 0; /* frame */
1056 *q++ = 0;
1057 *q++ = 1; /* last track */
1058 *q++ = 0x00;
1059 *q++ = 0x00;
1061 *q++ = 1; /* session number */
1062 *q++ = 0x14; /* data track */
1063 *q++ = 0; /* track number */
1064 *q++ = 0xa2; /* lead-out */
1065 *q++ = 0; /* min */
1066 *q++ = 0; /* sec */
1067 *q++ = 0; /* frame */
1068 nb_sectors = s->nb_sectors >> 2;
1069 if (msf) {
1070 *q++ = 0; /* reserved */
1071 lba_to_msf(q, nb_sectors);
1072 q += 3;
1073 } else {
1074 cpu_to_ube32(q, nb_sectors);
1075 q += 4;
1078 *q++ = 1; /* session number */
1079 *q++ = 0x14; /* ADR, control */
1080 *q++ = 0; /* track number */
1081 *q++ = 1; /* point */
1082 *q++ = 0; /* min */
1083 *q++ = 0; /* sec */
1084 *q++ = 0; /* frame */
1085 *q++ = 0;
1086 *q++ = 0;
1087 *q++ = 0;
1088 *q++ = 0;
1090 len = q - buf;
1091 cpu_to_ube16(buf, len - 2);
1092 return len;
1095 static void ide_atapi_cmd(IDEState *s)
1097 const uint8_t *packet;
1098 uint8_t *buf;
1099 int max_len;
1101 packet = s->io_buffer;
1102 buf = s->io_buffer;
1103 #ifdef DEBUG_IDE_ATAPI
1105 int i;
1106 printf("ATAPI limit=0x%x packet:", s->lcyl | (s->hcyl << 8));
1107 for(i = 0; i < ATAPI_PACKET_SIZE; i++) {
1108 printf(" %02x", packet[i]);
1110 printf("\n");
1112 #endif
1113 switch(s->io_buffer[0]) {
1114 case GPCMD_TEST_UNIT_READY:
1115 if (bdrv_is_inserted(s->bs)) {
1116 ide_atapi_cmd_ok(s);
1117 } else {
1118 ide_atapi_cmd_error(s, SENSE_NOT_READY,
1119 ASC_MEDIUM_NOT_PRESENT);
1121 break;
1122 case GPCMD_MODE_SENSE_10:
1124 int action, code;
1125 max_len = ube16_to_cpu(packet + 7);
1126 action = packet[2] >> 6;
1127 code = packet[2] & 0x3f;
1128 switch(action) {
1129 case 0: /* current values */
1130 switch(code) {
1131 case 0x01: /* error recovery */
1132 cpu_to_ube16(&buf[0], 16 + 6);
1133 buf[2] = 0x70;
1134 buf[3] = 0;
1135 buf[4] = 0;
1136 buf[5] = 0;
1137 buf[6] = 0;
1138 buf[7] = 0;
1140 buf[8] = 0x01;
1141 buf[9] = 0x06;
1142 buf[10] = 0x00;
1143 buf[11] = 0x05;
1144 buf[12] = 0x00;
1145 buf[13] = 0x00;
1146 buf[14] = 0x00;
1147 buf[15] = 0x00;
1148 ide_atapi_cmd_reply(s, 16, max_len);
1149 break;
1150 case 0x2a:
1151 cpu_to_ube16(&buf[0], 28 + 6);
1152 buf[2] = 0x70;
1153 buf[3] = 0;
1154 buf[4] = 0;
1155 buf[5] = 0;
1156 buf[6] = 0;
1157 buf[7] = 0;
1159 buf[8] = 0x2a;
1160 buf[9] = 0x12;
1161 buf[10] = 0x00;
1162 buf[11] = 0x00;
1164 buf[12] = 0x70;
1165 buf[13] = 3 << 5;
1166 buf[14] = (1 << 0) | (1 << 3) | (1 << 5);
1167 if (bdrv_is_locked(s->bs))
1168 buf[6] |= 1 << 1;
1169 buf[15] = 0x00;
1170 cpu_to_ube16(&buf[16], 706);
1171 buf[18] = 0;
1172 buf[19] = 2;
1173 cpu_to_ube16(&buf[20], 512);
1174 cpu_to_ube16(&buf[22], 706);
1175 buf[24] = 0;
1176 buf[25] = 0;
1177 buf[26] = 0;
1178 buf[27] = 0;
1179 ide_atapi_cmd_reply(s, 28, max_len);
1180 break;
1181 default:
1182 goto error_cmd;
1184 break;
1185 case 1: /* changeable values */
1186 goto error_cmd;
1187 case 2: /* default values */
1188 goto error_cmd;
1189 default:
1190 case 3: /* saved values */
1191 ide_atapi_cmd_error(s, SENSE_ILLEGAL_REQUEST,
1192 ASC_SAVING_PARAMETERS_NOT_SUPPORTED);
1193 break;
1196 break;
1197 case GPCMD_REQUEST_SENSE:
1198 max_len = packet[4];
1199 memset(buf, 0, 18);
1200 buf[0] = 0x70 | (1 << 7);
1201 buf[2] = s->sense_key;
1202 buf[7] = 10;
1203 buf[12] = s->asc;
1204 ide_atapi_cmd_reply(s, 18, max_len);
1205 break;
1206 case GPCMD_PREVENT_ALLOW_MEDIUM_REMOVAL:
1207 if (bdrv_is_inserted(s->bs)) {
1208 bdrv_set_locked(s->bs, packet[4] & 1);
1209 ide_atapi_cmd_ok(s);
1210 } else {
1211 ide_atapi_cmd_error(s, SENSE_NOT_READY,
1212 ASC_MEDIUM_NOT_PRESENT);
1214 break;
1215 case GPCMD_READ_10:
1216 case GPCMD_READ_12:
1218 int nb_sectors, lba;
1220 if (!bdrv_is_inserted(s->bs)) {
1221 ide_atapi_cmd_error(s, SENSE_NOT_READY,
1222 ASC_MEDIUM_NOT_PRESENT);
1223 break;
1225 if (packet[0] == GPCMD_READ_10)
1226 nb_sectors = ube16_to_cpu(packet + 7);
1227 else
1228 nb_sectors = ube32_to_cpu(packet + 6);
1229 lba = ube32_to_cpu(packet + 2);
1230 if (nb_sectors == 0) {
1231 ide_atapi_cmd_ok(s);
1232 break;
1234 if (((int64_t)(lba + nb_sectors) << 2) > s->nb_sectors) {
1235 ide_atapi_cmd_error(s, SENSE_ILLEGAL_REQUEST,
1236 ASC_LOGICAL_BLOCK_OOR);
1237 break;
1239 ide_atapi_cmd_read(s, lba, nb_sectors, 2048);
1241 break;
1242 case GPCMD_READ_CD:
1244 int nb_sectors, lba, transfer_request;
1246 if (!bdrv_is_inserted(s->bs)) {
1247 ide_atapi_cmd_error(s, SENSE_NOT_READY,
1248 ASC_MEDIUM_NOT_PRESENT);
1249 break;
1251 nb_sectors = (packet[6] << 16) | (packet[7] << 8) | packet[8];
1252 lba = ube32_to_cpu(packet + 2);
1253 if (nb_sectors == 0) {
1254 ide_atapi_cmd_ok(s);
1255 break;
1257 if (((int64_t)(lba + nb_sectors) << 2) > s->nb_sectors) {
1258 ide_atapi_cmd_error(s, SENSE_ILLEGAL_REQUEST,
1259 ASC_LOGICAL_BLOCK_OOR);
1260 break;
1262 transfer_request = packet[9];
1263 switch(transfer_request & 0xf8) {
1264 case 0x00:
1265 /* nothing */
1266 ide_atapi_cmd_ok(s);
1267 break;
1268 case 0x10:
1269 /* normal read */
1270 ide_atapi_cmd_read(s, lba, nb_sectors, 2048);
1271 break;
1272 case 0xf8:
1273 /* read all data */
1274 ide_atapi_cmd_read(s, lba, nb_sectors, 2352);
1275 break;
1276 default:
1277 ide_atapi_cmd_error(s, SENSE_ILLEGAL_REQUEST,
1278 ASC_INV_FIELD_IN_CMD_PACKET);
1279 break;
1282 break;
1283 case GPCMD_SEEK:
1285 int lba;
1286 if (!bdrv_is_inserted(s->bs)) {
1287 ide_atapi_cmd_error(s, SENSE_NOT_READY,
1288 ASC_MEDIUM_NOT_PRESENT);
1289 break;
1291 lba = ube32_to_cpu(packet + 2);
1292 if (((int64_t)lba << 2) > s->nb_sectors) {
1293 ide_atapi_cmd_error(s, SENSE_ILLEGAL_REQUEST,
1294 ASC_LOGICAL_BLOCK_OOR);
1295 break;
1297 ide_atapi_cmd_ok(s);
1299 break;
1300 case GPCMD_START_STOP_UNIT:
1302 int start, eject;
1303 start = packet[4] & 1;
1304 eject = (packet[4] >> 1) & 1;
1306 if (eject && !start) {
1307 /* eject the disk */
1308 bdrv_close(s->bs);
1310 ide_atapi_cmd_ok(s);
1312 break;
1313 case GPCMD_MECHANISM_STATUS:
1315 max_len = ube16_to_cpu(packet + 8);
1316 cpu_to_ube16(buf, 0);
1317 /* no current LBA */
1318 buf[2] = 0;
1319 buf[3] = 0;
1320 buf[4] = 0;
1321 buf[5] = 1;
1322 cpu_to_ube16(buf + 6, 0);
1323 ide_atapi_cmd_reply(s, 8, max_len);
1325 break;
1326 case GPCMD_READ_TOC_PMA_ATIP:
1328 int format, msf, start_track, len;
1330 if (!bdrv_is_inserted(s->bs)) {
1331 ide_atapi_cmd_error(s, SENSE_NOT_READY,
1332 ASC_MEDIUM_NOT_PRESENT);
1333 break;
1335 max_len = ube16_to_cpu(packet + 7);
1336 format = packet[9] >> 6;
1337 msf = (packet[1] >> 1) & 1;
1338 start_track = packet[6];
1339 switch(format) {
1340 case 0:
1341 len = cdrom_read_toc(s, buf, msf, start_track);
1342 if (len < 0)
1343 goto error_cmd;
1344 ide_atapi_cmd_reply(s, len, max_len);
1345 break;
1346 case 1:
1347 /* multi session : only a single session defined */
1348 memset(buf, 0, 12);
1349 buf[1] = 0x0a;
1350 buf[2] = 0x01;
1351 buf[3] = 0x01;
1352 ide_atapi_cmd_reply(s, 12, max_len);
1353 break;
1354 case 2:
1355 len = cdrom_read_toc_raw(s, buf, msf, start_track);
1356 if (len < 0)
1357 goto error_cmd;
1358 ide_atapi_cmd_reply(s, len, max_len);
1359 break;
1360 default:
1361 error_cmd:
1362 ide_atapi_cmd_error(s, SENSE_ILLEGAL_REQUEST,
1363 ASC_INV_FIELD_IN_CMD_PACKET);
1364 break;
1367 break;
1368 case GPCMD_READ_CDVD_CAPACITY:
1369 if (!bdrv_is_inserted(s->bs)) {
1370 ide_atapi_cmd_error(s, SENSE_NOT_READY,
1371 ASC_MEDIUM_NOT_PRESENT);
1372 break;
1374 /* NOTE: it is really the number of sectors minus 1 */
1375 cpu_to_ube32(buf, (s->nb_sectors >> 2) - 1);
1376 cpu_to_ube32(buf + 4, 2048);
1377 ide_atapi_cmd_reply(s, 8, 8);
1378 break;
1379 case GPCMD_INQUIRY:
1380 max_len = packet[4];
1381 buf[0] = 0x05; /* CD-ROM */
1382 buf[1] = 0x80; /* removable */
1383 buf[2] = 0x00; /* ISO */
1384 buf[3] = 0x21; /* ATAPI-2 (XXX: put ATAPI-4 ?) */
1385 buf[4] = 31; /* additionnal length */
1386 buf[5] = 0; /* reserved */
1387 buf[6] = 0; /* reserved */
1388 buf[7] = 0; /* reserved */
1389 padstr8(buf + 8, 8, "QEMU");
1390 padstr8(buf + 16, 16, "QEMU CD-ROM");
1391 padstr8(buf + 32, 4, QEMU_VERSION);
1392 ide_atapi_cmd_reply(s, 36, max_len);
1393 break;
1394 default:
1395 ide_atapi_cmd_error(s, SENSE_ILLEGAL_REQUEST,
1396 ASC_ILLEGAL_OPCODE);
1397 break;
1401 /* called when the inserted state of the media has changed */
1402 static void cdrom_change_cb(void *opaque)
1404 IDEState *s = opaque;
1405 int64_t nb_sectors;
1407 /* XXX: send interrupt too */
1408 bdrv_get_geometry(s->bs, &nb_sectors);
1409 s->nb_sectors = nb_sectors;
1412 static void ide_ioport_write(void *opaque, uint32_t addr, uint32_t val)
1414 IDEState *ide_if = opaque;
1415 IDEState *s;
1416 int unit, n;
1418 #ifdef DEBUG_IDE
1419 printf("IDE: write addr=0x%x val=0x%02x\n", addr, val);
1420 #endif
1421 addr &= 7;
1422 switch(addr) {
1423 case 0:
1424 break;
1425 case 1:
1426 /* NOTE: data is written to the two drives */
1427 ide_if[0].feature = val;
1428 ide_if[1].feature = val;
1429 break;
1430 case 2:
1431 if (val == 0)
1432 val = 256;
1433 ide_if[0].nsector = val;
1434 ide_if[1].nsector = val;
1435 break;
1436 case 3:
1437 ide_if[0].sector = val;
1438 ide_if[1].sector = val;
1439 break;
1440 case 4:
1441 ide_if[0].lcyl = val;
1442 ide_if[1].lcyl = val;
1443 break;
1444 case 5:
1445 ide_if[0].hcyl = val;
1446 ide_if[1].hcyl = val;
1447 break;
1448 case 6:
1449 ide_if[0].select = (val & ~0x10) | 0xa0;
1450 ide_if[1].select = (val | 0x10) | 0xa0;
1451 /* select drive */
1452 unit = (val >> 4) & 1;
1453 s = ide_if + unit;
1454 ide_if->cur_drive = s;
1455 break;
1456 default:
1457 case 7:
1458 /* command */
1459 #if defined(DEBUG_IDE)
1460 printf("ide: CMD=%02x\n", val);
1461 #endif
1462 s = ide_if->cur_drive;
1463 /* ignore commands to non existant slave */
1464 if (s != ide_if && !s->bs)
1465 break;
1466 switch(val) {
1467 case WIN_IDENTIFY:
1468 if (s->bs && !s->is_cdrom) {
1469 ide_identify(s);
1470 s->status = READY_STAT | SEEK_STAT;
1471 ide_transfer_start(s, s->io_buffer, 512, ide_transfer_stop);
1472 } else {
1473 if (s->is_cdrom) {
1474 ide_set_signature(s);
1476 ide_abort_command(s);
1478 ide_set_irq(s);
1479 break;
1480 case WIN_SPECIFY:
1481 case WIN_RECAL:
1482 s->error = 0;
1483 s->status = READY_STAT | SEEK_STAT;
1484 ide_set_irq(s);
1485 break;
1486 case WIN_SETMULT:
1487 if (s->nsector > MAX_MULT_SECTORS ||
1488 s->nsector == 0 ||
1489 (s->nsector & (s->nsector - 1)) != 0) {
1490 ide_abort_command(s);
1491 } else {
1492 s->mult_sectors = s->nsector;
1493 s->status = READY_STAT;
1495 ide_set_irq(s);
1496 break;
1497 case WIN_VERIFY:
1498 case WIN_VERIFY_ONCE:
1499 /* do sector number check ? */
1500 s->status = READY_STAT;
1501 ide_set_irq(s);
1502 break;
1503 case WIN_READ:
1504 case WIN_READ_ONCE:
1505 if (!s->bs)
1506 goto abort_cmd;
1507 s->req_nb_sectors = 1;
1508 ide_sector_read(s);
1509 break;
1510 case WIN_WRITE:
1511 case WIN_WRITE_ONCE:
1512 s->error = 0;
1513 s->status = SEEK_STAT | READY_STAT;
1514 s->req_nb_sectors = 1;
1515 ide_transfer_start(s, s->io_buffer, 512, ide_sector_write);
1516 break;
1517 case WIN_MULTREAD:
1518 if (!s->mult_sectors)
1519 goto abort_cmd;
1520 s->req_nb_sectors = s->mult_sectors;
1521 ide_sector_read(s);
1522 break;
1523 case WIN_MULTWRITE:
1524 if (!s->mult_sectors)
1525 goto abort_cmd;
1526 s->error = 0;
1527 s->status = SEEK_STAT | READY_STAT;
1528 s->req_nb_sectors = s->mult_sectors;
1529 n = s->nsector;
1530 if (n > s->req_nb_sectors)
1531 n = s->req_nb_sectors;
1532 ide_transfer_start(s, s->io_buffer, 512 * n, ide_sector_write);
1533 break;
1534 case WIN_READDMA:
1535 case WIN_READDMA_ONCE:
1536 if (!s->bs)
1537 goto abort_cmd;
1538 ide_sector_read_dma(s);
1539 break;
1540 case WIN_WRITEDMA:
1541 case WIN_WRITEDMA_ONCE:
1542 if (!s->bs)
1543 goto abort_cmd;
1544 ide_sector_write_dma(s);
1545 break;
1546 case WIN_READ_NATIVE_MAX:
1547 ide_set_sector(s, s->nb_sectors - 1);
1548 s->status = READY_STAT;
1549 ide_set_irq(s);
1550 break;
1551 case WIN_CHECKPOWERMODE1:
1552 s->nsector = 0xff; /* device active or idle */
1553 s->status = READY_STAT;
1554 ide_set_irq(s);
1555 break;
1556 case WIN_SETFEATURES:
1557 if (!s->bs)
1558 goto abort_cmd;
1559 /* XXX: valid for CDROM ? */
1560 switch(s->feature) {
1561 case 0x02: /* write cache enable */
1562 case 0x03: /* set transfer mode */
1563 case 0x82: /* write cache disable */
1564 case 0xaa: /* read look-ahead enable */
1565 case 0x55: /* read look-ahead disable */
1566 s->status = READY_STAT | SEEK_STAT;
1567 ide_set_irq(s);
1568 break;
1569 default:
1570 goto abort_cmd;
1572 break;
1573 case WIN_STANDBYNOW1:
1574 s->status = READY_STAT;
1575 ide_set_irq(s);
1576 break;
1577 /* ATAPI commands */
1578 case WIN_PIDENTIFY:
1579 if (s->is_cdrom) {
1580 ide_atapi_identify(s);
1581 s->status = READY_STAT;
1582 ide_transfer_start(s, s->io_buffer, 512, ide_transfer_stop);
1583 } else {
1584 ide_abort_command(s);
1586 ide_set_irq(s);
1587 break;
1588 case WIN_SRST:
1589 if (!s->is_cdrom)
1590 goto abort_cmd;
1591 ide_set_signature(s);
1592 s->status = 0x00; /* NOTE: READY is _not_ set */
1593 s->error = 0x01;
1594 break;
1595 case WIN_PACKETCMD:
1596 if (!s->is_cdrom)
1597 goto abort_cmd;
1598 /* overlapping commands not supported */
1599 if (s->feature & 0x02)
1600 goto abort_cmd;
1601 s->atapi_dma = s->feature & 1;
1602 s->nsector = 1;
1603 ide_transfer_start(s, s->io_buffer, ATAPI_PACKET_SIZE,
1604 ide_atapi_cmd);
1605 break;
1606 default:
1607 abort_cmd:
1608 ide_abort_command(s);
1609 ide_set_irq(s);
1610 break;
1615 static uint32_t ide_ioport_read(void *opaque, uint32_t addr1)
1617 IDEState *ide_if = opaque;
1618 IDEState *s = ide_if->cur_drive;
1619 uint32_t addr;
1620 int ret;
1622 addr = addr1 & 7;
1623 switch(addr) {
1624 case 0:
1625 ret = 0xff;
1626 break;
1627 case 1:
1628 if (!ide_if[0].bs && !ide_if[1].bs)
1629 ret = 0;
1630 else
1631 ret = s->error;
1632 break;
1633 case 2:
1634 if (!ide_if[0].bs && !ide_if[1].bs)
1635 ret = 0;
1636 else
1637 ret = s->nsector & 0xff;
1638 break;
1639 case 3:
1640 if (!ide_if[0].bs && !ide_if[1].bs)
1641 ret = 0;
1642 else
1643 ret = s->sector;
1644 break;
1645 case 4:
1646 if (!ide_if[0].bs && !ide_if[1].bs)
1647 ret = 0;
1648 else
1649 ret = s->lcyl;
1650 break;
1651 case 5:
1652 if (!ide_if[0].bs && !ide_if[1].bs)
1653 ret = 0;
1654 else
1655 ret = s->hcyl;
1656 break;
1657 case 6:
1658 if (!ide_if[0].bs && !ide_if[1].bs)
1659 ret = 0;
1660 else
1661 ret = s->select;
1662 break;
1663 default:
1664 case 7:
1665 if ((!ide_if[0].bs && !ide_if[1].bs) ||
1666 (s != ide_if && !s->bs))
1667 ret = 0;
1668 else
1669 ret = s->status;
1670 #ifdef TARGET_PPC
1671 if (s->openpic)
1672 openpic_set_irq(s->openpic, s->irq, 0);
1673 else
1674 #endif
1675 if (s->irq == 16)
1676 pci_set_irq(s->pci_dev, 0, 0);
1677 else
1678 pic_set_irq(s->irq, 0);
1679 break;
1681 #ifdef DEBUG_IDE
1682 printf("ide: read addr=0x%x val=%02x\n", addr1, ret);
1683 #endif
1684 return ret;
1687 static uint32_t ide_status_read(void *opaque, uint32_t addr)
1689 IDEState *ide_if = opaque;
1690 IDEState *s = ide_if->cur_drive;
1691 int ret;
1693 if ((!ide_if[0].bs && !ide_if[1].bs) ||
1694 (s != ide_if && !s->bs))
1695 ret = 0;
1696 else
1697 ret = s->status;
1698 #ifdef DEBUG_IDE
1699 printf("ide: read status addr=0x%x val=%02x\n", addr, ret);
1700 #endif
1701 return ret;
1704 static void ide_cmd_write(void *opaque, uint32_t addr, uint32_t val)
1706 IDEState *ide_if = opaque;
1707 IDEState *s;
1708 int i;
1710 #ifdef DEBUG_IDE
1711 printf("ide: write control addr=0x%x val=%02x\n", addr, val);
1712 #endif
1713 /* common for both drives */
1714 if (!(ide_if[0].cmd & IDE_CMD_RESET) &&
1715 (val & IDE_CMD_RESET)) {
1716 /* reset low to high */
1717 for(i = 0;i < 2; i++) {
1718 s = &ide_if[i];
1719 s->status = BUSY_STAT | SEEK_STAT;
1720 s->error = 0x01;
1722 } else if ((ide_if[0].cmd & IDE_CMD_RESET) &&
1723 !(val & IDE_CMD_RESET)) {
1724 /* high to low */
1725 for(i = 0;i < 2; i++) {
1726 s = &ide_if[i];
1727 if (s->is_cdrom)
1728 s->status = 0x00; /* NOTE: READY is _not_ set */
1729 else
1730 s->status = READY_STAT | SEEK_STAT;
1731 ide_set_signature(s);
1735 ide_if[0].cmd = val;
1736 ide_if[1].cmd = val;
1739 static void ide_data_writew(void *opaque, uint32_t addr, uint32_t val)
1741 IDEState *s = ((IDEState *)opaque)->cur_drive;
1742 uint8_t *p;
1744 p = s->data_ptr;
1745 *(uint16_t *)p = le16_to_cpu(val);
1746 p += 2;
1747 s->data_ptr = p;
1748 if (p >= s->data_end)
1749 s->end_transfer_func(s);
1752 static uint32_t ide_data_readw(void *opaque, uint32_t addr)
1754 IDEState *s = ((IDEState *)opaque)->cur_drive;
1755 uint8_t *p;
1756 int ret;
1757 p = s->data_ptr;
1758 ret = cpu_to_le16(*(uint16_t *)p);
1759 p += 2;
1760 s->data_ptr = p;
1761 if (p >= s->data_end)
1762 s->end_transfer_func(s);
1763 return ret;
1766 static void ide_data_writel(void *opaque, uint32_t addr, uint32_t val)
1768 IDEState *s = ((IDEState *)opaque)->cur_drive;
1769 uint8_t *p;
1771 p = s->data_ptr;
1772 *(uint32_t *)p = le32_to_cpu(val);
1773 p += 4;
1774 s->data_ptr = p;
1775 if (p >= s->data_end)
1776 s->end_transfer_func(s);
1779 static uint32_t ide_data_readl(void *opaque, uint32_t addr)
1781 IDEState *s = ((IDEState *)opaque)->cur_drive;
1782 uint8_t *p;
1783 int ret;
1785 p = s->data_ptr;
1786 ret = cpu_to_le32(*(uint32_t *)p);
1787 p += 4;
1788 s->data_ptr = p;
1789 if (p >= s->data_end)
1790 s->end_transfer_func(s);
1791 return ret;
1794 static void ide_dummy_transfer_stop(IDEState *s)
1796 s->data_ptr = s->io_buffer;
1797 s->data_end = s->io_buffer;
1798 s->io_buffer[0] = 0xff;
1799 s->io_buffer[1] = 0xff;
1800 s->io_buffer[2] = 0xff;
1801 s->io_buffer[3] = 0xff;
1804 static void ide_reset(IDEState *s)
1806 s->mult_sectors = MAX_MULT_SECTORS;
1807 s->cur_drive = s;
1808 s->select = 0xa0;
1809 s->status = READY_STAT;
1810 ide_set_signature(s);
1811 /* init the transfer handler so that 0xffff is returned on data
1812 accesses */
1813 s->end_transfer_func = ide_dummy_transfer_stop;
1814 ide_dummy_transfer_stop(s);
1817 struct partition {
1818 uint8_t boot_ind; /* 0x80 - active */
1819 uint8_t head; /* starting head */
1820 uint8_t sector; /* starting sector */
1821 uint8_t cyl; /* starting cylinder */
1822 uint8_t sys_ind; /* What partition type */
1823 uint8_t end_head; /* end head */
1824 uint8_t end_sector; /* end sector */
1825 uint8_t end_cyl; /* end cylinder */
1826 uint32_t start_sect; /* starting sector counting from 0 */
1827 uint32_t nr_sects; /* nr of sectors in partition */
1828 } __attribute__((packed));
1830 /* try to guess the IDE geometry from the MSDOS partition table */
1831 static void ide_guess_geometry(IDEState *s)
1833 uint8_t buf[512];
1834 int ret, i;
1835 struct partition *p;
1836 uint32_t nr_sects;
1838 if (s->cylinders != 0)
1839 return;
1840 ret = bdrv_read(s->bs, 0, buf, 1);
1841 if (ret < 0)
1842 return;
1843 /* test msdos magic */
1844 if (buf[510] != 0x55 || buf[511] != 0xaa)
1845 return;
1846 for(i = 0; i < 4; i++) {
1847 p = ((struct partition *)(buf + 0x1be)) + i;
1848 nr_sects = le32_to_cpu(p->nr_sects);
1849 if (nr_sects && p->end_head) {
1850 /* We make the assumption that the partition terminates on
1851 a cylinder boundary */
1852 s->heads = p->end_head + 1;
1853 s->sectors = p->end_sector & 63;
1854 if (s->sectors == 0)
1855 continue;
1856 s->cylinders = s->nb_sectors / (s->heads * s->sectors);
1857 if (s->cylinders < 1 || s->cylinders > 16383)
1858 continue;
1859 #if 0
1860 printf("guessed partition: CHS=%d %d %d\n",
1861 s->cylinders, s->heads, s->sectors);
1862 #endif
1867 static void ide_init2(IDEState *ide_state, int irq,
1868 BlockDriverState *hd0, BlockDriverState *hd1)
1870 IDEState *s;
1871 static int drive_serial = 1;
1872 int i, cylinders, heads, secs;
1873 int64_t nb_sectors;
1875 for(i = 0; i < 2; i++) {
1876 s = ide_state + i;
1877 if (i == 0)
1878 s->bs = hd0;
1879 else
1880 s->bs = hd1;
1881 if (s->bs) {
1882 bdrv_get_geometry(s->bs, &nb_sectors);
1883 s->nb_sectors = nb_sectors;
1884 /* if a geometry hint is available, use it */
1885 bdrv_get_geometry_hint(s->bs, &cylinders, &heads, &secs);
1886 if (cylinders != 0) {
1887 s->cylinders = cylinders;
1888 s->heads = heads;
1889 s->sectors = secs;
1890 } else {
1891 ide_guess_geometry(s);
1893 /* if heads > 16, it means that a BIOS LBA
1894 translation was active, so the default
1895 hardware geometry is OK */
1896 if ((s->heads > 16) || (s->cylinders == 0)) {
1897 /* if no geometry, use a standard physical disk geometry */
1898 cylinders = nb_sectors / (16 * 63);
1899 if (cylinders > 16383)
1900 cylinders = 16383;
1901 else if (cylinders < 2)
1902 cylinders = 2;
1903 s->cylinders = cylinders;
1904 s->heads = 16;
1905 s->sectors = 63;
1907 bdrv_set_geometry_hint(s->bs, s->cylinders, s->heads, s->sectors);
1909 if (bdrv_get_type_hint(s->bs) == BDRV_TYPE_CDROM) {
1910 s->is_cdrom = 1;
1911 bdrv_set_change_cb(s->bs, cdrom_change_cb, s);
1914 s->drive_serial = drive_serial++;
1915 s->irq = irq;
1916 ide_reset(s);
1920 static void ide_init_ioport(IDEState *ide_state, int iobase, int iobase2)
1922 register_ioport_write(iobase, 8, 1, ide_ioport_write, ide_state);
1923 register_ioport_read(iobase, 8, 1, ide_ioport_read, ide_state);
1924 if (iobase2) {
1925 register_ioport_read(iobase2, 1, 1, ide_status_read, ide_state);
1926 register_ioport_write(iobase2, 1, 1, ide_cmd_write, ide_state);
1929 /* data ports */
1930 register_ioport_write(iobase, 2, 2, ide_data_writew, ide_state);
1931 register_ioport_read(iobase, 2, 2, ide_data_readw, ide_state);
1932 register_ioport_write(iobase, 4, 4, ide_data_writel, ide_state);
1933 register_ioport_read(iobase, 4, 4, ide_data_readl, ide_state);
1936 /***********************************************************/
1937 /* ISA IDE definitions */
1939 void isa_ide_init(int iobase, int iobase2, int irq,
1940 BlockDriverState *hd0, BlockDriverState *hd1)
1942 IDEState *ide_state;
1944 ide_state = qemu_mallocz(sizeof(IDEState) * 2);
1945 if (!ide_state)
1946 return;
1948 ide_init2(ide_state, irq, hd0, hd1);
1949 ide_init_ioport(ide_state, iobase, iobase2);
1952 /***********************************************************/
1953 /* PCI IDE definitions */
1955 static void ide_map(PCIDevice *pci_dev, int region_num,
1956 uint32_t addr, uint32_t size, int type)
1958 PCIIDEState *d = (PCIIDEState *)pci_dev;
1959 IDEState *ide_state;
1961 if (region_num <= 3) {
1962 ide_state = &d->ide_if[(region_num >> 1) * 2];
1963 if (region_num & 1) {
1964 register_ioport_read(addr + 2, 1, 1, ide_status_read, ide_state);
1965 register_ioport_write(addr + 2, 1, 1, ide_cmd_write, ide_state);
1966 } else {
1967 register_ioport_write(addr, 8, 1, ide_ioport_write, ide_state);
1968 register_ioport_read(addr, 8, 1, ide_ioport_read, ide_state);
1970 /* data ports */
1971 register_ioport_write(addr, 2, 2, ide_data_writew, ide_state);
1972 register_ioport_read(addr, 2, 2, ide_data_readw, ide_state);
1973 register_ioport_write(addr, 4, 4, ide_data_writel, ide_state);
1974 register_ioport_read(addr, 4, 4, ide_data_readl, ide_state);
1979 /* XXX: full callback usage to prepare non blocking I/Os support -
1980 error handling */
1981 static void ide_dma_loop(BMDMAState *bm)
1983 struct {
1984 uint32_t addr;
1985 uint32_t size;
1986 } prd;
1987 target_phys_addr_t cur_addr;
1988 int len, i, len1;
1990 cur_addr = bm->addr;
1991 /* at most one page to avoid hanging if erroneous parameters */
1992 for(i = 0; i < 512; i++) {
1993 cpu_physical_memory_read(cur_addr, (uint8_t *)&prd, 8);
1994 prd.addr = le32_to_cpu(prd.addr);
1995 prd.size = le32_to_cpu(prd.size);
1996 #ifdef DEBUG_IDE
1997 printf("ide: dma: prd: %08x: addr=0x%08x size=0x%08x\n",
1998 (int)cur_addr, prd.addr, prd.size);
1999 #endif
2000 len = prd.size & 0xfffe;
2001 if (len == 0)
2002 len = 0x10000;
2003 while (len > 0) {
2004 len1 = bm->dma_cb(bm->ide_if, prd.addr, len);
2005 if (len1 == 0)
2006 goto the_end;
2007 prd.addr += len1;
2008 len -= len1;
2010 /* end of transfer */
2011 if (prd.size & 0x80000000)
2012 break;
2013 cur_addr += 8;
2015 /* end of transfer */
2016 the_end:
2017 bm->status &= ~BM_STATUS_DMAING;
2018 bm->status |= BM_STATUS_INT;
2019 bm->dma_cb = NULL;
2020 bm->ide_if = NULL;
2023 static void ide_dma_start(IDEState *s, IDEDMAFunc *dma_cb)
2025 BMDMAState *bm = s->bmdma;
2026 if(!bm)
2027 return;
2028 bm->ide_if = s;
2029 bm->dma_cb = dma_cb;
2030 if (bm->status & BM_STATUS_DMAING) {
2031 ide_dma_loop(bm);
2035 static uint32_t bmdma_cmd_readb(void *opaque, uint32_t addr)
2037 BMDMAState *bm = opaque;
2038 uint32_t val;
2039 val = bm->cmd;
2040 #ifdef DEBUG_IDE
2041 printf("%s: 0x%08x\n", __func__, val);
2042 #endif
2043 return val;
2046 static void bmdma_cmd_writeb(void *opaque, uint32_t addr, uint32_t val)
2048 BMDMAState *bm = opaque;
2049 #ifdef DEBUG_IDE
2050 printf("%s: 0x%08x\n", __func__, val);
2051 #endif
2052 if (!(val & BM_CMD_START)) {
2053 /* XXX: do it better */
2054 bm->status &= ~BM_STATUS_DMAING;
2055 bm->cmd = val & 0x09;
2056 } else {
2057 bm->status |= BM_STATUS_DMAING;
2058 bm->cmd = val & 0x09;
2059 /* start dma transfer if possible */
2060 if (bm->dma_cb)
2061 ide_dma_loop(bm);
2065 static uint32_t bmdma_status_readb(void *opaque, uint32_t addr)
2067 BMDMAState *bm = opaque;
2068 uint32_t val;
2069 val = bm->status;
2070 #ifdef DEBUG_IDE
2071 printf("%s: 0x%08x\n", __func__, val);
2072 #endif
2073 return val;
2076 static void bmdma_status_writeb(void *opaque, uint32_t addr, uint32_t val)
2078 BMDMAState *bm = opaque;
2079 #ifdef DEBUG_IDE
2080 printf("%s: 0x%08x\n", __func__, val);
2081 #endif
2082 bm->status = (val & 0x60) | (bm->status & 1) | (bm->status & ~val & 0x06);
2085 static uint32_t bmdma_addr_readl(void *opaque, uint32_t addr)
2087 BMDMAState *bm = opaque;
2088 uint32_t val;
2089 val = bm->addr;
2090 #ifdef DEBUG_IDE
2091 printf("%s: 0x%08x\n", __func__, val);
2092 #endif
2093 return val;
2096 static void bmdma_addr_writel(void *opaque, uint32_t addr, uint32_t val)
2098 BMDMAState *bm = opaque;
2099 #ifdef DEBUG_IDE
2100 printf("%s: 0x%08x\n", __func__, val);
2101 #endif
2102 bm->addr = val & ~3;
2105 static void bmdma_map(PCIDevice *pci_dev, int region_num,
2106 uint32_t addr, uint32_t size, int type)
2108 PCIIDEState *d = (PCIIDEState *)pci_dev;
2109 int i;
2111 for(i = 0;i < 2; i++) {
2112 BMDMAState *bm = &d->bmdma[i];
2113 d->ide_if[2 * i].bmdma = bm;
2114 d->ide_if[2 * i + 1].bmdma = bm;
2116 register_ioport_write(addr, 1, 1, bmdma_cmd_writeb, bm);
2117 register_ioport_read(addr, 1, 1, bmdma_cmd_readb, bm);
2119 register_ioport_write(addr + 2, 1, 1, bmdma_status_writeb, bm);
2120 register_ioport_read(addr + 2, 1, 1, bmdma_status_readb, bm);
2122 register_ioport_write(addr + 4, 4, 4, bmdma_addr_writel, bm);
2123 register_ioport_read(addr + 4, 4, 4, bmdma_addr_readl, bm);
2124 addr += 8;
2128 /* hd_table must contain 4 block drivers */
2129 void pci_ide_init(PCIBus *bus, BlockDriverState **hd_table)
2131 PCIIDEState *d;
2132 uint8_t *pci_conf;
2133 int i;
2135 d = (PCIIDEState *)pci_register_device(bus, "IDE", sizeof(PCIIDEState),
2136 -1,
2137 NULL, NULL);
2138 pci_conf = d->dev.config;
2139 pci_conf[0x00] = 0x86; // Intel
2140 pci_conf[0x01] = 0x80;
2141 pci_conf[0x02] = 0x00; // fake
2142 pci_conf[0x03] = 0x01; // fake
2143 pci_conf[0x0a] = 0x01; // class_sub = PCI_IDE
2144 pci_conf[0x0b] = 0x01; // class_base = PCI_mass_storage
2145 pci_conf[0x0e] = 0x80; // header_type = PCI_multifunction, generic
2147 pci_conf[0x2c] = 0x86; // subsys vendor
2148 pci_conf[0x2d] = 0x80; // subsys vendor
2149 pci_conf[0x2e] = 0x00; // fake
2150 pci_conf[0x2f] = 0x01; // fake
2152 pci_register_io_region((PCIDevice *)d, 0, 0x8,
2153 PCI_ADDRESS_SPACE_IO, ide_map);
2154 pci_register_io_region((PCIDevice *)d, 1, 0x4,
2155 PCI_ADDRESS_SPACE_IO, ide_map);
2156 pci_register_io_region((PCIDevice *)d, 2, 0x8,
2157 PCI_ADDRESS_SPACE_IO, ide_map);
2158 pci_register_io_region((PCIDevice *)d, 3, 0x4,
2159 PCI_ADDRESS_SPACE_IO, ide_map);
2160 pci_register_io_region((PCIDevice *)d, 4, 0x10,
2161 PCI_ADDRESS_SPACE_IO, bmdma_map);
2163 pci_conf[0x3d] = 0x01; // interrupt on pin 1
2165 for(i = 0; i < 4; i++)
2166 d->ide_if[i].pci_dev = (PCIDevice *)d;
2167 ide_init2(&d->ide_if[0], 16, hd_table[0], hd_table[1]);
2168 ide_init2(&d->ide_if[2], 16, hd_table[2], hd_table[3]);
2171 /* hd_table must contain 4 block drivers */
2172 /* NOTE: for the PIIX3, the IRQs and IOports are hardcoded */
2173 void pci_piix3_ide_init(PCIBus *bus, BlockDriverState **hd_table)
2175 PCIIDEState *d;
2176 uint8_t *pci_conf;
2178 /* register a function 1 of PIIX3 */
2179 d = (PCIIDEState *)pci_register_device(bus, "PIIX3 IDE",
2180 sizeof(PCIIDEState),
2181 ((PCIDevice *)piix3_state)->devfn + 1,
2182 NULL, NULL);
2183 pci_conf = d->dev.config;
2184 pci_conf[0x00] = 0x86; // Intel
2185 pci_conf[0x01] = 0x80;
2186 pci_conf[0x02] = 0x10;
2187 pci_conf[0x03] = 0x70;
2188 pci_conf[0x0a] = 0x01; // class_sub = PCI_IDE
2189 pci_conf[0x0b] = 0x01; // class_base = PCI_mass_storage
2190 pci_conf[0x0e] = 0x00; // header_type
2192 pci_register_io_region((PCIDevice *)d, 4, 0x10,
2193 PCI_ADDRESS_SPACE_IO, bmdma_map);
2195 ide_init2(&d->ide_if[0], 14, hd_table[0], hd_table[1]);
2196 ide_init2(&d->ide_if[2], 15, hd_table[2], hd_table[3]);
2197 ide_init_ioport(&d->ide_if[0], 0x1f0, 0x3f6);
2198 ide_init_ioport(&d->ide_if[2], 0x170, 0x376);
2201 /***********************************************************/
2202 /* MacIO based PowerPC IDE */
2204 /* PowerMac IDE memory IO */
2205 static void pmac_ide_writeb (void *opaque,
2206 target_phys_addr_t addr, uint32_t val)
2208 addr = (addr & 0xFFF) >> 4;
2209 switch (addr) {
2210 case 1 ... 7:
2211 ide_ioport_write(opaque, addr, val);
2212 break;
2213 case 8:
2214 case 22:
2215 ide_cmd_write(opaque, 0, val);
2216 break;
2217 default:
2218 break;
2222 static uint32_t pmac_ide_readb (void *opaque,target_phys_addr_t addr)
2224 uint8_t retval;
2226 addr = (addr & 0xFFF) >> 4;
2227 switch (addr) {
2228 case 1 ... 7:
2229 retval = ide_ioport_read(opaque, addr);
2230 break;
2231 case 8:
2232 case 22:
2233 retval = ide_status_read(opaque, 0);
2234 break;
2235 default:
2236 retval = 0xFF;
2237 break;
2239 return retval;
2242 static void pmac_ide_writew (void *opaque,
2243 target_phys_addr_t addr, uint32_t val)
2245 addr = (addr & 0xFFF) >> 4;
2246 #ifdef TARGET_WORDS_BIGENDIAN
2247 val = bswap16(val);
2248 #endif
2249 if (addr == 0) {
2250 ide_data_writew(opaque, 0, val);
2254 static uint32_t pmac_ide_readw (void *opaque,target_phys_addr_t addr)
2256 uint16_t retval;
2258 addr = (addr & 0xFFF) >> 4;
2259 if (addr == 0) {
2260 retval = ide_data_readw(opaque, 0);
2261 } else {
2262 retval = 0xFFFF;
2264 #ifdef TARGET_WORDS_BIGENDIAN
2265 retval = bswap16(retval);
2266 #endif
2267 return retval;
2270 static void pmac_ide_writel (void *opaque,
2271 target_phys_addr_t addr, uint32_t val)
2273 addr = (addr & 0xFFF) >> 4;
2274 #ifdef TARGET_WORDS_BIGENDIAN
2275 val = bswap32(val);
2276 #endif
2277 if (addr == 0) {
2278 ide_data_writel(opaque, 0, val);
2282 static uint32_t pmac_ide_readl (void *opaque,target_phys_addr_t addr)
2284 uint32_t retval;
2286 addr = (addr & 0xFFF) >> 4;
2287 if (addr == 0) {
2288 retval = ide_data_readl(opaque, 0);
2289 } else {
2290 retval = 0xFFFFFFFF;
2292 #ifdef TARGET_WORDS_BIGENDIAN
2293 retval = bswap32(retval);
2294 #endif
2295 return retval;
2298 static CPUWriteMemoryFunc *pmac_ide_write[] = {
2299 pmac_ide_writeb,
2300 pmac_ide_writew,
2301 pmac_ide_writel,
2302 };
2304 static CPUReadMemoryFunc *pmac_ide_read[] = {
2305 pmac_ide_readb,
2306 pmac_ide_readw,
2307 pmac_ide_readl,
2308 };
2310 /* hd_table must contain 4 block drivers */
2311 /* PowerMac uses memory mapped registers, not I/O. Return the memory
2312 I/O index to access the ide. */
2313 int pmac_ide_init (BlockDriverState **hd_table,
2314 openpic_t *openpic, int irq)
2316 IDEState *ide_if;
2317 int pmac_ide_memory;
2319 ide_if = qemu_mallocz(sizeof(IDEState) * 2);
2320 ide_init2(&ide_if[0], irq, hd_table[0], hd_table[1]);
2321 ide_if[0].openpic = openpic;
2322 ide_if[1].openpic = openpic;
2324 pmac_ide_memory = cpu_register_io_memory(0, pmac_ide_read,
2325 pmac_ide_write, &ide_if[0]);
2326 return pmac_ide_memory;