ia64/xen-unstable

view xen/arch/x86/cpu/amd.c @ 6435:b4b3f6be5226

merge?
author cl349@firebug.cl.cam.ac.uk
date Thu Aug 25 17:27:49 2005 +0000 (2005-08-25)
parents 0610add7c3fe e56b8040bc90
children 8799d14bef77 9312a3e8a6f8 112d44270733
line source
1 #include <xen/config.h>
2 #include <xen/init.h>
3 #include <xen/bitops.h>
4 #include <xen/mm.h>
5 #include <xen/smp.h>
6 #include <asm/io.h>
7 #include <asm/msr.h>
8 #include <asm/processor.h>
10 #include "cpu.h"
12 /*
13 * amd_flush_filter={on,off}. Forcibly Enable or disable the TLB flush
14 * filter on AMD 64-bit processors.
15 */
16 static int flush_filter_force;
17 static void flush_filter(char *s)
18 {
19 if (!strcmp(s, "off"))
20 flush_filter_force = -1;
21 if (!strcmp(s, "on"))
22 flush_filter_force = 1;
23 }
24 custom_param("amd_flush_filter", flush_filter);
26 #define num_physpages 0
28 /*
29 * B step AMD K6 before B 9730xxxx have hardware bugs that can cause
30 * misexecution of code under Linux. Owners of such processors should
31 * contact AMD for precise details and a CPU swap.
32 *
33 * See http://www.multimania.com/poulot/k6bug.html
34 * http://www.amd.com/K6/k6docs/revgd.html
35 *
36 * The following test is erm.. interesting. AMD neglected to up
37 * the chip setting when fixing the bug but they also tweaked some
38 * performance at the same time..
39 */
41 extern void vide(void);
42 __asm__(".text\n.align 4\nvide: ret");
44 static void __init init_amd(struct cpuinfo_x86 *c)
45 {
46 u32 l, h;
47 int mbytes = num_physpages >> (20-PAGE_SHIFT);
48 int r;
50 /*
51 * FIXME: We should handle the K5 here. Set up the write
52 * range and also turn on MSR 83 bits 4 and 31 (write alloc,
53 * no bus pipeline)
54 */
56 /* Bit 31 in normal CPUID used for nonstandard 3DNow ID;
57 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway */
58 clear_bit(0*32+31, c->x86_capability);
60 r = get_model_name(c);
62 switch(c->x86)
63 {
64 case 4:
65 /*
66 * General Systems BIOSen alias the cpu frequency registers
67 * of the Elan at 0x000df000. Unfortuantly, one of the Linux
68 * drivers subsequently pokes it, and changes the CPU speed.
69 * Workaround : Remove the unneeded alias.
70 */
71 #define CBAR (0xfffc) /* Configuration Base Address (32-bit) */
72 #define CBAR_ENB (0x80000000)
73 #define CBAR_KEY (0X000000CB)
74 if (c->x86_model==9 || c->x86_model == 10) {
75 if (inl (CBAR) & CBAR_ENB)
76 outl (0 | CBAR_KEY, CBAR);
77 }
78 break;
79 case 5:
80 if( c->x86_model < 6 )
81 {
82 /* Based on AMD doc 20734R - June 2000 */
83 if ( c->x86_model == 0 ) {
84 clear_bit(X86_FEATURE_APIC, c->x86_capability);
85 set_bit(X86_FEATURE_PGE, c->x86_capability);
86 }
87 break;
88 }
90 if ( c->x86_model == 6 && c->x86_mask == 1 ) {
91 const int K6_BUG_LOOP = 1000000;
92 int n;
93 void (*f_vide)(void);
94 unsigned long d, d2;
96 printk(KERN_INFO "AMD K6 stepping B detected - ");
98 /*
99 * It looks like AMD fixed the 2.6.2 bug and improved indirect
100 * calls at the same time.
101 */
103 n = K6_BUG_LOOP;
104 f_vide = vide;
105 rdtscl(d);
106 while (n--)
107 f_vide();
108 rdtscl(d2);
109 d = d2-d;
111 /* Knock these two lines out if it debugs out ok */
112 printk(KERN_INFO "AMD K6 stepping B detected - ");
113 /* -- cut here -- */
114 if (d > 20*K6_BUG_LOOP)
115 printk("system stability may be impaired when more than 32 MB are used.\n");
116 else
117 printk("probably OK (after B9730xxxx).\n");
118 printk(KERN_INFO "Please see http://membres.lycos.fr/poulot/k6bug.html\n");
119 }
121 /* K6 with old style WHCR */
122 if (c->x86_model < 8 ||
123 (c->x86_model== 8 && c->x86_mask < 8)) {
124 /* We can only write allocate on the low 508Mb */
125 if(mbytes>508)
126 mbytes=508;
128 rdmsr(MSR_K6_WHCR, l, h);
129 if ((l&0x0000FFFF)==0) {
130 unsigned long flags;
131 l=(1<<0)|((mbytes/4)<<1);
132 local_irq_save(flags);
133 wbinvd();
134 wrmsr(MSR_K6_WHCR, l, h);
135 local_irq_restore(flags);
136 printk(KERN_INFO "Enabling old style K6 write allocation for %d Mb\n",
137 mbytes);
138 }
139 break;
140 }
142 if ((c->x86_model == 8 && c->x86_mask >7) ||
143 c->x86_model == 9 || c->x86_model == 13) {
144 /* The more serious chips .. */
146 if(mbytes>4092)
147 mbytes=4092;
149 rdmsr(MSR_K6_WHCR, l, h);
150 if ((l&0xFFFF0000)==0) {
151 unsigned long flags;
152 l=((mbytes>>2)<<22)|(1<<16);
153 local_irq_save(flags);
154 wbinvd();
155 wrmsr(MSR_K6_WHCR, l, h);
156 local_irq_restore(flags);
157 printk(KERN_INFO "Enabling new style K6 write allocation for %d Mb\n",
158 mbytes);
159 }
161 /* Set MTRR capability flag if appropriate */
162 if (c->x86_model == 13 || c->x86_model == 9 ||
163 (c->x86_model == 8 && c->x86_mask >= 8))
164 set_bit(X86_FEATURE_K6_MTRR, c->x86_capability);
165 break;
166 }
167 break;
169 case 6: /* An Athlon/Duron */
171 /* Bit 15 of Athlon specific MSR 15, needs to be 0
172 * to enable SSE on Palomino/Morgan/Barton CPU's.
173 * If the BIOS didn't enable it already, enable it here.
174 */
175 if (c->x86_model >= 6 && c->x86_model <= 10) {
176 if (!cpu_has(c, X86_FEATURE_XMM)) {
177 printk(KERN_INFO "Enabling disabled K7/SSE Support.\n");
178 rdmsr(MSR_K7_HWCR, l, h);
179 l &= ~0x00008000;
180 wrmsr(MSR_K7_HWCR, l, h);
181 set_bit(X86_FEATURE_XMM, c->x86_capability);
182 }
183 }
185 /* It's been determined by AMD that Athlons since model 8 stepping 1
186 * are more robust with CLK_CTL set to 200xxxxx instead of 600xxxxx
187 * As per AMD technical note 27212 0.2
188 */
189 if ((c->x86_model == 8 && c->x86_mask>=1) || (c->x86_model > 8)) {
190 rdmsr(MSR_K7_CLK_CTL, l, h);
191 if ((l & 0xfff00000) != 0x20000000) {
192 printk ("CPU: CLK_CTL MSR was %x. Reprogramming to %x\n", l,
193 ((l & 0x000fffff)|0x20000000));
194 wrmsr(MSR_K7_CLK_CTL, (l & 0x000fffff)|0x20000000, h);
195 }
196 }
197 break;
198 }
200 switch (c->x86) {
201 case 15:
202 set_bit(X86_FEATURE_K8, c->x86_capability);
203 break;
204 case 6:
205 set_bit(X86_FEATURE_K7, c->x86_capability);
206 break;
207 }
209 if (c->x86 == 15) {
210 rdmsr(MSR_K7_HWCR, l, h);
211 printk(KERN_INFO "CPU%d: AMD Flush Filter %sabled",
212 smp_processor_id(), (l & (1<<6)) ? "dis" : "en");
213 if ((flush_filter_force > 0) && (l & (1<<6))) {
214 l &= ~(1<<6);
215 printk(" -> Forcibly enabled");
216 } else if ((flush_filter_force < 0) && !(l & (1<<6))) {
217 l |= 1<<6;
218 printk(" -> Forcibly disabled");
219 }
220 wrmsr(MSR_K7_HWCR, l, h);
221 printk("\n");
222 }
224 display_cacheinfo(c);
226 if (cpuid_eax(0x80000000) >= 0x80000008) {
227 c->x86_num_cores = (cpuid_ecx(0x80000008) & 0xff) + 1;
228 if (c->x86_num_cores & (c->x86_num_cores - 1))
229 c->x86_num_cores = 1;
230 }
232 #ifdef CONFIG_X86_HT
233 /*
234 * On a AMD dual core setup the lower bits of the APIC id
235 * distingush the cores. Assumes number of cores is a power
236 * of two.
237 */
238 if (c->x86_num_cores > 1) {
239 int cpu = smp_processor_id();
240 unsigned bits = 0;
241 while ((1 << bits) < c->x86_num_cores)
242 bits++;
243 cpu_core_id[cpu] = phys_proc_id[cpu] & ((1<<bits)-1);
244 phys_proc_id[cpu] >>= bits;
245 printk(KERN_INFO "CPU %d(%d) -> Core %d\n",
246 cpu, c->x86_num_cores, cpu_core_id[cpu]);
247 }
248 #endif
249 }
251 static unsigned int amd_size_cache(struct cpuinfo_x86 * c, unsigned int size)
252 {
253 /* AMD errata T13 (order #21922) */
254 if ((c->x86 == 6)) {
255 if (c->x86_model == 3 && c->x86_mask == 0) /* Duron Rev A0 */
256 size = 64;
257 if (c->x86_model == 4 &&
258 (c->x86_mask==0 || c->x86_mask==1)) /* Tbird rev A1/A2 */
259 size = 256;
260 }
261 return size;
262 }
264 static struct cpu_dev amd_cpu_dev __initdata = {
265 .c_vendor = "AMD",
266 .c_ident = { "AuthenticAMD" },
267 .c_models = {
268 { .vendor = X86_VENDOR_AMD, .family = 4, .model_names =
269 {
270 [3] = "486 DX/2",
271 [7] = "486 DX/2-WB",
272 [8] = "486 DX/4",
273 [9] = "486 DX/4-WB",
274 [14] = "Am5x86-WT",
275 [15] = "Am5x86-WB"
276 }
277 },
278 },
279 .c_init = init_amd,
280 .c_identify = generic_identify,
281 .c_size_cache = amd_size_cache,
282 };
284 int __init amd_init_cpu(void)
285 {
286 cpu_devs[X86_VENDOR_AMD] = &amd_cpu_dev;
287 return 0;
288 }
290 //early_arch_initcall(amd_init_cpu);