ia64/xen-unstable

view xen/arch/ia64/linux-xen/setup.c @ 15154:b46c2ff6dfb0

[IA64] Fix initialization order for buddy allocator

Fix initialization order of buddy allocator to avoid panic
on machines with multi NUMA node.

Signed-off-by: Daisuke Nishimura <nishimura@mxp.nes.nec.co.jp>
author Alex Williamson <alex.williamson@hp.com>
date Thu May 31 14:47:08 2007 -0600 (2007-05-31)
parents 034f3e20ad10
children 4108c2589fd1
line source
1 /*
2 * Architecture-specific setup.
3 *
4 * Copyright (C) 1998-2001, 2003-2004 Hewlett-Packard Co
5 * David Mosberger-Tang <davidm@hpl.hp.com>
6 * Stephane Eranian <eranian@hpl.hp.com>
7 * Copyright (C) 2000, 2004 Intel Corp
8 * Rohit Seth <rohit.seth@intel.com>
9 * Suresh Siddha <suresh.b.siddha@intel.com>
10 * Gordon Jin <gordon.jin@intel.com>
11 * Copyright (C) 1999 VA Linux Systems
12 * Copyright (C) 1999 Walt Drummond <drummond@valinux.com>
13 *
14 * 12/26/04 S.Siddha, G.Jin, R.Seth
15 * Add multi-threading and multi-core detection
16 * 11/12/01 D.Mosberger Convert get_cpuinfo() to seq_file based show_cpuinfo().
17 * 04/04/00 D.Mosberger renamed cpu_initialized to cpu_online_map
18 * 03/31/00 R.Seth cpu_initialized and current->processor fixes
19 * 02/04/00 D.Mosberger some more get_cpuinfo fixes...
20 * 02/01/00 R.Seth fixed get_cpuinfo for SMP
21 * 01/07/99 S.Eranian added the support for command line argument
22 * 06/24/99 W.Drummond added boot_cpu_data.
23 * 05/28/05 Z. Menyhart Dynamic stride size for "flush_icache_range()"
24 */
25 #include <linux/config.h>
26 #include <linux/module.h>
27 #include <linux/init.h>
29 #include <linux/acpi.h>
30 #include <linux/bootmem.h>
31 #include <linux/console.h>
32 #include <linux/delay.h>
33 #include <linux/kernel.h>
34 #include <linux/shutdown.h>
35 #include <linux/sched.h>
36 #include <linux/seq_file.h>
37 #include <linux/string.h>
38 #include <linux/threads.h>
39 #include <linux/tty.h>
40 #include <linux/serial.h>
41 #include <linux/serial_core.h>
42 #include <linux/efi.h>
43 #include <linux/initrd.h>
44 #ifndef XEN
45 #include <linux/platform.h>
46 #include <linux/pm.h>
47 #endif
49 #include <asm/ia32.h>
50 #include <asm/machvec.h>
51 #include <asm/mca.h>
52 #include <asm/meminit.h>
53 #include <asm/page.h>
54 #include <asm/patch.h>
55 #include <asm/pgtable.h>
56 #include <asm/processor.h>
57 #include <asm/sal.h>
58 #include <asm/sections.h>
59 #include <asm/serial.h>
60 #include <asm/setup.h>
61 #include <asm/smp.h>
62 #include <asm/system.h>
63 #include <asm/unistd.h>
64 #ifdef XEN
65 #include <asm/vmx.h>
66 #include <asm/io.h>
67 #endif
69 #if defined(CONFIG_SMP) && (IA64_CPU_SIZE > PAGE_SIZE)
70 # error "struct cpuinfo_ia64 too big!"
71 #endif
73 #ifdef CONFIG_SMP
74 unsigned long __per_cpu_offset[NR_CPUS];
75 EXPORT_SYMBOL(__per_cpu_offset);
76 #endif
78 DEFINE_PER_CPU(struct cpuinfo_ia64, cpu_info);
79 #ifdef XEN
80 DEFINE_PER_CPU(cpu_kr_ia64_t, cpu_kr);
81 #endif
82 DEFINE_PER_CPU(unsigned long, local_per_cpu_offset);
83 DEFINE_PER_CPU(unsigned long, ia64_phys_stacked_size_p8);
84 unsigned long ia64_cycles_per_usec;
85 struct ia64_boot_param *ia64_boot_param;
86 struct screen_info screen_info;
87 unsigned long vga_console_iobase;
88 unsigned long vga_console_membase;
90 unsigned long ia64_max_cacheline_size;
91 unsigned long ia64_iobase; /* virtual address for I/O accesses */
92 EXPORT_SYMBOL(ia64_iobase);
93 struct io_space io_space[MAX_IO_SPACES];
94 EXPORT_SYMBOL(io_space);
95 unsigned int num_io_spaces;
97 #ifdef XEN
98 extern void early_cmdline_parse(char **);
99 extern unsigned int ns16550_com1_gsi;
100 #endif
102 /*
103 * "flush_icache_range()" needs to know what processor dependent stride size to use
104 * when it makes i-cache(s) coherent with d-caches.
105 */
106 #define I_CACHE_STRIDE_SHIFT 5 /* Safest way to go: 32 bytes by 32 bytes */
107 unsigned long ia64_i_cache_stride_shift = ~0;
109 #ifdef XEN
110 #define D_CACHE_STRIDE_SHIFT 5 /* Safest. */
111 unsigned long ia64_d_cache_stride_shift = ~0;
112 #endif
114 /*
115 * The merge_mask variable needs to be set to (max(iommu_page_size(iommu)) - 1). This
116 * mask specifies a mask of address bits that must be 0 in order for two buffers to be
117 * mergeable by the I/O MMU (i.e., the end address of the first buffer and the start
118 * address of the second buffer must be aligned to (merge_mask+1) in order to be
119 * mergeable). By default, we assume there is no I/O MMU which can merge physically
120 * discontiguous buffers, so we set the merge_mask to ~0UL, which corresponds to a iommu
121 * page-size of 2^64.
122 */
123 unsigned long ia64_max_iommu_merge_mask = ~0UL;
124 EXPORT_SYMBOL(ia64_max_iommu_merge_mask);
126 /*
127 * We use a special marker for the end of memory and it uses the extra (+1) slot
128 */
129 struct rsvd_region rsvd_region[IA64_MAX_RSVD_REGIONS + 1];
130 int num_rsvd_regions;
133 /*
134 * Filter incoming memory segments based on the primitive map created from the boot
135 * parameters. Segments contained in the map are removed from the memory ranges. A
136 * caller-specified function is called with the memory ranges that remain after filtering.
137 * This routine does not assume the incoming segments are sorted.
138 */
139 int
140 filter_rsvd_memory (unsigned long start, unsigned long end, void *arg)
141 {
142 unsigned long range_start, range_end, prev_start;
143 void (*func)(unsigned long, unsigned long, int);
144 int i;
146 #if IGNORE_PFN0
147 if (start == PAGE_OFFSET) {
148 printk(KERN_WARNING "warning: skipping physical page 0\n");
149 start += PAGE_SIZE;
150 if (start >= end) return 0;
151 }
152 #endif
153 /*
154 * lowest possible address(walker uses virtual)
155 */
156 prev_start = PAGE_OFFSET;
157 func = arg;
159 for (i = 0; i < num_rsvd_regions; ++i) {
160 range_start = max(start, prev_start);
161 range_end = min(end, rsvd_region[i].start);
163 if (range_start < range_end)
164 #ifdef XEN
165 {
166 /* init_boot_pages requires "ps, pe" */
167 printk("Init boot pages: 0x%lx -> 0x%lx.\n",
168 __pa(range_start), __pa(range_end));
169 (*func)(__pa(range_start), __pa(range_end), 0);
170 }
171 #else
172 call_pernode_memory(__pa(range_start), range_end - range_start, func);
173 #endif
175 /* nothing more available in this segment */
176 if (range_end == end) return 0;
178 prev_start = rsvd_region[i].end;
179 }
180 /* end of memory marker allows full processing inside loop body */
181 return 0;
182 }
184 static void
185 sort_regions (struct rsvd_region *rsvd_region, int max)
186 {
187 int j;
189 /* simple bubble sorting */
190 while (max--) {
191 for (j = 0; j < max; ++j) {
192 if (rsvd_region[j].start > rsvd_region[j+1].start) {
193 struct rsvd_region tmp;
194 tmp = rsvd_region[j];
195 rsvd_region[j] = rsvd_region[j + 1];
196 rsvd_region[j + 1] = tmp;
197 }
198 }
199 }
200 }
202 /**
203 * reserve_memory - setup reserved memory areas
204 *
205 * Setup the reserved memory areas set aside for the boot parameters,
206 * initrd, etc. There are currently %IA64_MAX_RSVD_REGIONS defined,
207 * see include/asm-ia64/meminit.h if you need to define more.
208 */
209 void
210 reserve_memory (void)
211 {
212 int n = 0;
214 /*
215 * none of the entries in this table overlap
216 */
217 rsvd_region[n].start = (unsigned long) ia64_boot_param;
218 rsvd_region[n].end = rsvd_region[n].start + sizeof(*ia64_boot_param);
219 n++;
221 rsvd_region[n].start = (unsigned long) __va(ia64_boot_param->efi_memmap);
222 rsvd_region[n].end = rsvd_region[n].start + ia64_boot_param->efi_memmap_size;
223 n++;
225 rsvd_region[n].start = (unsigned long) __va(ia64_boot_param->command_line);
226 rsvd_region[n].end = (rsvd_region[n].start
227 + strlen(__va(ia64_boot_param->command_line)) + 1);
228 n++;
230 rsvd_region[n].start = (unsigned long) ia64_imva((void *)KERNEL_START);
231 #ifdef XEN
232 /* Reserve xen image/bitmap/xen-heap */
233 rsvd_region[n].end = rsvd_region[n].start + xenheap_size;
234 #else
235 rsvd_region[n].end = (unsigned long) ia64_imva(_end);
236 #endif
237 n++;
239 #ifdef XEN
240 rsvd_region[n].start = (unsigned long) __va(ia64_boot_param->domain_start);
241 rsvd_region[n].end = (rsvd_region[n].start + ia64_boot_param->domain_size);
242 n++;
243 #endif
245 #if defined(XEN)||defined(CONFIG_BLK_DEV_INITRD)
246 if (ia64_boot_param->initrd_start) {
247 rsvd_region[n].start = (unsigned long)__va(ia64_boot_param->initrd_start);
248 rsvd_region[n].end = rsvd_region[n].start + ia64_boot_param->initrd_size;
249 n++;
250 }
251 #endif
253 efi_memmap_init(&rsvd_region[n].start, &rsvd_region[n].end);
254 n++;
256 /* end of memory marker */
257 rsvd_region[n].start = ~0UL;
258 rsvd_region[n].end = ~0UL;
259 n++;
261 num_rsvd_regions = n;
263 sort_regions(rsvd_region, num_rsvd_regions);
264 }
266 /**
267 * find_initrd - get initrd parameters from the boot parameter structure
268 *
269 * Grab the initrd start and end from the boot parameter struct given us by
270 * the boot loader.
271 */
272 void
273 find_initrd (void)
274 {
275 #ifdef CONFIG_BLK_DEV_INITRD
276 if (ia64_boot_param->initrd_start) {
277 initrd_start = (unsigned long)__va(ia64_boot_param->initrd_start);
278 initrd_end = initrd_start+ia64_boot_param->initrd_size;
280 printk(KERN_INFO "Initial ramdisk at: 0x%lx (%lu bytes)\n",
281 initrd_start, ia64_boot_param->initrd_size);
282 }
283 #endif
284 }
286 static void __init
287 io_port_init (void)
288 {
289 extern unsigned long ia64_iobase;
290 unsigned long phys_iobase;
292 /*
293 * Set `iobase' to the appropriate address in region 6 (uncached access range).
294 *
295 * The EFI memory map is the "preferred" location to get the I/O port space base,
296 * rather the relying on AR.KR0. This should become more clear in future SAL
297 * specs. We'll fall back to getting it out of AR.KR0 if no appropriate entry is
298 * found in the memory map.
299 */
300 phys_iobase = efi_get_iobase();
301 if (phys_iobase)
302 /* set AR.KR0 since this is all we use it for anyway */
303 ia64_set_kr(IA64_KR_IO_BASE, phys_iobase);
304 else {
305 phys_iobase = ia64_get_kr(IA64_KR_IO_BASE);
306 printk(KERN_INFO "No I/O port range found in EFI memory map, falling back "
307 "to AR.KR0\n");
308 printk(KERN_INFO "I/O port base = 0x%lx\n", phys_iobase);
309 }
310 ia64_iobase = (unsigned long) ioremap(phys_iobase, 0);
312 /* setup legacy IO port space */
313 io_space[0].mmio_base = ia64_iobase;
314 io_space[0].sparse = 1;
315 num_io_spaces = 1;
316 }
318 #ifdef XEN
319 static int __init
320 acpi_oem_console_setup(void)
321 {
322 extern struct ns16550_defaults ns16550_com1;
323 efi_system_table_t *systab;
324 efi_config_table_t *tables;
325 struct acpi20_table_rsdp *rsdp = NULL;
326 struct acpi_table_xsdt *xsdt;
327 struct acpi_table_header *hdr;
328 int i;
330 /* Don't duplicate setup if an HCDP table is present */
331 if (efi.hcdp)
332 return -ENODEV;
334 /* Manually walk firmware provided tables to get to the XSDT. */
335 systab = __va(ia64_boot_param->efi_systab);
337 if (!systab || systab->hdr.signature != EFI_SYSTEM_TABLE_SIGNATURE)
338 return -ENODEV;
340 tables = __va(systab->tables);
342 for (i = 0 ; i < (int)systab->nr_tables && !rsdp ; i++) {
343 if (efi_guidcmp(tables[i].guid, ACPI_20_TABLE_GUID) == 0)
344 rsdp =
345 (struct acpi20_table_rsdp *)__va(tables[i].table);
346 }
348 if (!rsdp || strncmp(rsdp->signature, RSDP_SIG, sizeof(RSDP_SIG) - 1))
349 return -ENODEV;
351 xsdt = (struct acpi_table_xsdt *)__va(rsdp->xsdt_address);
352 hdr = &xsdt->header;
354 if (strncmp(hdr->signature, XSDT_SIG, sizeof(XSDT_SIG) - 1))
355 return -ENODEV;
357 /* Looking for Fujitsu PRIMEQUEST systems */
358 if (!strncmp(hdr->oem_id, "FUJITSPQ", 8) &&
359 (!strncmp(hdr->oem_table_id, "PQ", 2))){
360 ns16550_com1.baud = BAUD_AUTO;
361 ns16550_com1.io_base = 0x3f8;
362 ns16550_com1.irq = ns16550_com1_gsi = 4;
363 return 0;
364 }
366 /*
367 * Looking for Intel Tiger systems
368 * Tiger 2: SR870BH2
369 * Tiger 4: SR870BN4
370 */
371 if (strncmp(hdr->oem_id, "INTEL", 5) ||
372 (!strncmp(hdr->oem_table_id, "SR870BH2", 8) &&
373 !strncmp(hdr->oem_table_id, "SR870BN4", 8)))
374 return -ENODEV;
376 ns16550_com1.baud = BAUD_AUTO;
377 ns16550_com1.io_base = 0x2f8;
378 ns16550_com1.irq = 3;
380 return 0;
381 }
382 #endif
384 /**
385 * early_console_setup - setup debugging console
386 *
387 * Consoles started here require little enough setup that we can start using
388 * them very early in the boot process, either right after the machine
389 * vector initialization, or even before if the drivers can detect their hw.
390 *
391 * Returns non-zero if a console couldn't be setup.
392 */
393 static inline int __init
394 early_console_setup (char *cmdline)
395 {
396 int earlycons = 0;
398 #ifdef CONFIG_SERIAL_SGI_L1_CONSOLE
399 {
400 extern int sn_serial_console_early_setup(void);
401 if (!sn_serial_console_early_setup())
402 earlycons++;
403 }
404 #endif
405 #ifdef CONFIG_EFI_PCDP
406 if (!efi_setup_pcdp_console(cmdline))
407 earlycons++;
408 #endif
409 #ifdef CONFIG_SERIAL_8250_CONSOLE
410 if (!early_serial_console_init(cmdline))
411 earlycons++;
412 #endif
414 #ifdef XEN
415 if (!acpi_oem_console_setup())
416 earlycons++;
417 #endif
418 return (earlycons) ? 0 : -1;
419 }
421 static inline void
422 mark_bsp_online (void)
423 {
424 #ifdef CONFIG_SMP
425 /* If we register an early console, allow CPU 0 to printk */
426 cpu_set(smp_processor_id(), cpu_online_map);
427 #endif
428 }
430 #ifdef CONFIG_SMP
431 static void
432 check_for_logical_procs (void)
433 {
434 pal_logical_to_physical_t info;
435 s64 status;
437 status = ia64_pal_logical_to_phys(0, &info);
438 if (status == -1) {
439 printk(KERN_INFO "No logical to physical processor mapping "
440 "available\n");
441 return;
442 }
443 if (status) {
444 printk(KERN_ERR "ia64_pal_logical_to_phys failed with %ld\n",
445 status);
446 return;
447 }
448 /*
449 * Total number of siblings that BSP has. Though not all of them
450 * may have booted successfully. The correct number of siblings
451 * booted is in info.overview_num_log.
452 */
453 smp_num_siblings = info.overview_tpc;
454 smp_num_cpucores = info.overview_cpp;
455 }
456 #endif
458 void __init
459 #ifdef XEN
460 early_setup_arch (char **cmdline_p)
461 #else
462 setup_arch (char **cmdline_p)
463 #endif
464 {
465 unw_init();
467 #ifndef XEN
468 ia64_patch_vtop((u64) __start___vtop_patchlist, (u64) __end___vtop_patchlist);
469 #endif
471 *cmdline_p = __va(ia64_boot_param->command_line);
472 #ifndef XEN
473 strlcpy(saved_command_line, *cmdline_p, COMMAND_LINE_SIZE);
474 #else
475 early_cmdline_parse(cmdline_p);
476 cmdline_parse(*cmdline_p);
477 #endif
479 efi_init();
480 io_port_init();
482 #ifdef CONFIG_IA64_GENERIC
483 {
484 const char *mvec_name = strstr (*cmdline_p, "machvec=");
485 char str[64];
487 if (mvec_name) {
488 const char *end;
489 size_t len;
491 mvec_name += 8;
492 end = strchr (mvec_name, ' ');
493 if (end)
494 len = end - mvec_name;
495 else
496 len = strlen (mvec_name);
497 len = min(len, sizeof (str) - 1);
498 strlcpy (str, mvec_name, len);
499 mvec_name = str;
500 } else
501 mvec_name = acpi_get_sysname();
502 machvec_init(mvec_name);
503 }
504 #endif
506 if (early_console_setup(*cmdline_p) == 0)
507 mark_bsp_online();
509 #ifdef CONFIG_ACPI_BOOT
510 /* Initialize the ACPI boot-time table parser */
511 acpi_table_init();
512 # ifdef CONFIG_ACPI_NUMA
513 acpi_numa_init();
514 # endif
515 #else
516 # ifdef CONFIG_SMP
517 smp_build_cpu_map(); /* happens, e.g., with the Ski simulator */
518 # endif
519 #endif /* CONFIG_APCI_BOOT */
521 #ifdef XEN
522 }
524 void __init
525 late_setup_arch (char **cmdline_p)
526 {
527 #endif
528 #ifndef XEN
529 find_memory();
530 #endif
532 /* process SAL system table: */
533 ia64_sal_init(efi.sal_systab);
535 #ifdef CONFIG_SMP
536 #ifdef XEN
537 init_smp_config ();
538 #endif
540 cpu_physical_id(0) = hard_smp_processor_id();
542 cpu_set(0, cpu_sibling_map[0]);
543 cpu_set(0, cpu_core_map[0]);
545 check_for_logical_procs();
546 if (smp_num_cpucores > 1)
547 printk(KERN_INFO
548 "cpu package is Multi-Core capable: number of cores=%d\n",
549 smp_num_cpucores);
550 if (smp_num_siblings > 1)
551 printk(KERN_INFO
552 "cpu package is Multi-Threading capable: number of siblings=%d\n",
553 smp_num_siblings);
554 #endif
556 #ifdef XEN
557 identify_vmx_feature();
558 #endif
560 cpu_init(); /* initialize the bootstrap CPU */
562 #ifdef CONFIG_ACPI_BOOT
563 acpi_boot_init();
564 #endif
566 #ifdef CONFIG_VT
567 if (!conswitchp) {
568 # if defined(CONFIG_DUMMY_CONSOLE)
569 conswitchp = &dummy_con;
570 # endif
571 # if defined(CONFIG_VGA_CONSOLE)
572 /*
573 * Non-legacy systems may route legacy VGA MMIO range to system
574 * memory. vga_con probes the MMIO hole, so memory looks like
575 * a VGA device to it. The EFI memory map can tell us if it's
576 * memory so we can avoid this problem.
577 */
578 if (efi_mem_type(0xA0000) != EFI_CONVENTIONAL_MEMORY)
579 conswitchp = &vga_con;
580 # endif
581 }
582 #endif
584 /* enable IA-64 Machine Check Abort Handling unless disabled */
585 if (!strstr(saved_command_line, "nomca"))
586 ia64_mca_init();
588 platform_setup(cmdline_p);
589 paging_init();
590 }
592 #ifndef XEN
593 /*
594 * Display cpu info for all cpu's.
595 */
596 static int
597 show_cpuinfo (struct seq_file *m, void *v)
598 {
599 #ifdef CONFIG_SMP
600 # define lpj c->loops_per_jiffy
601 # define cpunum c->cpu
602 #else
603 # define lpj loops_per_jiffy
604 # define cpunum 0
605 #endif
606 static struct {
607 unsigned long mask;
608 const char *feature_name;
609 } feature_bits[] = {
610 { 1UL << 0, "branchlong" },
611 { 1UL << 1, "spontaneous deferral"},
612 { 1UL << 2, "16-byte atomic ops" }
613 };
614 char family[32], features[128], *cp, sep;
615 struct cpuinfo_ia64 *c = v;
616 unsigned long mask;
617 int i;
619 mask = c->features;
621 switch (c->family) {
622 case 0x07: memcpy(family, "Itanium", 8); break;
623 case 0x1f: memcpy(family, "Itanium 2", 10); break;
624 default: snprintf(family, sizeof(family), "%u", c->family); break;
625 }
627 /* build the feature string: */
628 memcpy(features, " standard", 10);
629 cp = features;
630 sep = 0;
631 for (i = 0; i < (int) ARRAY_SIZE(feature_bits); ++i) {
632 if (mask & feature_bits[i].mask) {
633 if (sep)
634 *cp++ = sep;
635 sep = ',';
636 *cp++ = ' ';
637 strlcpy(cp, feature_bits[i].feature_name, sizeof(features));
638 cp += strlen(feature_bits[i].feature_name);
639 mask &= ~feature_bits[i].mask;
640 }
641 }
642 if (mask) {
643 /* print unknown features as a hex value: */
644 if (sep)
645 *cp++ = sep;
646 snprintf(cp, sizeof(features) - (cp - features), " 0x%lx", mask);
647 }
649 seq_printf(m,
650 "processor : %d\n"
651 "vendor : %s\n"
652 "arch : IA-64\n"
653 "family : %s\n"
654 "model : %u\n"
655 "revision : %u\n"
656 "archrev : %u\n"
657 "features :%s\n" /* don't change this---it _is_ right! */
658 "cpu number : %lu\n"
659 "cpu regs : %u\n"
660 "cpu MHz : %lu.%06lu\n"
661 "itc MHz : %lu.%06lu\n"
662 "BogoMIPS : %lu.%02lu\n",
663 cpunum, c->vendor, family, c->model, c->revision, c->archrev,
664 features, c->ppn, c->number,
665 c->proc_freq / 1000000, c->proc_freq % 1000000,
666 c->itc_freq / 1000000, c->itc_freq % 1000000,
667 lpj*HZ/500000, (lpj*HZ/5000) % 100);
668 #ifdef CONFIG_SMP
669 seq_printf(m, "siblings : %u\n", c->num_log);
670 if (c->threads_per_core > 1 || c->cores_per_socket > 1)
671 seq_printf(m,
672 "physical id: %u\n"
673 "core id : %u\n"
674 "thread id : %u\n",
675 c->socket_id, c->core_id, c->thread_id);
676 #endif
677 seq_printf(m,"\n");
679 return 0;
680 }
682 static void *
683 c_start (struct seq_file *m, loff_t *pos)
684 {
685 #ifdef CONFIG_SMP
686 while (*pos < NR_CPUS && !cpu_isset(*pos, cpu_online_map))
687 ++*pos;
688 #endif
689 return *pos < NR_CPUS ? cpu_data(*pos) : NULL;
690 }
692 static void *
693 c_next (struct seq_file *m, void *v, loff_t *pos)
694 {
695 ++*pos;
696 return c_start(m, pos);
697 }
699 static void
700 c_stop (struct seq_file *m, void *v)
701 {
702 }
704 struct seq_operations cpuinfo_op = {
705 .start = c_start,
706 .next = c_next,
707 .stop = c_stop,
708 .show = show_cpuinfo
709 };
710 #endif /* XEN */
712 void
713 identify_cpu (struct cpuinfo_ia64 *c)
714 {
715 union {
716 unsigned long bits[5];
717 struct {
718 /* id 0 & 1: */
719 char vendor[16];
721 /* id 2 */
722 u64 ppn; /* processor serial number */
724 /* id 3: */
725 unsigned number : 8;
726 unsigned revision : 8;
727 unsigned model : 8;
728 unsigned family : 8;
729 unsigned archrev : 8;
730 unsigned reserved : 24;
732 /* id 4: */
733 u64 features;
734 } field;
735 } cpuid;
736 pal_vm_info_1_u_t vm1;
737 pal_vm_info_2_u_t vm2;
738 pal_status_t status;
739 unsigned long impl_va_msb = 50, phys_addr_size = 44; /* Itanium defaults */
740 int i;
742 for (i = 0; i < 5; ++i)
743 cpuid.bits[i] = ia64_get_cpuid(i);
745 memcpy(c->vendor, cpuid.field.vendor, 16);
746 #ifdef CONFIG_SMP
747 c->cpu = smp_processor_id();
749 /* below default values will be overwritten by identify_siblings()
750 * for Multi-Threading/Multi-Core capable cpu's
751 */
752 c->threads_per_core = c->cores_per_socket = c->num_log = 1;
753 c->socket_id = -1;
755 identify_siblings(c);
756 #endif
757 c->ppn = cpuid.field.ppn;
758 c->number = cpuid.field.number;
759 c->revision = cpuid.field.revision;
760 c->model = cpuid.field.model;
761 c->family = cpuid.field.family;
762 c->archrev = cpuid.field.archrev;
763 c->features = cpuid.field.features;
765 status = ia64_pal_vm_summary(&vm1, &vm2);
766 if (status == PAL_STATUS_SUCCESS) {
767 impl_va_msb = vm2.pal_vm_info_2_s.impl_va_msb;
768 phys_addr_size = vm1.pal_vm_info_1_s.phys_add_size;
769 }
770 c->unimpl_va_mask = ~((7L<<61) | ((1L << (impl_va_msb + 1)) - 1));
771 c->unimpl_pa_mask = ~((1L<<63) | ((1L << phys_addr_size) - 1));
773 #ifdef XEN
774 /* If vmx feature is on, do necessary initialization for vmx */
775 if (vmx_enabled)
776 vmx_init_env();
777 #endif
778 }
780 void
781 setup_per_cpu_areas (void)
782 {
783 /* start_kernel() requires this... */
784 }
786 /*
787 * Calculate the max. cache line size.
788 *
789 * In addition, the minimum of the i-cache stride sizes is calculated for
790 * "flush_icache_range()".
791 */
792 static void
793 get_max_cacheline_size (void)
794 {
795 unsigned long line_size, max = 1;
796 u64 l, levels, unique_caches;
797 pal_cache_config_info_t cci;
798 s64 status;
800 status = ia64_pal_cache_summary(&levels, &unique_caches);
801 if (status != 0) {
802 printk(KERN_ERR "%s: ia64_pal_cache_summary() failed (status=%ld)\n",
803 __FUNCTION__, status);
804 max = SMP_CACHE_BYTES;
805 /* Safest setup for "flush_icache_range()" */
806 ia64_i_cache_stride_shift = I_CACHE_STRIDE_SHIFT;
807 #ifdef XEN
808 ia64_d_cache_stride_shift = D_CACHE_STRIDE_SHIFT;
809 #endif
810 goto out;
811 }
813 for (l = 0; l < levels; ++l) {
814 status = ia64_pal_cache_config_info(l, /* cache_type (data_or_unified)= */ 2,
815 &cci);
816 if (status != 0) {
817 printk(KERN_ERR
818 "%s: ia64_pal_cache_config_info(l=%lu, 2) failed (status=%ld)\n",
819 __FUNCTION__, l, status);
820 max = SMP_CACHE_BYTES;
821 /* The safest setup for "flush_icache_range()" */
822 cci.pcci_stride = I_CACHE_STRIDE_SHIFT;
823 cci.pcci_unified = 1;
824 }
825 #ifdef XEN
826 if (cci.pcci_stride < ia64_d_cache_stride_shift)
827 ia64_d_cache_stride_shift = cci.pcci_stride;
828 #endif
829 line_size = 1 << cci.pcci_line_size;
830 if (line_size > max)
831 max = line_size;
832 if (!cci.pcci_unified) {
833 status = ia64_pal_cache_config_info(l,
834 /* cache_type (instruction)= */ 1,
835 &cci);
836 if (status != 0) {
837 printk(KERN_ERR
838 "%s: ia64_pal_cache_config_info(l=%lu, 1) failed (status=%ld)\n",
839 __FUNCTION__, l, status);
840 /* The safest setup for "flush_icache_range()" */
841 cci.pcci_stride = I_CACHE_STRIDE_SHIFT;
842 }
843 }
844 if (cci.pcci_stride < ia64_i_cache_stride_shift)
845 ia64_i_cache_stride_shift = cci.pcci_stride;
846 }
847 out:
848 if (max > ia64_max_cacheline_size)
849 ia64_max_cacheline_size = max;
850 #ifdef XEN
851 if (ia64_d_cache_stride_shift > ia64_i_cache_stride_shift)
852 ia64_d_cache_stride_shift = ia64_i_cache_stride_shift;
853 #endif
855 }
857 /*
858 * cpu_init() initializes state that is per-CPU. This function acts
859 * as a 'CPU state barrier', nothing should get across.
860 */
861 void
862 cpu_init (void)
863 {
864 extern void __devinit ia64_mmu_init (void *);
865 unsigned long num_phys_stacked;
866 #ifndef XEN
867 pal_vm_info_2_u_t vmi;
868 unsigned int max_ctx;
869 #endif
870 struct cpuinfo_ia64 *cpu_info;
871 void *cpu_data;
873 cpu_data = per_cpu_init();
875 #ifdef XEN
876 printk(XENLOG_DEBUG "cpu_init: current=%p\n", current);
877 #endif
879 /*
880 * We set ar.k3 so that assembly code in MCA handler can compute
881 * physical addresses of per cpu variables with a simple:
882 * phys = ar.k3 + &per_cpu_var
883 */
884 ia64_set_kr(IA64_KR_PER_CPU_DATA,
885 ia64_tpa(cpu_data) - (long) __per_cpu_start);
887 get_max_cacheline_size();
889 /*
890 * We can't pass "local_cpu_data" to identify_cpu() because we haven't called
891 * ia64_mmu_init() yet. And we can't call ia64_mmu_init() first because it
892 * depends on the data returned by identify_cpu(). We break the dependency by
893 * accessing cpu_data() through the canonical per-CPU address.
894 */
895 cpu_info = cpu_data + ((char *) &__ia64_per_cpu_var(cpu_info) - __per_cpu_start);
896 identify_cpu(cpu_info);
898 #ifdef CONFIG_MCKINLEY
899 {
900 # define FEATURE_SET 16
901 struct ia64_pal_retval iprv;
903 if (cpu_info->family == 0x1f) {
904 PAL_CALL_PHYS(iprv, PAL_PROC_GET_FEATURES, 0, FEATURE_SET, 0);
905 if ((iprv.status == 0) && (iprv.v0 & 0x80) && (iprv.v2 & 0x80))
906 PAL_CALL_PHYS(iprv, PAL_PROC_SET_FEATURES,
907 (iprv.v1 | 0x80), FEATURE_SET, 0);
908 }
909 }
910 #endif
912 /* Clear the stack memory reserved for pt_regs: */
913 memset(ia64_task_regs(current), 0, sizeof(struct pt_regs));
915 ia64_set_kr(IA64_KR_FPU_OWNER, 0);
917 /*
918 * Initialize the page-table base register to a global
919 * directory with all zeroes. This ensure that we can handle
920 * TLB-misses to user address-space even before we created the
921 * first user address-space. This may happen, e.g., due to
922 * aggressive use of lfetch.fault.
923 */
924 ia64_set_kr(IA64_KR_PT_BASE, __pa(ia64_imva(empty_zero_page)));
926 /*
927 * Initialize default control register to defer speculative faults except
928 * for those arising from TLB misses, which are not deferred. The
929 * kernel MUST NOT depend on a particular setting of these bits (in other words,
930 * the kernel must have recovery code for all speculative accesses). Turn on
931 * dcr.lc as per recommendation by the architecture team. Most IA-32 apps
932 * shouldn't be affected by this (moral: keep your ia32 locks aligned and you'll
933 * be fine).
934 */
935 #ifdef XEN
936 ia64_setreg(_IA64_REG_CR_DCR, IA64_DEFAULT_DCR_BITS);
937 #else
938 ia64_setreg(_IA64_REG_CR_DCR, ( IA64_DCR_DP | IA64_DCR_DK | IA64_DCR_DX | IA64_DCR_DR
939 | IA64_DCR_DA | IA64_DCR_DD | IA64_DCR_LC));
940 #endif
941 #ifndef XEN
942 atomic_inc(&init_mm.mm_count);
943 current->active_mm = &init_mm;
944 #endif
945 #ifndef XEN
946 if (current->mm)
947 BUG();
948 #endif
951 #ifdef XEN
952 ia64_fph_enable();
953 __ia64_init_fpu();
954 #endif
956 ia64_mmu_init(ia64_imva(cpu_data));
957 ia64_mca_cpu_init(ia64_imva(cpu_data));
959 #ifdef CONFIG_IA32_SUPPORT
960 ia32_cpu_init();
961 #endif
963 /* Clear ITC to eliminiate sched_clock() overflows in human time. */
964 ia64_set_itc(0);
966 /* disable all local interrupt sources: */
967 ia64_set_itv(1 << 16);
968 ia64_set_lrr0(1 << 16);
969 ia64_set_lrr1(1 << 16);
970 ia64_setreg(_IA64_REG_CR_PMV, 1 << 16);
971 ia64_setreg(_IA64_REG_CR_CMCV, 1 << 16);
973 /* clear TPR & XTP to enable all interrupt classes: */
974 ia64_setreg(_IA64_REG_CR_TPR, 0);
975 #ifdef CONFIG_SMP
976 normal_xtp();
977 #endif
979 #ifndef XEN
980 /* set ia64_ctx.max_rid to the maximum RID that is supported by all CPUs: */
981 if (ia64_pal_vm_summary(NULL, &vmi) == 0)
982 max_ctx = (1U << (vmi.pal_vm_info_2_s.rid_size - 3)) - 1;
983 else {
984 printk(KERN_WARNING "cpu_init: PAL VM summary failed, assuming 18 RID bits\n");
985 max_ctx = (1U << 15) - 1; /* use architected minimum */
986 }
987 while (max_ctx < ia64_ctx.max_ctx) {
988 unsigned int old = ia64_ctx.max_ctx;
989 if (cmpxchg(&ia64_ctx.max_ctx, old, max_ctx) == old)
990 break;
991 }
992 #endif
994 if (ia64_pal_rse_info(&num_phys_stacked, NULL) != 0) {
995 printk(KERN_WARNING "cpu_init: PAL RSE info failed; assuming 96 physical "
996 "stacked regs\n");
997 num_phys_stacked = 96;
998 }
999 /* size of physical stacked register partition plus 8 bytes: */
1000 __get_cpu_var(ia64_phys_stacked_size_p8) = num_phys_stacked*8 + 8;
1001 platform_cpu_init();
1002 #ifndef XEN
1003 pm_idle = default_idle;
1004 #endif
1006 #ifdef XEN
1007 /* surrender usage of kernel registers to domain, use percpu area instead */
1008 __get_cpu_var(cpu_kr)._kr[IA64_KR_IO_BASE] = ia64_get_kr(IA64_KR_IO_BASE);
1009 __get_cpu_var(cpu_kr)._kr[IA64_KR_PER_CPU_DATA] = ia64_get_kr(IA64_KR_PER_CPU_DATA);
1010 __get_cpu_var(cpu_kr)._kr[IA64_KR_CURRENT_STACK] = ia64_get_kr(IA64_KR_CURRENT_STACK);
1011 __get_cpu_var(cpu_kr)._kr[IA64_KR_FPU_OWNER] = ia64_get_kr(IA64_KR_FPU_OWNER);
1012 __get_cpu_var(cpu_kr)._kr[IA64_KR_CURRENT] = ia64_get_kr(IA64_KR_CURRENT);
1013 __get_cpu_var(cpu_kr)._kr[IA64_KR_PT_BASE] = ia64_get_kr(IA64_KR_PT_BASE);
1014 #endif
1017 #ifndef XEN
1018 void
1019 check_bugs (void)
1021 ia64_patch_mckinley_e9((unsigned long) __start___mckinley_e9_bundles,
1022 (unsigned long) __end___mckinley_e9_bundles);
1024 #endif