ia64/xen-unstable

view xen/include/asm-ia64/xenkregs.h @ 16785:af3550f53874

[IA64] domheap: Don't pin xenheap down. Now it's unnecessary.

Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
author Alex Williamson <alex.williamson@hp.com>
date Thu Jan 17 12:05:43 2008 -0700 (2008-01-17)
parents 6f7e6608cb74
children
line source
1 #ifndef _ASM_IA64_XENKREGS_H
2 #define _ASM_IA64_XENKREGS_H
4 /*
5 * Translation registers:
6 */
7 #define IA64_TR_MAPPED_REGS 3 /* dtr3: vcpu mapped regs */
8 #define IA64_TR_SHARED_INFO 4 /* dtr4: page shared with domain */
9 #define IA64_TR_VHPT 5 /* dtr5: vhpt */
11 #define IA64_TR_VPD 2 /* itr2: vpd */
13 #define IA64_DTR_GUEST_KERNEL 7
14 #define IA64_ITR_GUEST_KERNEL 2
15 /* Processor status register bits: */
16 #define IA64_PSR_VM_BIT 46
17 #define IA64_PSR_VM (__IA64_UL(1) << IA64_PSR_VM_BIT)
19 #define IA64_DEFAULT_DCR_BITS (IA64_DCR_PP | IA64_DCR_LC | IA64_DCR_DM | \
20 IA64_DCR_DP | IA64_DCR_DK | IA64_DCR_DX | \
21 IA64_DCR_DR | IA64_DCR_DA | IA64_DCR_DD)
23 // note IA64_PSR_PK removed from following, why is this necessary?
24 #define DELIVER_PSR_SET (IA64_PSR_IC | IA64_PSR_I | \
25 IA64_PSR_DT | IA64_PSR_RT | \
26 IA64_PSR_IT | IA64_PSR_BN)
28 #define DELIVER_PSR_CLR (IA64_PSR_AC | IA64_PSR_DFL| IA64_PSR_DFH| \
29 IA64_PSR_SP | IA64_PSR_DI | IA64_PSR_SI | \
30 IA64_PSR_DB | IA64_PSR_LP | IA64_PSR_TB | \
31 IA64_PSR_CPL| IA64_PSR_MC | IA64_PSR_IS | \
32 IA64_PSR_ID | IA64_PSR_DA | IA64_PSR_DD | \
33 IA64_PSR_SS | IA64_PSR_RI | IA64_PSR_ED | IA64_PSR_IA)
35 // NO PSR_CLR IS DIFFERENT! (CPL)
36 #define IA64_PSR_CPL1 (__IA64_UL(1) << IA64_PSR_CPL1_BIT)
37 #define IA64_PSR_CPL0 (__IA64_UL(1) << IA64_PSR_CPL0_BIT)
39 /* Interruption Function State */
40 #define IA64_IFS_V_BIT 63
41 #define IA64_IFS_V (__IA64_UL(1) << IA64_IFS_V_BIT)
43 /* Interruption Status Register. */
44 #define IA64_ISR_NI_BIT 39 /* Nested interrupt. */
46 /* Page Table Address */
47 #define IA64_PTA_VE_BIT 0
48 #define IA64_PTA_SIZE_BIT 2
49 #define IA64_PTA_SIZE_LEN 6
50 #define IA64_PTA_VF_BIT 8
51 #define IA64_PTA_BASE_BIT 15
53 #define IA64_PTA_VE (__IA64_UL(1) << IA64_PTA_VE_BIT)
54 #define IA64_PTA_SIZE (__IA64_UL((1 << IA64_PTA_SIZE_LEN) - 1) << \
55 IA64_PTA_SIZE_BIT)
56 #define IA64_PTA_VF (__IA64_UL(1) << IA64_PTA_VF_BIT)
57 #define IA64_PTA_BASE (__IA64_UL(0) - ((__IA64_UL(1) << IA64_PTA_BASE_BIT)))
59 /* Some cr.itir declarations. */
60 #define IA64_ITIR_PS 2
61 #define IA64_ITIR_PS_LEN 6
62 #define IA64_ITIR_PS_MASK (((__IA64_UL(1) << IA64_ITIR_PS_LEN) - 1) \
63 << IA64_ITIR_PS)
64 #define IA64_ITIR_KEY 8
65 #define IA64_ITIR_KEY_LEN 24
66 #define IA64_ITIR_KEY_MASK (((__IA64_UL(1) << IA64_ITIR_KEY_LEN) - 1) \
67 << IA64_ITIR_KEY)
68 #define IA64_ITIR_PS_KEY(_ps, _key) (((_ps) << IA64_ITIR_PS) | \
69 (((_key) << IA64_ITIR_KEY)))
71 /* Region Register Bits */
72 #define IA64_RR_PS 2
73 #define IA64_RR_PS_LEN 6
74 #define IA64_RR_RID 8
75 #define IA64_RR_RID_LEN 24
76 #define IA64_RR_RID_MASK (((__IA64_UL(1) << IA64_RR_RID_LEN) - 1) << \
77 IA64_RR_RID
79 /* Define Protection Key Register (PKR) */
80 #define IA64_PKR_V 0
81 #define IA64_PKR_WD 1
82 #define IA64_PKR_RD 2
83 #define IA64_PKR_XD 3
84 #define IA64_PKR_MBZ0 4
85 #define IA64_PKR_KEY 8
86 #define IA64_PKR_KEY_LEN 24
87 #define IA64_PKR_MBZ1 32
89 #define IA64_PKR_VALID (1 << IA64_PKR_V)
90 #define IA64_PKR_KEY_MASK (((__IA64_UL(1) << IA64_PKR_KEY_LEN) - 1) \
91 << IA64_PKR_KEY)
93 #define XEN_IA64_NPKRS 15 /* Number of pkr's in PV */
95 /* A pkr val for the hypervisor: key = 0, valid = 1. */
96 #define XEN_IA64_PKR_VAL ((0 << IA64_PKR_KEY) | IA64_PKR_VALID)
98 #endif /* _ASM_IA64_XENKREGS_H */