ia64/xen-unstable

view xen/arch/ia64/xen/relocate_kernel.S @ 16785:af3550f53874

[IA64] domheap: Don't pin xenheap down. Now it's unnecessary.

Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
author Alex Williamson <alex.williamson@hp.com>
date Thu Jan 17 12:05:43 2008 -0700 (2008-01-17)
parents 4108c2589fd1
children 0b20ac6ec64a
line source
1 /*
2 * arch/ia64/kernel/relocate_kernel.S
3 *
4 * Relocate kexec'able kernel and start it
5 *
6 * Copyright (C) 2005 Hewlett-Packard Development Company, L.P.
7 * Copyright (C) 2005 Khalid Aziz <khalid.aziz@hp.com>
8 * Copyright (C) 2005 Intel Corp, Zou Nan hai <nanhai.zou@intel.com>
9 *
10 * This source code is licensed under the GNU General Public License,
11 * Version 2. See the file COPYING for more details.
12 */
13 #include <asm/asmmacro.h>
14 #include <asm/kregs.h>
15 #include <asm/page.h>
16 #include <asm/pgtable.h>
17 #include <asm/mca_asm.h>
19 GLOBAL_ENTRY(ia64_dump_cpu_regs)
20 .prologue
21 alloc loc0=ar.pfs,1,2,0,0
22 .body
23 mov ar.rsc=0 // put RSE in enforced lazy mode
24 add loc1=4*8, in0 // save r4 and r5 first
25 ;;
26 {
27 flushrs // flush dirty regs to backing store
28 srlz.i
29 }
30 st8 [loc1]=r4, 8
31 ;;
32 st8 [loc1]=r5, 8
33 ;;
34 add loc1=32*8, in0
35 mov r4=ar.rnat
36 ;;
37 st8 [in0]=r0, 8 // r0
38 st8 [loc1]=r4, 8 // rnat
39 mov r5=pr
40 ;;
41 st8 [in0]=r1, 8 // r1
42 st8 [loc1]=r5, 8 // pr
43 mov r4=b0
44 ;;
45 st8 [in0]=r2, 8 // r2
46 st8 [loc1]=r4, 8 // b0
47 mov r5=b1;
48 ;;
49 st8 [in0]=r3, 24 // r3
50 st8 [loc1]=r5, 8 // b1
51 mov r4=b2
52 ;;
53 st8 [in0]=r6, 8 // r6
54 st8 [loc1]=r4, 8 // b2
55 mov r5=b3
56 ;;
57 st8 [in0]=r7, 8 // r7
58 st8 [loc1]=r5, 8 // b3
59 mov r4=b4
60 ;;
61 st8 [in0]=r8, 8 // r8
62 st8 [loc1]=r4, 8 // b4
63 mov r5=b5
64 ;;
65 st8 [in0]=r9, 8 // r9
66 st8 [loc1]=r5, 8 // b5
67 mov r4=b6
68 ;;
69 st8 [in0]=r10, 8 // r10
70 st8 [loc1]=r5, 8 // b6
71 mov r5=b7
72 ;;
73 st8 [in0]=r11, 8 // r11
74 st8 [loc1]=r5, 8 // b7
75 mov r4=b0
76 ;;
77 st8 [in0]=r12, 8 // r12
78 st8 [loc1]=r4, 8 // ip
79 mov r5=loc0
80 ;;
81 st8 [in0]=r13, 8 // r13
82 extr.u r5=r5, 0, 38 // ar.pfs.pfm
83 mov r4=r0 // user mask
84 ;;
85 st8 [in0]=r14, 8 // r14
86 st8 [loc1]=r5, 8 // cfm
87 ;;
88 st8 [in0]=r15, 8 // r15
89 st8 [loc1]=r4, 8 // user mask
90 mov r5=ar.rsc
91 ;;
92 st8 [in0]=r16, 8 // r16
93 st8 [loc1]=r5, 8 // ar.rsc
94 mov r4=ar.bsp
95 ;;
96 st8 [in0]=r17, 8 // r17
97 st8 [loc1]=r4, 8 // ar.bsp
98 mov r5=ar.bspstore
99 ;;
100 st8 [in0]=r18, 8 // r18
101 st8 [loc1]=r5, 8 // ar.bspstore
102 mov r4=ar.rnat
103 ;;
104 st8 [in0]=r19, 8 // r19
105 st8 [loc1]=r4, 8 // ar.rnat
106 mov r5=ar.ccv
107 ;;
108 st8 [in0]=r20, 8 // r20
109 st8 [loc1]=r5, 8 // ar.ccv
110 mov r4=ar.unat
111 ;;
112 st8 [in0]=r21, 8 // r21
113 st8 [loc1]=r4, 8 // ar.unat
114 mov r5 = ar.fpsr
115 ;;
116 st8 [in0]=r22, 8 // r22
117 st8 [loc1]=r5, 8 // ar.fpsr
118 mov r4 = ar.unat
119 ;;
120 st8 [in0]=r23, 8 // r23
121 st8 [loc1]=r4, 8 // unat
122 mov r5 = ar.fpsr
123 ;;
124 st8 [in0]=r24, 8 // r24
125 st8 [loc1]=r5, 8 // fpsr
126 mov r4 = ar.pfs
127 ;;
128 st8 [in0]=r25, 8 // r25
129 st8 [loc1]=r4, 8 // ar.pfs
130 mov r5 = ar.lc
131 ;;
132 st8 [in0]=r26, 8 // r26
133 st8 [loc1]=r5, 8 // ar.lc
134 mov r4 = ar.ec
135 ;;
136 st8 [in0]=r27, 8 // r27
137 st8 [loc1]=r4, 8 // ar.ec
138 mov r5 = ar.csd
139 ;;
140 st8 [in0]=r28, 8 // r28
141 st8 [loc1]=r5, 8 // ar.csd
142 mov r4 = ar.ssd
143 ;;
144 st8 [in0]=r29, 8 // r29
145 st8 [loc1]=r4, 8 // ar.ssd
146 ;;
147 st8 [in0]=r30, 8 // r30
148 ;;
149 st8 [in0]=r31, 8 // r31
150 mov ar.pfs=loc0
151 ;;
152 br.ret.sptk.many rp
153 END(ia64_dump_cpu_regs)