ia64/xen-unstable

view xen/arch/ia64/xen/ivt.S @ 16785:af3550f53874

[IA64] domheap: Don't pin xenheap down. Now it's unnecessary.

Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
author Alex Williamson <alex.williamson@hp.com>
date Thu Jan 17 12:05:43 2008 -0700 (2008-01-17)
parents 6a7fa7dbde56
children 91332bc4abd4
line source
1 #include <asm/debugger.h>
2 #include <asm/vhpt.h>
3 #include <public/arch-ia64.h>
4 #include <asm/config.h>
5 /*
6 * arch/ia64/kernel/ivt.S
7 *
8 * Copyright (C) 1998-2001, 2003 Hewlett-Packard Co
9 * Stephane Eranian <eranian@hpl.hp.com>
10 * David Mosberger <davidm@hpl.hp.com>
11 * Copyright (C) 2000, 2002-2003 Intel Co
12 * Asit Mallick <asit.k.mallick@intel.com>
13 * Suresh Siddha <suresh.b.siddha@intel.com>
14 * Kenneth Chen <kenneth.w.chen@intel.com>
15 * Fenghua Yu <fenghua.yu@intel.com>
16 *
17 * 00/08/23 Asit Mallick <asit.k.mallick@intel.com> TLB handling for SMP
18 * 00/12/20 David Mosberger-Tang <davidm@hpl.hp.com> DTLB/ITLB handler now
19 * uses virtual PT.
20 */
21 /*
22 * This file defines the interruption vector table used by the CPU.
23 * It does not include one entry per possible cause of interruption.
24 *
25 * The first 20 entries of the table contain 64 bundles each while the
26 * remaining 48 entries contain only 16 bundles each.
27 *
28 * The 64 bundles are used to allow inlining the whole handler for critical
29 * interruptions like TLB misses.
30 *
31 * For each entry, the comment is as follows:
32 *
33 * // 0x1c00 Entry 7 (size 64 bundles) Data Key Miss (12,51)
34 * entry offset ----/ / / / /
35 * entry number ---------/ / / /
36 * size of the entry -------------/ / /
37 * vector name -------------------------------------/ /
38 * interruptions triggering this vector ----------------------/
39 *
40 * The table is 32KB in size and must be aligned on 32KB boundary.
41 * (The CPU ignores the 15 lower bits of the address)
42 *
43 * Table is based upon EAS2.6 (Oct 1999)
44 */
46 #include <linux/config.h>
48 #include <asm/asmmacro.h>
49 #include <asm/break.h>
50 #include <asm/ia32.h>
51 #include <asm/kregs.h>
52 #include <asm/offsets.h>
53 #include <asm/pgtable.h>
54 #include <asm/processor.h>
55 #include <asm/ptrace.h>
56 #include <asm/system.h>
57 #include <asm/thread_info.h>
58 #include <asm/unistd.h>
59 #include <xen/errno.h>
61 #if 1
62 # define PSR_DEFAULT_BITS psr.ac
63 #else
64 # define PSR_DEFAULT_BITS 0
65 #endif
67 #if 0
68 /*
69 * This lets you track the last eight faults that occurred on the CPU.
70 * Make sure ar.k2 isn't needed for something else before enabling this...
71 */
72 # define DBG_FAULT(i) \
73 mov r16=ar.k2;; \
74 shl r16=r16,8;; \
75 add r16=(i),r16;; \
76 mov ar.k2=r16
77 #else
78 # define DBG_FAULT(i)
79 #endif
81 #define MINSTATE_VIRT /* needed by minstate.h */
82 #include "minstate.h"
84 #define FAULT(n) \
85 mov r19=n; /* prepare to save predicates */ \
86 mov r31=pr; \
87 br.sptk.many dispatch_to_fault_handler
89 #define FAULT_OR_REFLECT(n) \
90 mov r20=cr.ipsr; \
91 mov r19=n; /* prepare to save predicates */ \
92 mov r31=pr;; \
93 extr.u r20=r20,IA64_PSR_CPL0_BIT,2;; \
94 cmp.ne p6,p0=r0,r20; /* cpl != 0?*/ \
95 (p6) br.dptk.many dispatch_reflection; \
96 br.sptk.few dispatch_to_fault_handler
98 .section .text.ivt,"ax"
100 .align 32768 // align on 32KB boundary
101 .global ia64_ivt
102 ia64_ivt:
103 //////////////////////////////////////////////////////////////////////////
104 // 0x0000 Entry 0 (size 64 bundles) VHPT Translation (8,20,47)
105 ENTRY(vhpt_miss)
106 DBG_FAULT(0)
107 FAULT(0)
108 END(vhpt_miss)
110 .org ia64_ivt+0x400
111 //////////////////////////////////////////////////////////////////////////
112 // 0x0400 Entry 1 (size 64 bundles) ITLB (21)
113 ENTRY(itlb_miss)
114 DBG_FAULT(1)
115 mov r16 = cr.ifa
116 mov r31 = pr
117 ;;
118 extr.u r17=r16,59,5
119 ;;
120 /* If address belongs to VMM, go to alt tlb handler */
121 cmp.eq p6,p0=0x1e,r17
122 (p6) br.cond.spnt late_alt_itlb_miss
123 br.cond.sptk fast_tlb_miss_reflect
124 ;;
125 END(itlb_miss)
127 .org ia64_ivt+0x0800
128 //////////////////////////////////////////////////////////////////////////
129 // 0x0800 Entry 2 (size 64 bundles) DTLB (9,48)
130 ENTRY(dtlb_miss)
131 DBG_FAULT(2)
132 mov r16=cr.ifa // get virtual address
133 mov r31=pr
134 ;;
135 extr.u r17=r16,59,5
136 ;;
137 /* If address belongs to VMM, go to alt tlb handler */
138 cmp.eq p6,p0=0x1e,r17
139 (p6) br.cond.spnt late_alt_dtlb_miss
140 br.cond.sptk fast_tlb_miss_reflect
141 ;;
142 END(dtlb_miss)
144 .org ia64_ivt+0x0c00
145 //////////////////////////////////////////////////////////////////////////
146 // 0x0c00 Entry 3 (size 64 bundles) Alt ITLB (19)
147 ENTRY(alt_itlb_miss)
148 DBG_FAULT(3)
149 mov r16=cr.ifa // get address that caused the TLB miss
150 mov r31=pr
151 ;;
152 late_alt_itlb_miss:
153 mov r21=cr.ipsr
154 movl r17=PAGE_KERNEL
155 movl r19=(((1 << IA64_MAX_PHYS_BITS) - 1) & ~0xfff)
156 ;;
157 mov r20=cr.itir
158 extr.u r23=r21,IA64_PSR_CPL0_BIT,2 // extract psr.cpl
159 and r19=r19,r16 // clear ed, reserved bits, and PTE ctrl bits
160 extr.u r18=r16,XEN_VIRT_UC_BIT,1 // extract UC bit
161 ;;
162 cmp.ne p8,p0=r0,r23 // psr.cpl != 0?
163 or r19=r17,r19 // insert PTE control bits into r19
164 dep r20=0,r20,IA64_ITIR_KEY,IA64_ITIR_KEY_LEN // clear the key
165 ;;
166 dep r19=r18,r19,4,1 // set bit 4 (uncached) if access to UC area.
167 mov cr.itir=r20 // set itir with cleared key
168 (p8) br.cond.spnt page_fault
169 ;;
170 itc.i r19 // insert the TLB entry
171 mov pr=r31,-1
172 rfi
173 END(alt_itlb_miss)
175 .org ia64_ivt+0x1000
176 //////////////////////////////////////////////////////////////////////////
177 // 0x1000 Entry 4 (size 64 bundles) Alt DTLB (7,46)
178 ENTRY(alt_dtlb_miss)
179 DBG_FAULT(4)
180 mov r16=cr.ifa // get address that caused the TLB miss
181 mov r31=pr
182 ;;
183 late_alt_dtlb_miss:
184 mov r20=cr.isr
185 movl r17=PAGE_KERNEL
186 mov r21=cr.ipsr
187 movl r19=(((1 << IA64_MAX_PHYS_BITS) - 1) & ~0xfff)
188 ;;
189 extr.u r23=r21,IA64_PSR_CPL0_BIT,2 // extract psr.cpl
190 and r22=IA64_ISR_CODE_MASK,r20 // get the isr.code field
191 tbit.nz p6,p7=r20,IA64_ISR_SP_BIT // is speculation bit on?
192 extr.u r18=r16,XEN_VIRT_UC_BIT,1 // extract UC bit
193 and r19=r19,r16 // clear ed, reserved bits, and
194 // PTE control bits
195 tbit.nz p9,p0=r20,IA64_ISR_NA_BIT // is non-access bit on?
196 ;;
197 cmp.ne p8,p0=r0,r23
198 (p9) cmp.eq.or.andcm p6,p7=IA64_ISR_CODE_LFETCH,r22 // check isr.code field
199 (p8) br.cond.spnt page_fault
200 ;;
201 mov r20=cr.itir
202 #ifdef CONFIG_VIRTUAL_FRAME_TABLE
203 shr r22=r16,56 // Test for the address of virtual frame_table
204 ;;
205 cmp.eq p8,p0=((VIRT_FRAME_TABLE_ADDR>>56)&0xff)-0x100,r22
206 (p8) br.cond.sptk frametable_miss ;;
207 #endif
208 // If it is not a Xen address, handle it via page_fault.
209 extr.u r22=r16,59,5
210 ;;
211 dep r20=0,r20,IA64_ITIR_KEY,IA64_ITIR_KEY_LEN // clear the key
212 cmp.ne p8,p0=0x1e,r22
213 (p8) br.cond.sptk page_fault
214 ;;
215 dep r21=-1,r21,IA64_PSR_ED_BIT,1
216 or r19=r19,r17 // insert PTE control bits into r19
217 mov cr.itir=r20 // set itir with cleared key
218 ;;
219 dep r19=r18,r19,4,1 // set bit 4 (uncached) if access to UC area
220 (p6) mov cr.ipsr=r21
221 ;;
222 (p7) itc.d r19 // insert the TLB entry
223 mov pr=r31,-1
224 rfi
225 END(alt_dtlb_miss)
227 #ifdef CONFIG_VIRTUAL_FRAME_TABLE
228 GLOBAL_ENTRY(frametable_miss)
229 rsm psr.dt // switch to using physical data addressing
230 movl r24=(frametable_pg_dir-PAGE_OFFSET) // r24=__pa(frametable_pg_dir)
231 ;;
232 srlz.d
233 extr.u r17=r16,PGDIR_SHIFT,(PAGE_SHIFT-3)
234 ;;
235 shladd r24=r17,3,r24 // r24=&pgd[pgd_offset(addr)]
236 ;;
237 ld8 r24=[r24] // r24=pgd[pgd_offset(addr)]
238 extr.u r18=r16,PMD_SHIFT,(PAGE_SHIFT-3) // r18=pmd_offset
239 ;;
240 cmp.eq p6,p7=0,r24 // pgd present?
241 shladd r24=r18,3,r24 // r24=&pmd[pmd_offset(addr)]
242 ;;
243 (p7) ld8 r24=[r24] // r24=pmd[pmd_offset(addr)]
244 extr.u r19=r16,PAGE_SHIFT,(PAGE_SHIFT-3)// r19=pte_offset
245 (p6) br.spnt.few frametable_fault
246 ;;
247 cmp.eq p6,p7=0,r24 // pmd present?
248 shladd r24=r19,3,r24 // r24=&pte[pte_offset(addr)]
249 ;;
250 (p7) ld8 r24=[r24] // r24=pte[pte_offset(addr)]
251 mov r25=(PAGE_SHIFT<<IA64_ITIR_PS)
252 (p6) br.spnt.few frametable_fault
253 ;;
254 mov cr.itir=r25
255 ssm psr.dt // switch to using virtual data addressing
256 tbit.z p6,p7=r24,_PAGE_P_BIT // pte present?
257 ;;
258 (p7) itc.d r24 // install updated PTE
259 (p6) br.spnt.few frametable_fault // page present bit cleared?
260 ;;
261 mov pr=r31,-1 // restore predicate registers
262 rfi
263 END(frametable_miss)
265 ENTRY(frametable_fault)
266 ssm psr.dt // switch to using virtual data addressing
267 mov r18=cr.iip
268 movl r19=ia64_frametable_probe
269 ;;
270 cmp.eq p6,p7=r18,r19 // is faulting addrress ia64_frametable_probe?
271 mov r8=0 // assumes that 'probe.r' uses r8
272 dep r21=-1,r21,IA64_PSR_RI_BIT+1,1 // return to next instruction in
273 // bundle 2
274 ;;
275 (p6) mov cr.ipsr=r21
276 mov r19=4 // FAULT(4)
277 (p7) br.spnt.few dispatch_to_fault_handler
278 ;;
279 mov pr=r31,-1
280 rfi
281 END(frametable_fault)
283 GLOBAL_ENTRY(ia64_frametable_probe)
284 {
285 probe.r r8=r32,0 // destination register must be r8
286 nop.f 0x0
287 br.ret.sptk.many b0 // this instruction must be in bundle 2
288 }
289 END(ia64_frametable_probe)
290 #endif /* CONFIG_VIRTUAL_FRAME_TABLE */
292 .org ia64_ivt+0x1400
293 /////////////////////////////////////////////////////////////////////////////////////////
294 // 0x1400 Entry 5 (size 64 bundles) Data nested TLB (6,45)
295 ENTRY(nested_dtlb_miss)
296 DBG_FAULT(5)
297 mov b0=r30
298 br.sptk.many b0 // return to the continuation point
299 ;;
300 END(nested_dtlb_miss)
302 GLOBAL_ENTRY(dispatch_reflection)
303 /*
304 * Input:
305 * psr.ic: off
306 * r19: intr type (offset into ivt, see ia64_int.h)
307 * r31: contains saved predicates (pr)
308 */
309 SAVE_MIN_WITH_COVER_R19
310 alloc r14=ar.pfs,0,0,5,0
311 mov out4=r15
312 mov out0=cr.ifa
313 adds out1=16,sp
314 mov out2=cr.isr
315 mov out3=cr.iim
317 ssm psr.ic | PSR_DEFAULT_BITS
318 ;;
319 srlz.i // guarantee that interruption
320 // collection is on
321 ;;
322 (p15) ssm psr.i // restore psr.i
323 adds r3=8,r2 // set up second base pointer
324 ;;
325 SAVE_REST
326 movl r14=ia64_leave_kernel
327 ;;
328 mov rp=r14
329 // br.sptk.many ia64_prepare_handle_reflection // TODO: why commented out?
330 br.call.sptk.many b6=ia64_handle_reflection
331 END(dispatch_reflection)
333 .org ia64_ivt+0x1800
334 //////////////////////////////////////////////////////////////////////////
335 // 0x1800 Entry 6 (size 64 bundles) Instruction Key Miss (24)
336 ENTRY(ikey_miss)
337 DBG_FAULT(6)
338 FAULT_OR_REFLECT(6)
339 END(ikey_miss)
341 //----------------------------------------------------------------
342 // call do_page_fault (predicates are in r31, psr.dt may be off,
343 // r16 is faulting address)
344 GLOBAL_ENTRY(page_fault)
345 ssm psr.dt
346 ;;
347 srlz.i
348 ;;
349 SAVE_MIN_WITH_COVER
350 alloc r15=ar.pfs,0,0,4,0
351 mov out0=cr.ifa
352 mov out1=cr.isr
353 mov out3=cr.itir
354 adds r3=8,r2 // set up second base pointer
355 ;;
356 ssm psr.ic | PSR_DEFAULT_BITS
357 ;;
358 srlz.i // guarantee that interruption
359 // collection is on
360 ;;
361 (p15) ssm psr.i // restore psr.i
362 movl r14=ia64_leave_kernel
363 ;;
364 SAVE_REST
365 mov rp=r14
366 ;;
367 adds out2=16,r12 // out2 = pointer to pt_regs
368 br.call.sptk.many b6=ia64_do_page_fault // ignore return address
369 END(page_fault)
371 .org ia64_ivt+0x1c00
372 //////////////////////////////////////////////////////////////////////////
373 // 0x1c00 Entry 7 (size 64 bundles) Data Key Miss (12,51)
374 ENTRY(dkey_miss)
375 DBG_FAULT(7)
376 FAULT_OR_REFLECT(7)
377 END(dkey_miss)
379 .org ia64_ivt+0x2000
380 //////////////////////////////////////////////////////////////////////////
381 // 0x2000 Entry 8 (size 64 bundles) Dirty-bit (54)
382 ENTRY(dirty_bit)
383 DBG_FAULT(8)
384 mov r20=cr.ipsr
385 mov r31=pr
386 ;;
387 extr.u r20=r20,IA64_PSR_CPL0_BIT,2
388 ;;
389 mov r19=8 // prepare to save predicates
390 cmp.eq p6,p0=r0,r20 // cpl == 0?
391 (p6) br.sptk.few dispatch_to_fault_handler
392 // If shadow mode is not enabled, reflect the fault.
393 movl r22=THIS_CPU(cpu_kr)+IA64_KR_CURRENT_OFFSET
394 ;;
395 ld8 r22=[r22]
396 ;;
397 add r22=IA64_VCPU_SHADOW_BITMAP_OFFSET,r22
398 ;;
399 ld8 r22=[r22]
400 ;;
401 cmp.eq p6,p0=r0,r22 // !shadow_bitmap ?
402 (p6) br.dptk.many dispatch_reflection
404 SAVE_MIN_WITH_COVER
405 alloc r14=ar.pfs,0,0,4,0
406 mov out0=cr.ifa
407 mov out1=cr.itir
408 mov out2=cr.isr
409 adds out3=16,sp
411 ssm psr.ic | PSR_DEFAULT_BITS
412 ;;
413 srlz.i // guarantee that interruption
414 // collection is on
415 ;;
416 (p15) ssm psr.i // restore psr.i
417 adds r3=8,r2 // set up second base pointer
418 ;;
419 SAVE_REST
420 movl r14=ia64_leave_kernel
421 ;;
422 mov rp=r14
423 br.call.sptk.many b6=ia64_shadow_fault
424 END(dirty_bit)
426 .org ia64_ivt+0x2400
427 //////////////////////////////////////////////////////////////////////////
428 // 0x2400 Entry 9 (size 64 bundles) Instruction Access-bit (27)
429 ENTRY(iaccess_bit)
430 DBG_FAULT(9)
431 mov r16=cr.isr
432 mov r17=cr.ifa
433 mov r31=pr
434 mov r19=9
435 mov r20=0x2400
436 br.sptk.many fast_access_reflect;;
437 END(iaccess_bit)
439 .org ia64_ivt+0x2800
440 //////////////////////////////////////////////////////////////////////////
441 // 0x2800 Entry 10 (size 64 bundles) Data Access-bit (15,55)
442 ENTRY(daccess_bit)
443 DBG_FAULT(10)
444 mov r16=cr.isr
445 mov r17=cr.ifa
446 mov r31=pr
447 mov r19=10
448 mov r20=0x2800
449 br.sptk.many fast_access_reflect
450 ;;
451 END(daccess_bit)
453 .org ia64_ivt+0x2c00
454 //////////////////////////////////////////////////////////////////////////
455 // 0x2c00 Entry 11 (size 64 bundles) Break instruction (33)
456 ENTRY(break_fault)
457 .body
458 /*
459 * The streamlined system call entry/exit paths only save/restore
460 * the initial part of pt_regs. This implies that the callers of
461 * system-calls must adhere to the normal procedure calling
462 * conventions.
463 *
464 * Registers to be saved & restored:
465 * CR registers: cr.ipsr, cr.iip, cr.ifs
466 * AR registers: ar.unat, ar.pfs, ar.rsc, ar.rnat, ar.bspstore,
467 * ar.fpsr
468 * others: pr, b0, b6, loadrs, r1, r11, r12, r13, r15
469 * Registers to be restored only:
470 * r8-r11: output value from the system call.
471 *
472 * During system call exit, scratch registers (including r15) are
473 * modified/cleared to prevent leaking bits from kernel to user
474 * level.
475 */
476 DBG_FAULT(11)
477 mov r16=cr.isr
478 mov r17=cr.iim
479 mov r31=pr
480 ;;
481 cmp.eq p7,p0=r17,r0
482 (p7) br.spnt.few dispatch_break_fault
483 ;;
484 #ifdef CRASH_DEBUG
485 // A panic can occur before domain0 is created. In such cases,
486 // referencing XSI_PSR_IC causes nested_dtlb_miss.
487 movl r18=CDB_BREAK_NUM
488 ;;
489 cmp.eq p7,p0=r17,r18
490 ;;
491 (p7) br.spnt.few dispatch_break_fault
492 ;;
493 #endif
494 movl r18=THIS_CPU(current_psr_ic_addr)
495 ;;
496 ld8 r18=[r18]
497 ;;
498 #ifdef CONFIG_PRIVIFY
499 // pseudo-cover are replaced by break.b which (unfortunatly) always
500 // clear iim.
501 cmp.eq p7,p0=r0,r17
502 (p7) br.spnt.many dispatch_privop_fault
503 ;;
504 #endif
505 // if (ipsr.cpl == CONFIG_CPL0_EMUL &&
506 // (iim - HYPERPRIVOP_START) < HYPERPRIVOP_MAX)
507 // this is a hyperprivop. A hyperprivop is hand-coded assembly with
508 // psr.ic off which means it can make no calls, cannot use r1-r15,
509 // and it can have no memory accesses unless they are to pinned
510 // addresses!
511 mov r19= cr.ipsr
512 mov r20=HYPERPRIVOP_START
513 mov r21=HYPERPRIVOP_MAX
514 ;;
515 sub r20=r17,r20
516 extr.u r19=r19,IA64_PSR_CPL0_BIT,2 // extract cpl field from cr.ipsr
517 ;;
518 cmp.gtu p7,p0=r21,r20
519 ;;
520 cmp.eq.and p7,p0=CONFIG_CPL0_EMUL,r19 // ipsr.cpl==CONFIG_CPL0_EMUL
521 (p7) br.sptk.many fast_hyperprivop
522 ;;
523 movl r22=THIS_CPU(cpu_kr)+IA64_KR_CURRENT_OFFSET
524 ;;
525 ld8 r22 = [r22]
526 ;;
527 adds r23=IA64_VCPU_BREAKIMM_OFFSET,r22
528 ;;
529 ld4 r23=[r23];;
530 cmp4.eq p6,p0=r23,r17;; // Xen-reserved breakimm?
531 cmp.eq.and p6,p0=CONFIG_CPL0_EMUL,r19
532 (p6) br.spnt.many fast_hypercall
533 ;;
534 br.sptk.many fast_break_reflect
535 ;;
538 fast_hypercall:
539 shr r25=r2,8;;
540 cmp.ne p7,p0=r0,r25
541 (p7) br.spnt.few dispatch_break_fault
542 ;;
543 // fall through
546 /*
547 * The streamlined system call entry/exit paths only save/restore the initial part
548 * of pt_regs. This implies that the callers of system-calls must adhere to the
549 * normal procedure calling conventions.
550 *
551 * Registers to be saved & restored:
552 * CR registers: cr.ipsr, cr.iip, cr.ifs
553 * AR registers: ar.unat, ar.pfs, ar.rsc, ar.rnat, ar.bspstore, ar.fpsr
554 * others: pr, b0, b6, loadrs, r1, r11, r12, r13, r15
555 * Registers to be restored only:
556 * r8-r11: output value from the system call.
557 *
558 * During system call exit, scratch registers (including r15) are modified/cleared
559 * to prevent leaking bits from kernel to user level.
560 */
562 // DBG_FAULT(11)
563 // mov.m r16=IA64_KR(CURRENT) // M2 r16 <- current task (12 cyc)
564 mov r16=r22
565 mov r29=cr.ipsr // M2 (12 cyc)
566 // mov r31=pr // I0 (2 cyc)
567 mov r15=r2
569 // mov r17=cr.iim // M2 (2 cyc)
570 mov.m r27=ar.rsc // M2 (12 cyc)
571 // mov r18=__IA64_BREAK_SYSCALL // A
573 mov.m ar.rsc=0 // M2
574 mov.m r21=ar.fpsr // M2 (12 cyc)
575 mov r19=b6 // I0 (2 cyc)
576 ;;
577 mov.m r23=ar.bspstore // M2 (12 cyc)
578 mov.m r24=ar.rnat // M2 (5 cyc)
579 mov.i r26=ar.pfs // I0 (2 cyc)
581 invala // M0|1
582 nop.m 0 // M
583 mov r20=r1 // A save r1
585 nop.m 0
586 // movl r30=sys_call_table // X
587 movl r30=ia64_hypercall_table // X
589 mov r28=cr.iip // M2 (2 cyc)
590 // cmp.eq p0,p7=r18,r17 // I0 is this a system call?
591 //(p7) br.cond.spnt non_syscall // B no ->
592 //
593 // From this point on, we are definitely on the syscall-path
594 // and we can use (non-banked) scratch registers.
595 //
596 ///////////////////////////////////////////////////////////////////////
597 mov r1=r16 // A move task-pointer to "addl"-addressable reg
598 mov r2=r16 // A setup r2 for ia64_syscall_setup
599 // add r9=TI_FLAGS+IA64_TASK_SIZE,r16 // A r9 = &current_thread_info()->flags
601 adds r16=IA64_TASK_THREAD_ON_USTACK_OFFSET,r16
602 // adds r15=-1024,r15 // A subtract 1024 from syscall number
603 // mov r3=NR_syscalls - 1
604 mov r3=NR_hypercalls - 1
605 ;;
606 ld1.bias r17=[r16] // M0|1 r17 = current->thread.on_ustack flag
607 // ld4 r9=[r9] // M0|1 r9 = current_thread_info()->flags
608 mov r9=r0 // force flags = 0
609 extr.u r8=r29,41,2 // I0 extract ei field from cr.ipsr
611 shladd r30=r15,3,r30 // A r30 = sys_call_table + 8*(syscall-1024)
612 addl r22=IA64_RBS_OFFSET,r1 // A compute base of RBS
613 cmp.leu p6,p7=r15,r3 // A syscall number in range?
614 ;;
616 lfetch.fault.excl.nt1 [r22] // M0|1 prefetch RBS
617 (p6) ld8 r30=[r30] // M0|1 load address of syscall entry point
618 tnat.nz.or p7,p0=r15 // I0 is syscall nr a NaT?
620 mov.m ar.bspstore=r22 // M2 switch to kernel RBS
621 cmp.eq p8,p9=2,r8 // A isr.ei==2?
622 ;;
624 (p8) mov r8=0 // A clear ei to 0
625 //(p7) movl r30=sys_ni_syscall // X
626 (p7) movl r30=do_ni_hypercall // X
628 (p8) adds r28=16,r28 // A switch cr.iip to next bundle
629 (p9) adds r8=1,r8 // A increment ei to next slot
630 nop.i 0
631 ;;
633 mov.m r25=ar.unat // M2 (5 cyc)
634 dep r29=r8,r29,41,2 // I0 insert new ei into cr.ipsr
635 // adds r15=1024,r15 // A restore original syscall number
636 //
637 // If any of the above loads miss in L1D, we'll stall here until
638 // the data arrives.
639 //
640 ///////////////////////////////////////////////////////////////////////
641 st1 [r16]=r0 // M2|3 clear current->thread.on_ustack flag
642 mov b6=r30 // I0 setup syscall handler branch reg early
643 cmp.eq pKStk,pUStk=r0,r17 // A were we on kernel stacks already?
645 // and r9=_TIF_SYSCALL_TRACEAUDIT,r9 // A mask trace or audit
646 mov r18=ar.bsp // M2 (12 cyc)
647 ;;
648 (pUStk) addl r1=IA64_STK_OFFSET-IA64_PT_REGS_SIZE,r1 // A compute base of memory stack
649 // cmp.eq p14,p0=r9,r0 // A are syscalls being traced/audited?
650 br.call.sptk.many b7=ia64_syscall_setup // B
651 1:
652 mov ar.rsc=0x3 // M2 set eager mode, pl 0, LE, loadrs=0
653 nop 0
654 bsw.1 // B (6 cyc) regs are saved, switch to bank 1
655 ;;
657 PT_REGS_UNWIND_INFO(0)
658 ssm psr.ic | PSR_DEFAULT_BITS // M2 now it's safe to re-enable intr.-collection
659 // movl r3=ia64_ret_from_syscall // X
660 ;;
662 srlz.i // M0 ensure interruption collection is on
663 // mov rp=r3 // I0 set the real return addr
664 //(p10) br.cond.spnt.many ia64_ret_from_syscall // B return if bad call-frame or r15 is a NaT
665 (p15) ssm psr.i // M2 restore psr.i
666 //(p14) br.call.sptk.many b6=b6 // B invoke syscall-handker (ignore return addr)
667 // br.call.sptk.many b6=b6 // B invoke syscall-handker (ignore return addr)
668 br.call.sptk.many b0=b6 // B invoke syscall-handker (ignore return addr)
669 // br.cond.spnt.many ia64_trace_syscall // B do syscall-tracing thingamagic
670 ;;
671 adds r2=PT(R8)+16,r12
672 ;;
673 st8 [r2]=r8
674 ;;
675 br.call.sptk.many b0=do_softirq
676 ;;
677 //restore hypercall argument if continuation
678 adds r2=IA64_VCPU_HYPERCALL_CONTINUATION_OFS,r13
679 ;;
680 ld1 r20=[r2]
681 ;;
682 st1 [r2]=r0
683 ;;
684 cmp.ne p6,p0=r20,r0
685 ;;
686 (p6) adds r2=PT(R16)+16,r12
687 (p6) adds r3=PT(R17)+16,r12
688 ;;
689 (p6) ld8 r32=[r2],16
690 (p6) ld8 r33=[r3],16
691 ;;
692 (p6) ld8 r34=[r2],16
693 (p6) ld8 r35=[r3],16
694 ;;
695 (p6) ld8 r36=[r2],16
696 ;;
697 //save ar.bsp before cover
698 mov r16=ar.bsp
699 add r2=PT(R14)+16,r12
700 ;;
701 st8 [r2]=r16
702 ;;
703 rsm psr.i|psr.ic
704 ;;
705 srlz.i
706 ;;
707 cover
708 ;;
709 mov r20=cr.ifs
710 adds r2=PT(CR_IFS)+16,r12
711 ;;
712 st8 [r2]=r20
713 ssm psr.ic | PSR_DEFAULT_BITS
714 ;;
715 srlz.i
716 ;;
717 br.call.sptk.many b0=reflect_event
718 ;;
719 rsm psr.i|psr.ic
720 adds r2=PT(R14)+16,r12
721 adds r3=PT(R8)+16,r12
722 ;;
723 //r16 contains ar.bsp before cover
724 ld8 r16=[r2]
725 ld8 r8=[r3]
726 srlz.i
727 ;;
728 br.sptk.many ia64_ret_from_syscall
729 ;;
730 END(break_fault)
732 .org ia64_ivt+0x3000
733 //////////////////////////////////////////////////////////////////////////
734 // 0x3000 Entry 12 (size 64 bundles) External Interrupt (4)
735 ENTRY(interrupt)
736 DBG_FAULT(12)
737 mov r31=pr // prepare to save predicates
738 mov r30=cr.ivr // pass cr.ivr as first arg
739 // FIXME: this is a hack... use cpuinfo.ksoftirqd because its
740 // not used anywhere else and we need a place to stash ivr and
741 // there's no registers available unused by SAVE_MIN/REST
742 movl r29=THIS_CPU(cpu_info)+IA64_CPUINFO_KSOFTIRQD_OFFSET
743 ;;
744 st8 [r29]=r30
745 movl r28=slow_interrupt
746 ;;
747 mov r29=rp
748 ;;
749 mov rp=r28
750 ;;
751 br.cond.sptk.many fast_tick_reflect
752 ;;
753 slow_interrupt:
754 mov rp=r29;;
755 SAVE_MIN_WITH_COVER // uses r31; defines r2 and r3
756 ssm psr.ic | PSR_DEFAULT_BITS
757 ;;
758 adds r3=8,r2 // set up second base pointer for SAVE_REST
759 srlz.i // ensure everybody knows psr.ic is back on
760 ;;
761 SAVE_REST
762 ;;
763 alloc r14=ar.pfs,0,0,2,0 // must be first in an insn group
764 movl out0=THIS_CPU(cpu_info)+IA64_CPUINFO_KSOFTIRQD_OFFSET;;
765 ld8 out0=[out0];;
766 add out1=16,sp // pass pointer to pt_regs as second arg
767 movl r14=ia64_leave_kernel
768 ;;
769 mov rp=r14
770 br.call.sptk.many b6=ia64_handle_irq
771 END(interrupt)
773 .org ia64_ivt+0x3400
774 //////////////////////////////////////////////////////////////////////////
775 // 0x3400 Entry 13 (size 64 bundles) Reserved
776 DBG_FAULT(13)
777 FAULT(13)
779 // There is no particular reason for this code to be here, other
780 // than that there happens to be space here that would go unused
781 // otherwise. If this fault ever gets "unreserved", simply move
782 // the following code to a more suitable spot...
784 GLOBAL_ENTRY(dispatch_break_fault)
785 SAVE_MIN_WITH_COVER
786 ;;
787 dispatch_break_fault_post_save:
788 alloc r14=ar.pfs,0,0,4,0 // now it's safe (must be first in insn group!)
789 mov out0=cr.ifa
790 adds out1=16,sp
791 mov out2=cr.isr // FIXME: pity to make this slow access twice
792 mov out3=cr.iim // FIXME: pity to make this slow access twice
794 ssm psr.ic | PSR_DEFAULT_BITS
795 ;;
796 srlz.i // guarantee that interruption collection is on
797 ;;
798 (p15) ssm psr.i // restore psr.i
799 adds r3=8,r2 // set up second base pointer
800 ;;
801 SAVE_REST
802 movl r14=ia64_leave_kernel
803 ;;
804 mov rp=r14
805 br.call.sptk.many b6=ia64_handle_break
806 END(dispatch_break_fault)
808 .org ia64_ivt+0x3800
809 //////////////////////////////////////////////////////////////////////////
810 // 0x3800 Entry 14 (size 64 bundles) Reserved
811 DBG_FAULT(14)
812 FAULT(14)
814 // this code segment is from 2.6.16.13
816 /*
817 * There is no particular reason for this code to be here, other than that
818 * there happens to be space here that would go unused otherwise. If this
819 * fault ever gets "unreserved", simply moved the following code to a more
820 * suitable spot...
821 *
822 * ia64_syscall_setup() is a separate subroutine so that it can
823 * allocate stacked registers so it can safely demine any
824 * potential NaT values from the input registers.
825 *
826 * On entry:
827 * - executing on bank 0 or bank 1 register set (doesn't matter)
828 * - r1: stack pointer
829 * - r2: current task pointer
830 * - r3: preserved
831 * - r11: original contents (saved ar.pfs to be saved)
832 * - r12: original contents (sp to be saved)
833 * - r13: original contents (tp to be saved)
834 * - r15: original contents (syscall # to be saved)
835 * - r18: saved bsp (after switching to kernel stack)
836 * - r19: saved b6
837 * - r20: saved r1 (gp)
838 * - r21: saved ar.fpsr
839 * - r22: kernel's register backing store base (krbs_base)
840 * - r23: saved ar.bspstore
841 * - r24: saved ar.rnat
842 * - r25: saved ar.unat
843 * - r26: saved ar.pfs
844 * - r27: saved ar.rsc
845 * - r28: saved cr.iip
846 * - r29: saved cr.ipsr
847 * - r31: saved pr
848 * - b0: original contents (to be saved)
849 * On exit:
850 * - p10: TRUE if syscall is invoked with more than 8 out
851 * registers or r15's Nat is true
852 * - r1: kernel's gp
853 * - r3: preserved (same as on entry)
854 * - r8: -EINVAL if p10 is true
855 * - r12: points to kernel stack
856 * - r13: points to current task
857 * - r14: preserved (same as on entry)
858 * - p13: preserved
859 * - p15: TRUE if interrupts need to be re-enabled
860 * - ar.fpsr: set to kernel settings
861 * - b6: preserved (same as on entry)
862 */
863 GLOBAL_ENTRY(ia64_syscall_setup)
864 #if PT(B6) != 0
865 # error This code assumes that b6 is the first field in pt_regs.
866 #endif
867 st8 [r1]=r19 // save b6
868 add r16=PT(CR_IPSR),r1 // initialize first base pointer
869 add r17=PT(R11),r1 // initialize second base pointer
870 ;;
871 alloc r19=ar.pfs,8,0,0,0 // ensure in0-in7 are writable
872 st8 [r16]=r29,PT(AR_PFS)-PT(CR_IPSR) // save cr.ipsr
873 tnat.nz p8,p0=in0
875 st8.spill [r17]=r11,PT(CR_IIP)-PT(R11) // save r11
876 tnat.nz p9,p0=in1
877 (pKStk) mov r18=r0 // make sure r18 isn't NaT
878 ;;
880 st8 [r16]=r26,PT(CR_IFS)-PT(AR_PFS) // save ar.pfs
881 st8 [r17]=r28,PT(AR_UNAT)-PT(CR_IIP) // save cr.iip
882 mov r28=b0 // save b0 (2 cyc)
883 ;;
885 st8 [r17]=r25,PT(AR_RSC)-PT(AR_UNAT) // save ar.unat
886 dep r19=0,r19,38,26 // clear all bits but 0..37 [I0]
887 (p8) mov in0=-1
888 ;;
890 st8 [r16]=r19,PT(AR_RNAT)-PT(CR_IFS) // store ar.pfs.pfm in cr.ifs
891 extr.u r11=r19,7,7 // I0 // get sol of ar.pfs
892 and r8=0x7f,r19 // A // get sof of ar.pfs
894 st8 [r17]=r27,PT(AR_BSPSTORE)-PT(AR_RSC)// save ar.rsc
895 tbit.nz p15,p0=r29,IA64_PSR_I_BIT // I0
896 (p9) mov in1=-1
897 ;;
899 (pUStk) sub r18=r18,r22 // r18=RSE.ndirty*8
900 tnat.nz p10,p0=in2
901 add r11=8,r11
902 ;;
903 (pKStk) adds r16=PT(PR)-PT(AR_RNAT),r16 // skip over ar_rnat field
904 (pKStk) adds r17=PT(B0)-PT(AR_BSPSTORE),r17 // skip over ar_bspstore field
905 tnat.nz p11,p0=in3
906 ;;
907 (p10) mov in2=-1
908 tnat.nz p12,p0=in4 // [I0]
909 (p11) mov in3=-1
910 ;;
911 (pUStk) st8 [r16]=r24,PT(PR)-PT(AR_RNAT) // save ar.rnat
912 (pUStk) st8 [r17]=r23,PT(B0)-PT(AR_BSPSTORE) // save ar.bspstore
913 shl r18=r18,16 // compute ar.rsc to be used for "loadrs"
914 ;;
915 st8 [r16]=r31,PT(LOADRS)-PT(PR) // save predicates
916 st8 [r17]=r28,PT(R1)-PT(B0) // save b0
917 tnat.nz p13,p0=in5 // [I0]
918 ;;
919 st8 [r16]=r18,PT(R12)-PT(LOADRS) // save ar.rsc value for "loadrs"
920 st8.spill [r17]=r20,PT(R13)-PT(R1) // save original r1
921 (p12) mov in4=-1
922 ;;
924 .mem.offset 0,0; st8.spill [r16]=r12,PT(AR_FPSR)-PT(R12) // save r12
925 .mem.offset 8,0; st8.spill [r17]=r13,PT(R15)-PT(R13) // save r13
926 (p13) mov in5=-1
927 ;;
928 st8 [r16]=r21,PT(R8)-PT(AR_FPSR) // save ar.fpsr
929 tnat.nz p13,p0=in6
930 cmp.lt p10,p9=r11,r8 // frame size can't be more than local+8
931 ;;
932 mov r8=1
933 (p9) tnat.nz p10,p0=r15
934 adds r12=-16,r1 // switch to kernel memory stack (with 16 bytes of scratch)
936 st8.spill [r17]=r15 // save r15
937 tnat.nz p8,p0=in7
938 nop.i 0
940 mov r13=r2 // establish `current'
941 movl r1=__gp // establish kernel global pointer
942 ;;
943 st8 [r16]=r8 // ensure pt_regs.r8 != 0 (see handle_syscall_error)
944 (p13) mov in6=-1
945 (p8) mov in7=-1
947 cmp.eq pSys,pNonSys=r0,r0 // set pSys=1, pNonSys=0
948 movl r17=FPSR_DEFAULT
949 ;;
950 mov.m ar.fpsr=r17 // set ar.fpsr to kernel default value
951 (p10) mov r8=-EINVAL
952 br.ret.sptk.many b7
953 END(ia64_syscall_setup)
956 .org ia64_ivt+0x3c00
957 //////////////////////////////////////////////////////////////////////////
958 // 0x3c00 Entry 15 (size 64 bundles) Reserved
959 DBG_FAULT(15)
960 FAULT(15)
963 .org ia64_ivt+0x4000
964 //////////////////////////////////////////////////////////////////////////
965 // 0x4000 Entry 16 (size 64 bundles) Reserved
966 DBG_FAULT(16)
967 FAULT(16)
969 // There is no particular reason for this code to be here, other
970 // than that there happens to be space here that would go unused
971 // otherwise. If this fault ever gets "unreserved", simply move
972 // the following code to a more suitable spot...
974 ENTRY(dispatch_privop_fault)
975 SAVE_MIN_WITH_COVER
976 ;;
977 alloc r14=ar.pfs,0,0,4,0 // now it's safe (must be first in
978 // insn group!)
979 mov out0=cr.ifa
980 adds out1=16,sp
981 mov out2=cr.isr // FIXME: pity to make this slow access twice
982 mov out3=cr.itir
984 ssm psr.ic | PSR_DEFAULT_BITS
985 ;;
986 srlz.i // guarantee that interruption
987 // collection is on
988 ;;
989 (p15) ssm psr.i // restore psr.i
990 adds r3=8,r2 // set up second base pointer
991 ;;
992 SAVE_REST
993 movl r14=ia64_leave_kernel
994 ;;
995 mov rp=r14
996 br.call.sptk.many b6=ia64_handle_privop
997 END(dispatch_privop_fault)
1000 .org ia64_ivt+0x4400
1001 //////////////////////////////////////////////////////////////////////////
1002 // 0x4400 Entry 17 (size 64 bundles) Reserved
1003 DBG_FAULT(17)
1004 FAULT(17)
1007 .org ia64_ivt+0x4800
1008 //////////////////////////////////////////////////////////////////////////
1009 // 0x4800 Entry 18 (size 64 bundles) Reserved
1010 DBG_FAULT(18)
1011 FAULT(18)
1014 .org ia64_ivt+0x4c00
1015 //////////////////////////////////////////////////////////////////////////
1016 // 0x4c00 Entry 19 (size 64 bundles) Reserved
1017 DBG_FAULT(19)
1018 FAULT(19)
1020 /*
1021 * There is no particular reason for this code to be here, other
1022 * than that there happens to be space here that would go unused
1023 * otherwise. If this fault ever gets "unreserved", simply move
1024 * the following code to a more suitable spot...
1025 */
1027 GLOBAL_ENTRY(dispatch_to_fault_handler)
1028 /*
1029 * Input:
1030 * psr.ic: off
1031 * r19: fault vector number (e.g., 24 for General Exception)
1032 * r31: contains saved predicates (pr)
1033 */
1034 SAVE_MIN_WITH_COVER_R19
1035 alloc r14=ar.pfs,0,0,5,0
1036 mov out0=r15
1037 mov out1=cr.isr
1038 mov out2=cr.ifa
1039 mov out3=cr.iim
1040 mov out4=cr.itir
1041 ;;
1042 ssm psr.ic | PSR_DEFAULT_BITS
1043 ;;
1044 srlz.i // guarantee that interruption
1045 // collection is on
1046 ;;
1047 (p15) ssm psr.i // restore psr.i
1048 adds r3=8,r2 // set up second base pointer for
1049 // SAVE_REST
1050 ;;
1051 SAVE_REST
1052 movl r14=ia64_leave_kernel
1053 ;;
1054 mov rp=r14
1055 br.call.sptk.many b6=ia64_fault
1056 END(dispatch_to_fault_handler)
1058 //
1059 // --- End of long entries, Beginning of short entries
1060 //
1062 .org ia64_ivt+0x5000
1063 //////////////////////////////////////////////////////////////////////////
1064 // 0x5000 Entry 20 (size 16 bundles) Page Not Present (10,22,49)
1065 ENTRY(page_not_present)
1066 DBG_FAULT(20)
1067 FAULT_OR_REFLECT(20)
1068 END(page_not_present)
1070 .org ia64_ivt+0x5100
1071 //////////////////////////////////////////////////////////////////////////
1072 // 0x5100 Entry 21 (size 16 bundles) Key Permission (13,25,52)
1073 ENTRY(key_permission)
1074 DBG_FAULT(21)
1075 FAULT_OR_REFLECT(21)
1076 END(key_permission)
1078 .org ia64_ivt+0x5200
1079 //////////////////////////////////////////////////////////////////////////
1080 // 0x5200 Entry 22 (size 16 bundles) Instruction Access Rights (26)
1081 ENTRY(iaccess_rights)
1082 DBG_FAULT(22)
1083 FAULT_OR_REFLECT(22)
1084 END(iaccess_rights)
1086 .org ia64_ivt+0x5300
1087 //////////////////////////////////////////////////////////////////////////
1088 // 0x5300 Entry 23 (size 16 bundles) Data Access Rights (14,53)
1089 ENTRY(daccess_rights)
1090 DBG_FAULT(23)
1091 mov r31=pr
1092 mov r16=cr.isr
1093 mov r17=cr.ifa
1094 mov r19=23
1095 mov r20=0x5300
1096 br.sptk.many fast_access_reflect
1097 ;;
1098 END(daccess_rights)
1100 .org ia64_ivt+0x5400
1101 //////////////////////////////////////////////////////////////////////////
1102 // 0x5400 Entry 24 (size 16 bundles) General Exception (5,32,34,36,38,39)
1103 ENTRY(general_exception)
1104 DBG_FAULT(24)
1105 mov r16=cr.isr
1106 mov r31=pr
1107 ;;
1108 cmp4.ge p6,p0=0x20,r16
1109 (p6) br.sptk.many dispatch_privop_fault
1110 ;;
1111 FAULT_OR_REFLECT(24)
1112 END(general_exception)
1114 .org ia64_ivt+0x5500
1115 //////////////////////////////////////////////////////////////////////////
1116 // 0x5500 Entry 25 (size 16 bundles) Disabled FP-Register (35)
1117 ENTRY(disabled_fp_reg)
1118 DBG_FAULT(25)
1119 FAULT_OR_REFLECT(25)
1120 END(disabled_fp_reg)
1122 .org ia64_ivt+0x5600
1123 //////////////////////////////////////////////////////////////////////////
1124 // 0x5600 Entry 26 (size 16 bundles) Nat Consumption (11,23,37,50)
1125 ENTRY(nat_consumption)
1126 DBG_FAULT(26)
1127 FAULT_OR_REFLECT(26)
1128 END(nat_consumption)
1130 .org ia64_ivt+0x5700
1131 //////////////////////////////////////////////////////////////////////////
1132 // 0x5700 Entry 27 (size 16 bundles) Speculation (40)
1133 ENTRY(speculation_vector)
1134 DBG_FAULT(27)
1135 // this probably need not reflect...
1136 FAULT_OR_REFLECT(27)
1137 END(speculation_vector)
1139 .org ia64_ivt+0x5800
1140 //////////////////////////////////////////////////////////////////////////
1141 // 0x5800 Entry 28 (size 16 bundles) Reserved
1142 DBG_FAULT(28)
1143 FAULT(28)
1145 .org ia64_ivt+0x5900
1146 //////////////////////////////////////////////////////////////////////////
1147 // 0x5900 Entry 29 (size 16 bundles) Debug (16,28,56)
1148 ENTRY(debug_vector)
1149 DBG_FAULT(29)
1150 FAULT_OR_REFLECT(29)
1151 END(debug_vector)
1153 .org ia64_ivt+0x5a00
1154 //////////////////////////////////////////////////////////////////////////
1155 // 0x5a00 Entry 30 (size 16 bundles) Unaligned Reference (57)
1156 ENTRY(unaligned_access)
1157 DBG_FAULT(30)
1158 FAULT_OR_REFLECT(30)
1159 END(unaligned_access)
1161 .org ia64_ivt+0x5b00
1162 //////////////////////////////////////////////////////////////////////////
1163 // 0x5b00 Entry 31 (size 16 bundles) Unsupported Data Reference (57)
1164 ENTRY(unsupported_data_reference)
1165 DBG_FAULT(31)
1166 FAULT_OR_REFLECT(31)
1167 END(unsupported_data_reference)
1169 .org ia64_ivt+0x5c00
1170 //////////////////////////////////////////////////////////////////////////
1171 // 0x5c00 Entry 32 (size 16 bundles) Floating-Point Fault (64)
1172 ENTRY(floating_point_fault)
1173 DBG_FAULT(32)
1174 FAULT_OR_REFLECT(32)
1175 END(floating_point_fault)
1177 .org ia64_ivt+0x5d00
1178 //////////////////////////////////////////////////////////////////////////
1179 // 0x5d00 Entry 33 (size 16 bundles) Floating Point Trap (66)
1180 ENTRY(floating_point_trap)
1181 DBG_FAULT(33)
1182 FAULT_OR_REFLECT(33)
1183 END(floating_point_trap)
1185 .org ia64_ivt+0x5e00
1186 //////////////////////////////////////////////////////////////////////////
1187 // 0x5e00 Entry 34 (size 16 bundles) Lower Privilege Transfer Trap (66)
1188 ENTRY(lower_privilege_trap)
1189 DBG_FAULT(34)
1190 FAULT_OR_REFLECT(34)
1191 END(lower_privilege_trap)
1193 .org ia64_ivt+0x5f00
1194 //////////////////////////////////////////////////////////////////////////
1195 // 0x5f00 Entry 35 (size 16 bundles) Taken Branch Trap (68)
1196 ENTRY(taken_branch_trap)
1197 DBG_FAULT(35)
1198 FAULT_OR_REFLECT(35)
1199 END(taken_branch_trap)
1201 .org ia64_ivt+0x6000
1202 //////////////////////////////////////////////////////////////////////////
1203 // 0x6000 Entry 36 (size 16 bundles) Single Step Trap (69)
1204 ENTRY(single_step_trap)
1205 DBG_FAULT(36)
1206 FAULT_OR_REFLECT(36)
1207 END(single_step_trap)
1209 .org ia64_ivt+0x6100
1210 //////////////////////////////////////////////////////////////////////////
1211 // 0x6100 Entry 37 (size 16 bundles) Reserved
1212 DBG_FAULT(37)
1213 FAULT(37)
1215 .org ia64_ivt+0x6200
1216 //////////////////////////////////////////////////////////////////////////
1217 // 0x6200 Entry 38 (size 16 bundles) Reserved
1218 DBG_FAULT(38)
1219 FAULT(38)
1221 .org ia64_ivt+0x6300
1222 //////////////////////////////////////////////////////////////////////////
1223 // 0x6300 Entry 39 (size 16 bundles) Reserved
1224 DBG_FAULT(39)
1225 FAULT(39)
1227 .org ia64_ivt+0x6400
1228 //////////////////////////////////////////////////////////////////////////
1229 // 0x6400 Entry 40 (size 16 bundles) Reserved
1230 DBG_FAULT(40)
1231 FAULT(40)
1233 .org ia64_ivt+0x6500
1234 //////////////////////////////////////////////////////////////////////////
1235 // 0x6500 Entry 41 (size 16 bundles) Reserved
1236 DBG_FAULT(41)
1237 FAULT(41)
1239 .org ia64_ivt+0x6600
1240 //////////////////////////////////////////////////////////////////////////
1241 // 0x6600 Entry 42 (size 16 bundles) Reserved
1242 DBG_FAULT(42)
1243 FAULT(42)
1245 .org ia64_ivt+0x6700
1246 //////////////////////////////////////////////////////////////////////////
1247 // 0x6700 Entry 43 (size 16 bundles) Reserved
1248 DBG_FAULT(43)
1249 FAULT(43)
1251 .org ia64_ivt+0x6800
1252 //////////////////////////////////////////////////////////////////////////
1253 // 0x6800 Entry 44 (size 16 bundles) Reserved
1254 DBG_FAULT(44)
1255 FAULT(44)
1257 .org ia64_ivt+0x6900
1258 //////////////////////////////////////////////////////////////////////////
1259 // 0x6900 Entry 45 (size 16 bundles) IA-32 Exeception (17,18,29,41,42,43,
1260 // 44,58,60,61,62,72,
1261 // 73,75,76,77)
1262 ENTRY(ia32_exception)
1263 DBG_FAULT(45)
1264 FAULT_OR_REFLECT(45)
1265 END(ia32_exception)
1267 .org ia64_ivt+0x6a00
1268 //////////////////////////////////////////////////////////////////////////
1269 // 0x6a00 Entry 46 (size 16 bundles) IA-32 Intercept (30,31,59,70,71)
1270 ENTRY(ia32_intercept)
1271 DBG_FAULT(46)
1272 FAULT_OR_REFLECT(46)
1273 END(ia32_intercept)
1275 .org ia64_ivt+0x6b00
1276 //////////////////////////////////////////////////////////////////////////
1277 // 0x6b00 Entry 47 (size 16 bundles) IA-32 Interrupt (74)
1278 ENTRY(ia32_interrupt)
1279 DBG_FAULT(47)
1280 FAULT_OR_REFLECT(47)
1281 END(ia32_interrupt)
1283 .org ia64_ivt+0x6c00
1284 //////////////////////////////////////////////////////////////////////////
1285 // 0x6c00 Entry 48 (size 16 bundles) Reserved
1286 DBG_FAULT(48)
1287 FAULT(48)
1289 .org ia64_ivt+0x6d00
1290 //////////////////////////////////////////////////////////////////////////
1291 // 0x6d00 Entry 49 (size 16 bundles) Reserved
1292 DBG_FAULT(49)
1293 FAULT(49)
1295 .org ia64_ivt+0x6e00
1296 //////////////////////////////////////////////////////////////////////////
1297 // 0x6e00 Entry 50 (size 16 bundles) Reserved
1298 DBG_FAULT(50)
1299 FAULT(50)
1301 .org ia64_ivt+0x6f00
1302 //////////////////////////////////////////////////////////////////////////
1303 // 0x6f00 Entry 51 (size 16 bundles) Reserved
1304 DBG_FAULT(51)
1305 FAULT(51)
1307 .org ia64_ivt+0x7000
1308 //////////////////////////////////////////////////////////////////////////
1309 // 0x7000 Entry 52 (size 16 bundles) Reserved
1310 DBG_FAULT(52)
1311 FAULT(52)
1313 .org ia64_ivt+0x7100
1314 //////////////////////////////////////////////////////////////////////////
1315 // 0x7100 Entry 53 (size 16 bundles) Reserved
1316 DBG_FAULT(53)
1317 FAULT(53)
1319 .org ia64_ivt+0x7200
1320 //////////////////////////////////////////////////////////////////////////
1321 // 0x7200 Entry 54 (size 16 bundles) Reserved
1322 DBG_FAULT(54)
1323 FAULT(54)
1325 .org ia64_ivt+0x7300
1326 //////////////////////////////////////////////////////////////////////////
1327 // 0x7300 Entry 55 (size 16 bundles) Reserved
1328 DBG_FAULT(55)
1329 FAULT(55)
1331 .org ia64_ivt+0x7400
1332 //////////////////////////////////////////////////////////////////////////
1333 // 0x7400 Entry 56 (size 16 bundles) Reserved
1334 DBG_FAULT(56)
1335 FAULT(56)
1337 .org ia64_ivt+0x7500
1338 //////////////////////////////////////////////////////////////////////////
1339 // 0x7500 Entry 57 (size 16 bundles) Reserved
1340 DBG_FAULT(57)
1341 FAULT(57)
1343 .org ia64_ivt+0x7600
1344 //////////////////////////////////////////////////////////////////////////
1345 // 0x7600 Entry 58 (size 16 bundles) Reserved
1346 DBG_FAULT(58)
1347 FAULT(58)
1349 .org ia64_ivt+0x7700
1350 //////////////////////////////////////////////////////////////////////////
1351 // 0x7700 Entry 59 (size 16 bundles) Reserved
1352 DBG_FAULT(59)
1353 FAULT(59)
1355 .org ia64_ivt+0x7800
1356 //////////////////////////////////////////////////////////////////////////
1357 // 0x7800 Entry 60 (size 16 bundles) Reserved
1358 DBG_FAULT(60)
1359 FAULT(60)
1361 .org ia64_ivt+0x7900
1362 //////////////////////////////////////////////////////////////////////////
1363 // 0x7900 Entry 61 (size 16 bundles) Reserved
1364 DBG_FAULT(61)
1365 FAULT(61)
1367 .org ia64_ivt+0x7a00
1368 //////////////////////////////////////////////////////////////////////////
1369 // 0x7a00 Entry 62 (size 16 bundles) Reserved
1370 DBG_FAULT(62)
1371 FAULT(62)
1373 .org ia64_ivt+0x7b00
1374 //////////////////////////////////////////////////////////////////////////
1375 // 0x7b00 Entry 63 (size 16 bundles) Reserved
1376 DBG_FAULT(63)
1377 FAULT(63)
1379 .org ia64_ivt+0x7c00
1380 //////////////////////////////////////////////////////////////////////////
1381 // 0x7c00 Entry 64 (size 16 bundles) Reserved
1382 DBG_FAULT(64)
1383 FAULT(64)
1385 .org ia64_ivt+0x7d00
1386 //////////////////////////////////////////////////////////////////////////
1387 // 0x7d00 Entry 65 (size 16 bundles) Reserved
1388 DBG_FAULT(65)
1389 FAULT(65)
1391 .org ia64_ivt+0x7e00
1392 //////////////////////////////////////////////////////////////////////////
1393 // 0x7e00 Entry 66 (size 16 bundles) Reserved
1394 DBG_FAULT(66)
1395 FAULT(66)
1397 .org ia64_ivt+0x7f00
1398 //////////////////////////////////////////////////////////////////////////
1399 // 0x7f00 Entry 67 (size 16 bundles) Reserved
1400 DBG_FAULT(67)
1401 FAULT(67)
1403 .org ia64_ivt+0x8000