ia64/xen-unstable

view xen/arch/ia64/xen/flushd.S @ 16785:af3550f53874

[IA64] domheap: Don't pin xenheap down. Now it's unnecessary.

Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
author Alex Williamson <alex.williamson@hp.com>
date Thu Jan 17 12:05:43 2008 -0700 (2008-01-17)
parents 6fec75ff8acf
children
line source
1 /*
2 * Cache flushing routines.
3 *
4 * Copyright (C) 1999-2001, 2005 Hewlett-Packard Co
5 * David Mosberger-Tang <davidm@hpl.hp.com>
6 *
7 * 05/28/05 Zoltan Menyhart Dynamic stride size
8 * 03/31/06 Tristan Gingold copied and modified for dcache.
9 */
11 #include <asm/asmmacro.h>
14 /*
15 * flush_dcache_range(start,end)
16 *
17 * Flush cache.
18 *
19 * Must deal with range from start to end-1 but nothing else
20 * (need to be careful not to touch addresses that may be
21 * unmapped).
22 *
23 * Note: "in0" and "in1" are preserved for debugging purposes.
24 */
25 GLOBAL_ENTRY(flush_dcache_range)
27 .prologue
28 alloc r2=ar.pfs,2,0,0,0
29 movl r3=ia64_d_cache_stride_shift
30 mov r21=1
31 ;;
32 ld8 r20=[r3] // r20: stride shift
33 sub r22=in1,r0,1 // last byte address
34 ;;
35 shr.u r23=in0,r20 // start / (stride size)
36 shr.u r22=r22,r20 // (last byte address) / (stride size)
37 shl r21=r21,r20 // r21: stride size of the i-cache(s)
38 ;;
39 sub r8=r22,r23 // number of strides - 1
40 shl r24=r23,r20 // r24: addresses for "fc" =
41 // "start" rounded down to stride
42 // boundary
43 .save ar.lc,r3
44 mov r3=ar.lc // save ar.lc
45 ;;
47 .body
48 mov ar.lc=r8
49 ;;
50 /*
51 * 32 byte aligned loop, even number of (actually 2) bundles
52 */
53 .Loop: fc r24 // issuable on M0 only
54 add r24=r21,r24 // we flush "stride size" bytes per
55 // iteration
56 nop.i 0
57 br.cloop.sptk.few .Loop
58 ;;
59 sync.i
60 ;;
61 srlz.i
62 ;;
63 mov ar.lc=r3 // restore ar.lc
64 br.ret.sptk.many rp
65 END(flush_dcache_range)