ia64/xen-unstable

view xen/arch/ia64/linux-xen/head.S @ 16785:af3550f53874

[IA64] domheap: Don't pin xenheap down. Now it's unnecessary.

Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
author Alex Williamson <alex.williamson@hp.com>
date Thu Jan 17 12:05:43 2008 -0700 (2008-01-17)
parents fd56e24b07c8
children 54e5d15af567
line source
1 /*
2 * Here is where the ball gets rolling as far as the kernel is concerned.
3 * When control is transferred to _start, the bootload has already
4 * loaded us to the correct address. All that's left to do here is
5 * to set up the kernel's global pointer and jump to the kernel
6 * entry point.
7 *
8 * Copyright (C) 1998-2001, 2003, 2005 Hewlett-Packard Co
9 * David Mosberger-Tang <davidm@hpl.hp.com>
10 * Stephane Eranian <eranian@hpl.hp.com>
11 * Copyright (C) 1999 VA Linux Systems
12 * Copyright (C) 1999 Walt Drummond <drummond@valinux.com>
13 * Copyright (C) 1999 Intel Corp.
14 * Copyright (C) 1999 Asit Mallick <Asit.K.Mallick@intel.com>
15 * Copyright (C) 1999 Don Dugger <Don.Dugger@intel.com>
16 * Copyright (C) 2002 Fenghua Yu <fenghua.yu@intel.com>
17 * -Optimize __ia64_save_fpu() and __ia64_load_fpu() for Itanium 2.
18 * Copyright (C) 2004 Ashok Raj <ashok.raj@intel.com>
19 * Support for CPU Hotplug
20 */
22 #include <linux/config.h>
24 #include <asm/asmmacro.h>
25 #include <asm/fpu.h>
26 #include <asm/kregs.h>
27 #include <asm/mmu_context.h>
28 #include <asm/offsets.h>
29 #include <asm/pal.h>
30 #include <asm/pgtable.h>
31 #include <asm/processor.h>
32 #include <asm/ptrace.h>
33 #include <asm/system.h>
34 #include <asm/mca_asm.h>
36 #ifdef CONFIG_HOTPLUG_CPU
37 #define SAL_PSR_BITS_TO_SET \
38 (IA64_PSR_AC | IA64_PSR_BN | IA64_PSR_MFH | IA64_PSR_MFL)
40 #define SAVE_FROM_REG(src, ptr, dest) \
41 mov dest=src;; \
42 st8 [ptr]=dest,0x08
44 #define RESTORE_REG(reg, ptr, _tmp) \
45 ld8 _tmp=[ptr],0x08;; \
46 mov reg=_tmp
48 #define SAVE_BREAK_REGS(ptr, _idx, _breg, _dest)\
49 mov ar.lc=IA64_NUM_DBG_REGS-1;; \
50 mov _idx=0;; \
51 1: \
52 SAVE_FROM_REG(_breg[_idx], ptr, _dest);; \
53 add _idx=1,_idx;; \
54 br.cloop.sptk.many 1b
56 #define RESTORE_BREAK_REGS(ptr, _idx, _breg, _tmp, _lbl)\
57 mov ar.lc=IA64_NUM_DBG_REGS-1;; \
58 mov _idx=0;; \
59 _lbl: RESTORE_REG(_breg[_idx], ptr, _tmp);; \
60 add _idx=1, _idx;; \
61 br.cloop.sptk.many _lbl
63 #define SAVE_ONE_RR(num, _reg, _tmp) \
64 movl _tmp=(num<<61);; \
65 mov _reg=rr[_tmp]
67 #define SAVE_REGION_REGS(_tmp, _r0, _r1, _r2, _r3, _r4, _r5, _r6, _r7) \
68 SAVE_ONE_RR(0,_r0, _tmp);; \
69 SAVE_ONE_RR(1,_r1, _tmp);; \
70 SAVE_ONE_RR(2,_r2, _tmp);; \
71 SAVE_ONE_RR(3,_r3, _tmp);; \
72 SAVE_ONE_RR(4,_r4, _tmp);; \
73 SAVE_ONE_RR(5,_r5, _tmp);; \
74 SAVE_ONE_RR(6,_r6, _tmp);; \
75 SAVE_ONE_RR(7,_r7, _tmp);;
77 #define STORE_REGION_REGS(ptr, _r0, _r1, _r2, _r3, _r4, _r5, _r6, _r7) \
78 st8 [ptr]=_r0, 8;; \
79 st8 [ptr]=_r1, 8;; \
80 st8 [ptr]=_r2, 8;; \
81 st8 [ptr]=_r3, 8;; \
82 st8 [ptr]=_r4, 8;; \
83 st8 [ptr]=_r5, 8;; \
84 st8 [ptr]=_r6, 8;; \
85 st8 [ptr]=_r7, 8;;
87 #define RESTORE_REGION_REGS(ptr, _idx1, _idx2, _tmp) \
88 mov ar.lc=0x08-1;; \
89 movl _idx1=0x00;; \
90 RestRR: \
91 dep.z _idx2=_idx1,61,3;; \
92 ld8 _tmp=[ptr],8;; \
93 mov rr[_idx2]=_tmp;; \
94 srlz.d;; \
95 add _idx1=1,_idx1;; \
96 br.cloop.sptk.few RestRR
98 #define SET_AREA_FOR_BOOTING_CPU(reg1, reg2) \
99 movl reg1=sal_state_for_booting_cpu;; \
100 ld8 reg2=[reg1];;
102 /*
103 * Adjust region registers saved before starting to save
104 * break regs and rest of the states that need to be preserved.
105 */
106 #define SAL_TO_OS_BOOT_HANDOFF_STATE_SAVE(_reg1,_reg2,_pred) \
107 SAVE_FROM_REG(b0,_reg1,_reg2);; \
108 SAVE_FROM_REG(b1,_reg1,_reg2);; \
109 SAVE_FROM_REG(b2,_reg1,_reg2);; \
110 SAVE_FROM_REG(b3,_reg1,_reg2);; \
111 SAVE_FROM_REG(b4,_reg1,_reg2);; \
112 SAVE_FROM_REG(b5,_reg1,_reg2);; \
113 st8 [_reg1]=r1,0x08;; \
114 st8 [_reg1]=r12,0x08;; \
115 st8 [_reg1]=r13,0x08;; \
116 SAVE_FROM_REG(ar.fpsr,_reg1,_reg2);; \
117 SAVE_FROM_REG(ar.pfs,_reg1,_reg2);; \
118 SAVE_FROM_REG(ar.rnat,_reg1,_reg2);; \
119 SAVE_FROM_REG(ar.unat,_reg1,_reg2);; \
120 SAVE_FROM_REG(ar.bspstore,_reg1,_reg2);; \
121 SAVE_FROM_REG(cr.dcr,_reg1,_reg2);; \
122 SAVE_FROM_REG(cr.iva,_reg1,_reg2);; \
123 SAVE_FROM_REG(cr.pta,_reg1,_reg2);; \
124 SAVE_FROM_REG(cr.itv,_reg1,_reg2);; \
125 SAVE_FROM_REG(cr.pmv,_reg1,_reg2);; \
126 SAVE_FROM_REG(cr.cmcv,_reg1,_reg2);; \
127 SAVE_FROM_REG(cr.lrr0,_reg1,_reg2);; \
128 SAVE_FROM_REG(cr.lrr1,_reg1,_reg2);; \
129 st8 [_reg1]=r4,0x08;; \
130 st8 [_reg1]=r5,0x08;; \
131 st8 [_reg1]=r6,0x08;; \
132 st8 [_reg1]=r7,0x08;; \
133 st8 [_reg1]=_pred,0x08;; \
134 SAVE_FROM_REG(ar.lc, _reg1, _reg2);; \
135 stf.spill.nta [_reg1]=f2,16;; \
136 stf.spill.nta [_reg1]=f3,16;; \
137 stf.spill.nta [_reg1]=f4,16;; \
138 stf.spill.nta [_reg1]=f5,16;; \
139 stf.spill.nta [_reg1]=f16,16;; \
140 stf.spill.nta [_reg1]=f17,16;; \
141 stf.spill.nta [_reg1]=f18,16;; \
142 stf.spill.nta [_reg1]=f19,16;; \
143 stf.spill.nta [_reg1]=f20,16;; \
144 stf.spill.nta [_reg1]=f21,16;; \
145 stf.spill.nta [_reg1]=f22,16;; \
146 stf.spill.nta [_reg1]=f23,16;; \
147 stf.spill.nta [_reg1]=f24,16;; \
148 stf.spill.nta [_reg1]=f25,16;; \
149 stf.spill.nta [_reg1]=f26,16;; \
150 stf.spill.nta [_reg1]=f27,16;; \
151 stf.spill.nta [_reg1]=f28,16;; \
152 stf.spill.nta [_reg1]=f29,16;; \
153 stf.spill.nta [_reg1]=f30,16;; \
154 stf.spill.nta [_reg1]=f31,16;;
156 #else
157 #define SET_AREA_FOR_BOOTING_CPU(a1, a2)
158 #define SAL_TO_OS_BOOT_HANDOFF_STATE_SAVE(a1,a2, a3)
159 #define SAVE_REGION_REGS(_tmp, _r0, _r1, _r2, _r3, _r4, _r5, _r6, _r7)
160 #define STORE_REGION_REGS(ptr, _r0, _r1, _r2, _r3, _r4, _r5, _r6, _r7)
161 #endif
163 #ifdef XEN
164 #define SET_ONE_RR(num, pgsize, _tmp1, _tmp2, vhpt) \
165 movl _tmp1=(num << 61);; \
166 movl _tmp2=((ia64_rid(IA64_REGION_ID_KERNEL, (num<<61)) << 8) | (pgsize << 2) | vhpt);; \
167 mov rr[_tmp1]=_tmp2
168 #else
169 #define SET_ONE_RR(num, pgsize, _tmp1, _tmp2, vhpt) \
170 movl _tmp1=(num << 61);; \
171 mov _tmp2=((ia64_rid(IA64_REGION_ID_KERNEL, (num<<61)) << 8) | (pgsize << 2) | vhpt);; \
172 mov rr[_tmp1]=_tmp2
173 #endif
175 .section __special_page_section,"ax"
177 .global empty_zero_page
178 empty_zero_page:
179 .skip PAGE_SIZE
181 #ifndef XEN
182 .global swapper_pg_dir
183 swapper_pg_dir:
184 .skip PAGE_SIZE
185 #endif
187 #if defined(XEN) && defined(CONFIG_VIRTUAL_FRAME_TABLE)
188 .global frametable_pg_dir
189 frametable_pg_dir:
190 .skip PAGE_SIZE
191 #endif
193 .rodata
194 halt_msg:
195 stringz "Halting kernel\n"
197 .text
199 .global start_ap
201 /*
202 * Start the kernel. When the bootloader passes control to _start(), r28
203 * points to the address of the boot parameter area. Execution reaches
204 * here in physical mode.
205 */
206 GLOBAL_ENTRY(_start)
207 start_ap:
208 .prologue
209 .save rp, r0 // terminate unwind chain with a NULL rp
210 .body
212 rsm psr.i | psr.ic
213 ;;
214 srlz.i
215 ;;
216 /*
217 * Save the region registers, predicate before they get clobbered
218 */
219 SAVE_REGION_REGS(r2, r8,r9,r10,r11,r12,r13,r14,r15);
220 mov r25=pr;;
222 /*
223 * Initialize kernel region registers:
224 * rr[0]: VHPT enabled, page size = PAGE_SHIFT
225 * rr[1]: VHPT enabled, page size = PAGE_SHIFT
226 * rr[2]: VHPT enabled, page size = PAGE_SHIFT
227 * rr[3]: VHPT enabled, page size = PAGE_SHIFT
228 * rr[4]: VHPT enabled, page size = PAGE_SHIFT
229 * rr[5]: VHPT enabled, page size = PAGE_SHIFT
230 * rr[6]: VHPT disabled, page size = IA64_GRANULE_SHIFT
231 * rr[7]: VHPT disabled, page size = IA64_GRANULE_SHIFT
232 * We initialize all of them to prevent inadvertently assuming
233 * something about the state of address translation early in boot.
234 */
235 SET_ONE_RR(0, PAGE_SHIFT, r2, r16, 1);;
236 SET_ONE_RR(1, PAGE_SHIFT, r2, r16, 1);;
237 SET_ONE_RR(2, PAGE_SHIFT, r2, r16, 1);;
238 SET_ONE_RR(3, PAGE_SHIFT, r2, r16, 1);;
239 SET_ONE_RR(4, PAGE_SHIFT, r2, r16, 1);;
240 SET_ONE_RR(5, PAGE_SHIFT, r2, r16, 1);;
241 SET_ONE_RR(6, IA64_GRANULE_SHIFT, r2, r16, 0);;
242 SET_ONE_RR(7, IA64_GRANULE_SHIFT, r2, r16, 0);;
243 /*
244 * Now pin mappings into the TLB for kernel text and data
245 */
246 mov r18=KERNEL_TR_PAGE_SHIFT<<2
247 movl r17=KERNEL_START
248 ;;
249 mov cr.itir=r18
250 mov cr.ifa=r17
251 mov r16=IA64_TR_KERNEL
252 mov r3=ip
253 movl r18=PAGE_KERNEL
254 ;;
255 dep r2=0,r3,0,KERNEL_TR_PAGE_SHIFT
256 ;;
257 or r18=r2,r18
258 ;;
259 srlz.i
260 ;;
261 itr.i itr[r16]=r18
262 ;;
263 itr.d dtr[r16]=r18
264 ;;
265 srlz.i
267 /*
268 * Switch into virtual mode:
269 */
270 movl r16=(IA64_PSR_IT|IA64_PSR_IC|IA64_PSR_DT|IA64_PSR_RT|IA64_PSR_DFH|IA64_PSR_BN \
271 |IA64_PSR_DI)
272 ;;
273 mov cr.ipsr=r16
274 movl r17=1f
275 ;;
276 mov cr.iip=r17
277 mov cr.ifs=r0
278 ;;
279 rfi
280 ;;
281 1: // now we are in virtual mode
283 SET_AREA_FOR_BOOTING_CPU(r2, r16);
285 STORE_REGION_REGS(r16, r8,r9,r10,r11,r12,r13,r14,r15);
286 SAL_TO_OS_BOOT_HANDOFF_STATE_SAVE(r16,r17,r25)
287 ;;
289 // set IVT entry point---can't access I/O ports without it
290 movl r3=ia64_ivt
291 ;;
292 mov cr.iva=r3
293 movl r2=FPSR_DEFAULT
294 ;;
295 srlz.i
296 movl gp=__gp
297 ;;
298 mov ar.fpsr=r2
299 ;;
301 #define isAP p2 // are we an Application Processor?
302 #define isBP p3 // are we the Bootstrap Processor?
304 #ifdef XEN
305 # define init_task init_task_mem
306 #endif
308 #ifdef CONFIG_SMP
309 /*
310 * Find the init_task for the currently booting CPU. At poweron, and in
311 * UP mode, task_for_booting_cpu is NULL.
312 */
313 movl r3=task_for_booting_cpu
314 ;;
315 ld8 r3=[r3]
316 movl r2=init_task
317 ;;
318 cmp.eq isBP,isAP=r3,r0
319 ;;
320 (isAP) mov r2=r3
321 #else
322 movl r2=init_task
323 cmp.eq isBP,isAP=r0,r0
324 #endif
325 ;;
326 tpa r3=r2 // r3 == phys addr of task struct
327 mov r16=-1
328 #ifndef XEN
329 (isBP) br.cond.dpnt .load_current // BP stack is on region 5 --- no need to map it
330 #endif
332 // load mapping for stack (virtaddr in r2, physaddr in r3)
333 rsm psr.ic
334 movl r17=PAGE_KERNEL
335 ;;
336 srlz.d
337 dep r18=0,r3,0,12
338 ;;
339 or r18=r17,r18
340 #ifdef XEN
341 dep r2=-1,r3,60,4 // IMVA of task
342 #else
343 dep r2=-1,r3,61,3 // IMVA of task
344 #endif
345 ;;
346 mov r17=rr[r2]
347 shr.u r16=r3,IA64_GRANULE_SHIFT
348 ;;
349 dep r17=0,r17,8,24
350 ;;
351 mov cr.itir=r17
352 mov cr.ifa=r2
354 mov r19=IA64_TR_CURRENT_STACK
355 ;;
356 itr.d dtr[r19]=r18
357 ;;
358 ssm psr.ic
359 srlz.d
360 ;;
362 .load_current:
363 // load the "current" pointer (r13) and ar.k6 with the current task
364 mov IA64_KR(CURRENT)=r2 // virtual address
365 mov IA64_KR(CURRENT_STACK)=r16
366 mov r13=r2
367 /*
368 * Reserve space at the top of the stack for "struct pt_regs". Kernel
369 * threads don't store interesting values in that structure, but the space
370 * still needs to be there because time-critical stuff such as the context
371 * switching can be implemented more efficiently (for example, __switch_to()
372 * always sets the psr.dfh bit of the task it is switching to).
373 */
375 addl r12=IA64_STK_OFFSET-IA64_PT_REGS_SIZE-16,r2
376 addl r2=IA64_RBS_OFFSET,r2 // initialize the RSE
377 mov ar.rsc=0 // place RSE in enforced lazy mode
378 ;;
379 loadrs // clear the dirty partition
380 ;;
381 mov ar.bspstore=r2 // establish the new RSE stack
382 ;;
383 mov ar.rsc=0x3 // place RSE in eager mode
385 #ifdef XEN
386 (isBP) dep r28=-1,r28,60,4 // make address virtual
387 #else
388 (isBP) dep r28=-1,r28,61,3 // make address virtual
389 #endif
390 (isBP) movl r2=ia64_boot_param
391 ;;
392 (isBP) st8 [r2]=r28 // save the address of the boot param area passed by the bootloader
394 #ifdef CONFIG_SMP
395 (isAP) br.call.sptk.many rp=start_secondary
396 .ret0:
397 (isAP) br.cond.sptk self
398 #endif
400 // This is executed by the bootstrap processor (bsp) only:
402 #ifdef CONFIG_IA64_FW_EMU
403 // initialize PAL & SAL emulator:
404 br.call.sptk.many rp=sys_fw_init
405 .ret1:
406 #endif
407 br.call.sptk.many rp=start_kernel
408 .ret2: addl r3=@ltoff(halt_msg),gp
409 ;;
410 alloc r2=ar.pfs,8,0,2,0
411 ;;
412 ld8 out0=[r3]
413 br.call.sptk.many b0=console_print
415 self: hint @pause
416 #ifdef XEN
417 ;;
418 br.sptk.many self // endless loop
419 ;;
420 #else
421 br.sptk.many self // endless loop
422 #endif
423 END(_start)
425 GLOBAL_ENTRY(ia64_save_debug_regs)
426 alloc r16=ar.pfs,1,0,0,0
427 mov r20=ar.lc // preserve ar.lc
428 mov ar.lc=IA64_NUM_DBG_REGS-1
429 mov r18=0
430 add r19=IA64_NUM_DBG_REGS*8,in0
431 ;;
432 1: mov r16=dbr[r18]
433 #ifdef CONFIG_ITANIUM
434 ;;
435 srlz.d
436 #endif
437 mov r17=ibr[r18]
438 add r18=1,r18
439 ;;
440 st8.nta [in0]=r16,8
441 st8.nta [r19]=r17,8
442 br.cloop.sptk.many 1b
443 ;;
444 mov ar.lc=r20 // restore ar.lc
445 br.ret.sptk.many rp
446 END(ia64_save_debug_regs)
448 GLOBAL_ENTRY(ia64_load_debug_regs)
449 alloc r16=ar.pfs,1,0,0,0
450 lfetch.nta [in0]
451 mov r20=ar.lc // preserve ar.lc
452 add r19=IA64_NUM_DBG_REGS*8,in0
453 mov ar.lc=IA64_NUM_DBG_REGS-1
454 mov r18=-1
455 ;;
456 1: ld8.nta r16=[in0],8
457 ld8.nta r17=[r19],8
458 add r18=1,r18
459 ;;
460 mov dbr[r18]=r16
461 #ifdef CONFIG_ITANIUM
462 ;;
463 srlz.d // Errata 132 (NoFix status)
464 #endif
465 mov ibr[r18]=r17
466 br.cloop.sptk.many 1b
467 ;;
468 mov ar.lc=r20 // restore ar.lc
469 br.ret.sptk.many rp
470 END(ia64_load_debug_regs)
472 GLOBAL_ENTRY(__ia64_save_fpu)
473 alloc r2=ar.pfs,1,4,0,0
474 adds loc0=96*16-16,in0
475 adds loc1=96*16-16-128,in0
476 ;;
477 stf.spill.nta [loc0]=f127,-256
478 stf.spill.nta [loc1]=f119,-256
479 ;;
480 stf.spill.nta [loc0]=f111,-256
481 stf.spill.nta [loc1]=f103,-256
482 ;;
483 stf.spill.nta [loc0]=f95,-256
484 stf.spill.nta [loc1]=f87,-256
485 ;;
486 stf.spill.nta [loc0]=f79,-256
487 stf.spill.nta [loc1]=f71,-256
488 ;;
489 stf.spill.nta [loc0]=f63,-256
490 stf.spill.nta [loc1]=f55,-256
491 adds loc2=96*16-32,in0
492 ;;
493 stf.spill.nta [loc0]=f47,-256
494 stf.spill.nta [loc1]=f39,-256
495 adds loc3=96*16-32-128,in0
496 ;;
497 stf.spill.nta [loc2]=f126,-256
498 stf.spill.nta [loc3]=f118,-256
499 ;;
500 stf.spill.nta [loc2]=f110,-256
501 stf.spill.nta [loc3]=f102,-256
502 ;;
503 stf.spill.nta [loc2]=f94,-256
504 stf.spill.nta [loc3]=f86,-256
505 ;;
506 stf.spill.nta [loc2]=f78,-256
507 stf.spill.nta [loc3]=f70,-256
508 ;;
509 stf.spill.nta [loc2]=f62,-256
510 stf.spill.nta [loc3]=f54,-256
511 adds loc0=96*16-48,in0
512 ;;
513 stf.spill.nta [loc2]=f46,-256
514 stf.spill.nta [loc3]=f38,-256
515 adds loc1=96*16-48-128,in0
516 ;;
517 stf.spill.nta [loc0]=f125,-256
518 stf.spill.nta [loc1]=f117,-256
519 ;;
520 stf.spill.nta [loc0]=f109,-256
521 stf.spill.nta [loc1]=f101,-256
522 ;;
523 stf.spill.nta [loc0]=f93,-256
524 stf.spill.nta [loc1]=f85,-256
525 ;;
526 stf.spill.nta [loc0]=f77,-256
527 stf.spill.nta [loc1]=f69,-256
528 ;;
529 stf.spill.nta [loc0]=f61,-256
530 stf.spill.nta [loc1]=f53,-256
531 adds loc2=96*16-64,in0
532 ;;
533 stf.spill.nta [loc0]=f45,-256
534 stf.spill.nta [loc1]=f37,-256
535 adds loc3=96*16-64-128,in0
536 ;;
537 stf.spill.nta [loc2]=f124,-256
538 stf.spill.nta [loc3]=f116,-256
539 ;;
540 stf.spill.nta [loc2]=f108,-256
541 stf.spill.nta [loc3]=f100,-256
542 ;;
543 stf.spill.nta [loc2]=f92,-256
544 stf.spill.nta [loc3]=f84,-256
545 ;;
546 stf.spill.nta [loc2]=f76,-256
547 stf.spill.nta [loc3]=f68,-256
548 ;;
549 stf.spill.nta [loc2]=f60,-256
550 stf.spill.nta [loc3]=f52,-256
551 adds loc0=96*16-80,in0
552 ;;
553 stf.spill.nta [loc2]=f44,-256
554 stf.spill.nta [loc3]=f36,-256
555 adds loc1=96*16-80-128,in0
556 ;;
557 stf.spill.nta [loc0]=f123,-256
558 stf.spill.nta [loc1]=f115,-256
559 ;;
560 stf.spill.nta [loc0]=f107,-256
561 stf.spill.nta [loc1]=f99,-256
562 ;;
563 stf.spill.nta [loc0]=f91,-256
564 stf.spill.nta [loc1]=f83,-256
565 ;;
566 stf.spill.nta [loc0]=f75,-256
567 stf.spill.nta [loc1]=f67,-256
568 ;;
569 stf.spill.nta [loc0]=f59,-256
570 stf.spill.nta [loc1]=f51,-256
571 adds loc2=96*16-96,in0
572 ;;
573 stf.spill.nta [loc0]=f43,-256
574 stf.spill.nta [loc1]=f35,-256
575 adds loc3=96*16-96-128,in0
576 ;;
577 stf.spill.nta [loc2]=f122,-256
578 stf.spill.nta [loc3]=f114,-256
579 ;;
580 stf.spill.nta [loc2]=f106,-256
581 stf.spill.nta [loc3]=f98,-256
582 ;;
583 stf.spill.nta [loc2]=f90,-256
584 stf.spill.nta [loc3]=f82,-256
585 ;;
586 stf.spill.nta [loc2]=f74,-256
587 stf.spill.nta [loc3]=f66,-256
588 ;;
589 stf.spill.nta [loc2]=f58,-256
590 stf.spill.nta [loc3]=f50,-256
591 adds loc0=96*16-112,in0
592 ;;
593 stf.spill.nta [loc2]=f42,-256
594 stf.spill.nta [loc3]=f34,-256
595 adds loc1=96*16-112-128,in0
596 ;;
597 stf.spill.nta [loc0]=f121,-256
598 stf.spill.nta [loc1]=f113,-256
599 ;;
600 stf.spill.nta [loc0]=f105,-256
601 stf.spill.nta [loc1]=f97,-256
602 ;;
603 stf.spill.nta [loc0]=f89,-256
604 stf.spill.nta [loc1]=f81,-256
605 ;;
606 stf.spill.nta [loc0]=f73,-256
607 stf.spill.nta [loc1]=f65,-256
608 ;;
609 stf.spill.nta [loc0]=f57,-256
610 stf.spill.nta [loc1]=f49,-256
611 adds loc2=96*16-128,in0
612 ;;
613 stf.spill.nta [loc0]=f41,-256
614 stf.spill.nta [loc1]=f33,-256
615 adds loc3=96*16-128-128,in0
616 ;;
617 stf.spill.nta [loc2]=f120,-256
618 stf.spill.nta [loc3]=f112,-256
619 ;;
620 stf.spill.nta [loc2]=f104,-256
621 stf.spill.nta [loc3]=f96,-256
622 ;;
623 stf.spill.nta [loc2]=f88,-256
624 stf.spill.nta [loc3]=f80,-256
625 ;;
626 stf.spill.nta [loc2]=f72,-256
627 stf.spill.nta [loc3]=f64,-256
628 ;;
629 stf.spill.nta [loc2]=f56,-256
630 stf.spill.nta [loc3]=f48,-256
631 ;;
632 stf.spill.nta [loc2]=f40
633 stf.spill.nta [loc3]=f32
634 br.ret.sptk.many rp
635 END(__ia64_save_fpu)
637 GLOBAL_ENTRY(__ia64_load_fpu)
638 alloc r2=ar.pfs,1,2,0,0
639 adds r3=128,in0
640 adds r14=256,in0
641 adds r15=384,in0
642 mov loc0=512
643 mov loc1=-1024+16
644 ;;
645 ldf.fill.nta f32=[in0],loc0
646 ldf.fill.nta f40=[ r3],loc0
647 ldf.fill.nta f48=[r14],loc0
648 ldf.fill.nta f56=[r15],loc0
649 ;;
650 ldf.fill.nta f64=[in0],loc0
651 ldf.fill.nta f72=[ r3],loc0
652 ldf.fill.nta f80=[r14],loc0
653 ldf.fill.nta f88=[r15],loc0
654 ;;
655 ldf.fill.nta f96=[in0],loc1
656 ldf.fill.nta f104=[ r3],loc1
657 ldf.fill.nta f112=[r14],loc1
658 ldf.fill.nta f120=[r15],loc1
659 ;;
660 ldf.fill.nta f33=[in0],loc0
661 ldf.fill.nta f41=[ r3],loc0
662 ldf.fill.nta f49=[r14],loc0
663 ldf.fill.nta f57=[r15],loc0
664 ;;
665 ldf.fill.nta f65=[in0],loc0
666 ldf.fill.nta f73=[ r3],loc0
667 ldf.fill.nta f81=[r14],loc0
668 ldf.fill.nta f89=[r15],loc0
669 ;;
670 ldf.fill.nta f97=[in0],loc1
671 ldf.fill.nta f105=[ r3],loc1
672 ldf.fill.nta f113=[r14],loc1
673 ldf.fill.nta f121=[r15],loc1
674 ;;
675 ldf.fill.nta f34=[in0],loc0
676 ldf.fill.nta f42=[ r3],loc0
677 ldf.fill.nta f50=[r14],loc0
678 ldf.fill.nta f58=[r15],loc0
679 ;;
680 ldf.fill.nta f66=[in0],loc0
681 ldf.fill.nta f74=[ r3],loc0
682 ldf.fill.nta f82=[r14],loc0
683 ldf.fill.nta f90=[r15],loc0
684 ;;
685 ldf.fill.nta f98=[in0],loc1
686 ldf.fill.nta f106=[ r3],loc1
687 ldf.fill.nta f114=[r14],loc1
688 ldf.fill.nta f122=[r15],loc1
689 ;;
690 ldf.fill.nta f35=[in0],loc0
691 ldf.fill.nta f43=[ r3],loc0
692 ldf.fill.nta f51=[r14],loc0
693 ldf.fill.nta f59=[r15],loc0
694 ;;
695 ldf.fill.nta f67=[in0],loc0
696 ldf.fill.nta f75=[ r3],loc0
697 ldf.fill.nta f83=[r14],loc0
698 ldf.fill.nta f91=[r15],loc0
699 ;;
700 ldf.fill.nta f99=[in0],loc1
701 ldf.fill.nta f107=[ r3],loc1
702 ldf.fill.nta f115=[r14],loc1
703 ldf.fill.nta f123=[r15],loc1
704 ;;
705 ldf.fill.nta f36=[in0],loc0
706 ldf.fill.nta f44=[ r3],loc0
707 ldf.fill.nta f52=[r14],loc0
708 ldf.fill.nta f60=[r15],loc0
709 ;;
710 ldf.fill.nta f68=[in0],loc0
711 ldf.fill.nta f76=[ r3],loc0
712 ldf.fill.nta f84=[r14],loc0
713 ldf.fill.nta f92=[r15],loc0
714 ;;
715 ldf.fill.nta f100=[in0],loc1
716 ldf.fill.nta f108=[ r3],loc1
717 ldf.fill.nta f116=[r14],loc1
718 ldf.fill.nta f124=[r15],loc1
719 ;;
720 ldf.fill.nta f37=[in0],loc0
721 ldf.fill.nta f45=[ r3],loc0
722 ldf.fill.nta f53=[r14],loc0
723 ldf.fill.nta f61=[r15],loc0
724 ;;
725 ldf.fill.nta f69=[in0],loc0
726 ldf.fill.nta f77=[ r3],loc0
727 ldf.fill.nta f85=[r14],loc0
728 ldf.fill.nta f93=[r15],loc0
729 ;;
730 ldf.fill.nta f101=[in0],loc1
731 ldf.fill.nta f109=[ r3],loc1
732 ldf.fill.nta f117=[r14],loc1
733 ldf.fill.nta f125=[r15],loc1
734 ;;
735 ldf.fill.nta f38 =[in0],loc0
736 ldf.fill.nta f46 =[ r3],loc0
737 ldf.fill.nta f54 =[r14],loc0
738 ldf.fill.nta f62 =[r15],loc0
739 ;;
740 ldf.fill.nta f70 =[in0],loc0
741 ldf.fill.nta f78 =[ r3],loc0
742 ldf.fill.nta f86 =[r14],loc0
743 ldf.fill.nta f94 =[r15],loc0
744 ;;
745 ldf.fill.nta f102=[in0],loc1
746 ldf.fill.nta f110=[ r3],loc1
747 ldf.fill.nta f118=[r14],loc1
748 ldf.fill.nta f126=[r15],loc1
749 ;;
750 ldf.fill.nta f39 =[in0],loc0
751 ldf.fill.nta f47 =[ r3],loc0
752 ldf.fill.nta f55 =[r14],loc0
753 ldf.fill.nta f63 =[r15],loc0
754 ;;
755 ldf.fill.nta f71 =[in0],loc0
756 ldf.fill.nta f79 =[ r3],loc0
757 ldf.fill.nta f87 =[r14],loc0
758 ldf.fill.nta f95 =[r15],loc0
759 ;;
760 ldf.fill.nta f103=[in0]
761 ldf.fill.nta f111=[ r3]
762 ldf.fill.nta f119=[r14]
763 ldf.fill.nta f127=[r15]
764 br.ret.sptk.many rp
765 END(__ia64_load_fpu)
767 GLOBAL_ENTRY(__ia64_init_fpu)
768 stf.spill [sp]=f0 // M3
769 mov f32=f0 // F
770 nop.b 0
772 ldfps f33,f34=[sp] // M0
773 ldfps f35,f36=[sp] // M1
774 mov f37=f0 // F
775 ;;
777 setf.s f38=r0 // M2
778 setf.s f39=r0 // M3
779 mov f40=f0 // F
781 ldfps f41,f42=[sp] // M0
782 ldfps f43,f44=[sp] // M1
783 mov f45=f0 // F
785 setf.s f46=r0 // M2
786 setf.s f47=r0 // M3
787 mov f48=f0 // F
789 ldfps f49,f50=[sp] // M0
790 ldfps f51,f52=[sp] // M1
791 mov f53=f0 // F
793 setf.s f54=r0 // M2
794 setf.s f55=r0 // M3
795 mov f56=f0 // F
797 ldfps f57,f58=[sp] // M0
798 ldfps f59,f60=[sp] // M1
799 mov f61=f0 // F
801 setf.s f62=r0 // M2
802 setf.s f63=r0 // M3
803 mov f64=f0 // F
805 ldfps f65,f66=[sp] // M0
806 ldfps f67,f68=[sp] // M1
807 mov f69=f0 // F
809 setf.s f70=r0 // M2
810 setf.s f71=r0 // M3
811 mov f72=f0 // F
813 ldfps f73,f74=[sp] // M0
814 ldfps f75,f76=[sp] // M1
815 mov f77=f0 // F
817 setf.s f78=r0 // M2
818 setf.s f79=r0 // M3
819 mov f80=f0 // F
821 ldfps f81,f82=[sp] // M0
822 ldfps f83,f84=[sp] // M1
823 mov f85=f0 // F
825 setf.s f86=r0 // M2
826 setf.s f87=r0 // M3
827 mov f88=f0 // F
829 /*
830 * When the instructions are cached, it would be faster to initialize
831 * the remaining registers with simply mov instructions (F-unit).
832 * This gets the time down to ~29 cycles. However, this would use up
833 * 33 bundles, whereas continuing with the above pattern yields
834 * 10 bundles and ~30 cycles.
835 */
837 ldfps f89,f90=[sp] // M0
838 ldfps f91,f92=[sp] // M1
839 mov f93=f0 // F
841 setf.s f94=r0 // M2
842 setf.s f95=r0 // M3
843 mov f96=f0 // F
845 ldfps f97,f98=[sp] // M0
846 ldfps f99,f100=[sp] // M1
847 mov f101=f0 // F
849 setf.s f102=r0 // M2
850 setf.s f103=r0 // M3
851 mov f104=f0 // F
853 ldfps f105,f106=[sp] // M0
854 ldfps f107,f108=[sp] // M1
855 mov f109=f0 // F
857 setf.s f110=r0 // M2
858 setf.s f111=r0 // M3
859 mov f112=f0 // F
861 ldfps f113,f114=[sp] // M0
862 ldfps f115,f116=[sp] // M1
863 mov f117=f0 // F
865 setf.s f118=r0 // M2
866 setf.s f119=r0 // M3
867 mov f120=f0 // F
869 ldfps f121,f122=[sp] // M0
870 ldfps f123,f124=[sp] // M1
871 mov f125=f0 // F
873 setf.s f126=r0 // M2
874 setf.s f127=r0 // M3
875 br.ret.sptk.many rp // F
876 END(__ia64_init_fpu)
878 /*
879 * Switch execution mode from virtual to physical
880 *
881 * Inputs:
882 * r16 = new psr to establish
883 * Output:
884 * r19 = old virtual address of ar.bsp
885 * r20 = old virtual address of sp
886 *
887 * Note: RSE must already be in enforced lazy mode
888 */
889 GLOBAL_ENTRY(ia64_switch_mode_phys)
890 {
891 alloc r2=ar.pfs,0,0,0,0
892 rsm psr.i | psr.ic // disable interrupts and interrupt collection
893 mov r15=ip
894 }
895 ;;
896 {
897 flushrs // must be first insn in group
898 srlz.i
899 }
900 ;;
901 mov cr.ipsr=r16 // set new PSR
902 add r3=1f-ia64_switch_mode_phys,r15
904 mov r19=ar.bsp
905 mov r20=sp
906 mov r14=rp // get return address into a general register
907 ;;
909 // going to physical mode, use tpa to translate virt->phys
910 tpa r17=r19
911 tpa r3=r3
912 tpa sp=sp
913 tpa r14=r14
914 ;;
916 mov r18=ar.rnat // save ar.rnat
917 mov ar.bspstore=r17 // this steps on ar.rnat
918 mov cr.iip=r3
919 mov cr.ifs=r0
920 ;;
921 mov ar.rnat=r18 // restore ar.rnat
922 rfi // must be last insn in group
923 ;;
924 1: mov rp=r14
925 br.ret.sptk.many rp
926 END(ia64_switch_mode_phys)
928 /*
929 * Switch execution mode from physical to virtual
930 *
931 * Inputs:
932 * r16 = new psr to establish
933 * r19 = new bspstore to establish
934 * r20 = new sp to establish
935 *
936 * Note: RSE must already be in enforced lazy mode
937 */
938 GLOBAL_ENTRY(ia64_switch_mode_virt)
939 {
940 alloc r2=ar.pfs,0,0,0,0
941 rsm psr.i | psr.ic // disable interrupts and interrupt collection
942 mov r15=ip
943 }
944 ;;
945 {
946 flushrs // must be first insn in group
947 srlz.i
948 }
949 ;;
950 mov cr.ipsr=r16 // set new PSR
951 add r3=1f-ia64_switch_mode_virt,r15
953 mov r14=rp // get return address into a general register
954 ;;
956 // going to virtual
957 // - for code addresses, set upper bits of addr to KERNEL_START
958 // - for stack addresses, copy from input argument
959 movl r18=KERNEL_START
960 dep r3=0,r3,KERNEL_TR_PAGE_SHIFT,64-KERNEL_TR_PAGE_SHIFT
961 dep r14=0,r14,KERNEL_TR_PAGE_SHIFT,64-KERNEL_TR_PAGE_SHIFT
962 mov sp=r20
963 ;;
964 or r3=r3,r18
965 or r14=r14,r18
966 ;;
968 mov r18=ar.rnat // save ar.rnat
969 mov ar.bspstore=r19 // this steps on ar.rnat
970 mov cr.iip=r3
971 mov cr.ifs=r0
972 ;;
973 mov ar.rnat=r18 // restore ar.rnat
974 rfi // must be last insn in group
975 ;;
976 1: mov rp=r14
977 br.ret.sptk.many rp
978 END(ia64_switch_mode_virt)
980 GLOBAL_ENTRY(ia64_delay_loop)
981 .prologue
982 { nop 0 // work around GAS unwind info generation bug...
983 .save ar.lc,r2
984 mov r2=ar.lc
985 .body
986 ;;
987 mov ar.lc=r32
988 }
989 ;;
990 // force loop to be 32-byte aligned (GAS bug means we cannot use .align
991 // inside function body without corrupting unwind info).
992 { nop 0 }
993 1: br.cloop.sptk.few 1b
994 ;;
995 mov ar.lc=r2
996 br.ret.sptk.many rp
997 END(ia64_delay_loop)
999 #ifndef XEN
1000 /*
1001 * Return a CPU-local timestamp in nano-seconds. This timestamp is
1002 * NOT synchronized across CPUs its return value must never be
1003 * compared against the values returned on another CPU. The usage in
1004 * kernel/sched.c ensures that.
1006 * The return-value of sched_clock() is NOT supposed to wrap-around.
1007 * If it did, it would cause some scheduling hiccups (at the worst).
1008 * Fortunately, with a 64-bit cycle-counter ticking at 100GHz, even
1009 * that would happen only once every 5+ years.
1011 * The code below basically calculates:
1013 * (ia64_get_itc() * local_cpu_data->nsec_per_cyc) >> IA64_NSEC_PER_CYC_SHIFT
1015 * except that the multiplication and the shift are done with 128-bit
1016 * intermediate precision so that we can produce a full 64-bit result.
1017 */
1018 GLOBAL_ENTRY(sched_clock)
1019 #ifdef XEN
1020 movl r8=THIS_CPU(cpu_info) + IA64_CPUINFO_NSEC_PER_CYC_OFFSET
1021 #else
1022 addl r8=THIS_CPU(cpu_info) + IA64_CPUINFO_NSEC_PER_CYC_OFFSET,r0
1023 #endif
1024 mov.m r9=ar.itc // fetch cycle-counter (35 cyc)
1025 ;;
1026 ldf8 f8=[r8]
1027 ;;
1028 setf.sig f9=r9 // certain to stall, so issue it _after_ ldf8...
1029 ;;
1030 xmpy.lu f10=f9,f8 // calculate low 64 bits of 128-bit product (4 cyc)
1031 xmpy.hu f11=f9,f8 // calculate high 64 bits of 128-bit product
1032 ;;
1033 getf.sig r8=f10 // (5 cyc)
1034 getf.sig r9=f11
1035 ;;
1036 shrp r8=r9,r8,IA64_NSEC_PER_CYC_SHIFT
1037 br.ret.sptk.many rp
1038 END(sched_clock)
1040 GLOBAL_ENTRY(start_kernel_thread)
1041 .prologue
1042 .save rp, r0 // this is the end of the call-chain
1043 .body
1044 alloc r2 = ar.pfs, 0, 0, 2, 0
1045 mov out0 = r9
1046 mov out1 = r11;;
1047 br.call.sptk.many rp = kernel_thread_helper;;
1048 mov out0 = r8
1049 br.call.sptk.many rp = sys_exit;;
1050 1: br.sptk.few 1b // not reached
1051 END(start_kernel_thread)
1052 #endif /* XEN */
1054 #ifdef CONFIG_IA64_BRL_EMU
1056 /*
1057 * Assembly routines used by brl_emu.c to set preserved register state.
1058 */
1060 #define SET_REG(reg) \
1061 GLOBAL_ENTRY(ia64_set_##reg); \
1062 alloc r16=ar.pfs,1,0,0,0; \
1063 mov reg=r32; \
1064 ;; \
1065 br.ret.sptk.many rp; \
1066 END(ia64_set_##reg)
1068 SET_REG(b1);
1069 SET_REG(b2);
1070 SET_REG(b3);
1071 SET_REG(b4);
1072 SET_REG(b5);
1074 #endif /* CONFIG_IA64_BRL_EMU */
1076 #ifdef CONFIG_SMP
1077 /*
1078 * This routine handles spinlock contention. It uses a non-standard calling
1079 * convention to avoid converting leaf routines into interior routines. Because
1080 * of this special convention, there are several restrictions:
1082 * - do not use gp relative variables, this code is called from the kernel
1083 * and from modules, r1 is undefined.
1084 * - do not use stacked registers, the caller owns them.
1085 * - do not use the scratch stack space, the caller owns it.
1086 * - do not use any registers other than the ones listed below
1088 * Inputs:
1089 * ar.pfs - saved CFM of caller
1090 * ar.ccv - 0 (and available for use)
1091 * r27 - flags from spin_lock_irqsave or 0. Must be preserved.
1092 * r28 - available for use.
1093 * r29 - available for use.
1094 * r30 - available for use.
1095 * r31 - address of lock, available for use.
1096 * b6 - return address
1097 * p14 - available for use.
1098 * p15 - used to track flag status.
1100 * If you patch this code to use more registers, do not forget to update
1101 * the clobber lists for spin_lock() in include/asm-ia64/spinlock.h.
1102 */
1104 #if __GNUC__ < 3 || (__GNUC__ == 3 && __GNUC_MINOR__ < 3)
1106 GLOBAL_ENTRY(ia64_spinlock_contention_pre3_4)
1107 .prologue
1108 .save ar.pfs, r0 // this code effectively has a zero frame size
1109 .save rp, r28
1110 .body
1111 nop 0
1112 tbit.nz p15,p0=r27,IA64_PSR_I_BIT
1113 .restore sp // pop existing prologue after next insn
1114 mov b6 = r28
1115 .prologue
1116 .save ar.pfs, r0
1117 .altrp b6
1118 .body
1119 ;;
1120 (p15) ssm psr.i // reenable interrupts if they were on
1121 // DavidM says that srlz.d is slow and is not required in this case
1122 .wait:
1123 // exponential backoff, kdb, lockmeter etc. go in here
1124 hint @pause
1125 ld4 r30=[r31] // don't use ld4.bias; if it's contended, we won't write the word
1126 nop 0
1127 ;;
1128 cmp4.ne p14,p0=r30,r0
1129 (p14) br.cond.sptk.few .wait
1130 (p15) rsm psr.i // disable interrupts if we reenabled them
1131 br.cond.sptk.few b6 // lock is now free, try to acquire
1132 .global ia64_spinlock_contention_pre3_4_end // for kernprof
1133 ia64_spinlock_contention_pre3_4_end:
1134 END(ia64_spinlock_contention_pre3_4)
1136 #else
1138 GLOBAL_ENTRY(ia64_spinlock_contention)
1139 .prologue
1140 .altrp b6
1141 .body
1142 tbit.nz p15,p0=r27,IA64_PSR_I_BIT
1143 ;;
1144 .wait:
1145 (p15) ssm psr.i // reenable interrupts if they were on
1146 // DavidM says that srlz.d is slow and is not required in this case
1147 .wait2:
1148 // exponential backoff, kdb, lockmeter etc. go in here
1149 hint @pause
1150 ld4 r30=[r31] // don't use ld4.bias; if it's contended, we won't write the word
1151 ;;
1152 cmp4.ne p14,p0=r30,r0
1153 mov r30 = 1
1154 (p14) br.cond.sptk.few .wait2
1155 (p15) rsm psr.i // disable interrupts if we reenabled them
1156 ;;
1157 cmpxchg4.acq r30=[r31], r30, ar.ccv
1158 ;;
1159 cmp4.ne p14,p0=r0,r30
1160 (p14) br.cond.sptk.few .wait
1162 br.ret.sptk.many b6 // lock is now taken
1163 END(ia64_spinlock_contention)
1165 #endif
1167 #ifdef CONFIG_HOTPLUG_CPU
1168 GLOBAL_ENTRY(ia64_jump_to_sal)
1169 alloc r16=ar.pfs,1,0,0,0;;
1170 rsm psr.i | psr.ic
1172 flushrs
1173 srlz.i
1175 tpa r25=in0
1176 movl r18=tlb_purge_done;;
1177 DATA_VA_TO_PA(r18);;
1178 mov b1=r18 // Return location
1179 movl r18=ia64_do_tlb_purge;;
1180 DATA_VA_TO_PA(r18);;
1181 mov b2=r18 // doing tlb_flush work
1182 mov ar.rsc=0 // Put RSE in enforced lazy, LE mode
1183 movl r17=1f;;
1184 DATA_VA_TO_PA(r17);;
1185 mov cr.iip=r17
1186 movl r16=SAL_PSR_BITS_TO_SET;;
1187 mov cr.ipsr=r16
1188 mov cr.ifs=r0;;
1189 rfi;;
1190 1:
1191 /*
1192 * Invalidate all TLB data/inst
1193 */
1194 br.sptk.many b2;; // jump to tlb purge code
1196 tlb_purge_done:
1197 RESTORE_REGION_REGS(r25, r17,r18,r19);;
1198 RESTORE_REG(b0, r25, r17);;
1199 RESTORE_REG(b1, r25, r17);;
1200 RESTORE_REG(b2, r25, r17);;
1201 RESTORE_REG(b3, r25, r17);;
1202 RESTORE_REG(b4, r25, r17);;
1203 RESTORE_REG(b5, r25, r17);;
1204 ld8 r1=[r25],0x08;;
1205 ld8 r12=[r25],0x08;;
1206 ld8 r13=[r25],0x08;;
1207 RESTORE_REG(ar.fpsr, r25, r17);;
1208 RESTORE_REG(ar.pfs, r25, r17);;
1209 RESTORE_REG(ar.rnat, r25, r17);;
1210 RESTORE_REG(ar.unat, r25, r17);;
1211 RESTORE_REG(ar.bspstore, r25, r17);;
1212 RESTORE_REG(cr.dcr, r25, r17);;
1213 RESTORE_REG(cr.iva, r25, r17);;
1214 RESTORE_REG(cr.pta, r25, r17);;
1215 #ifdef XEN
1216 dv_serialize_instruction
1217 #endif
1218 RESTORE_REG(cr.itv, r25, r17);;
1219 RESTORE_REG(cr.pmv, r25, r17);;
1220 RESTORE_REG(cr.cmcv, r25, r17);;
1221 RESTORE_REG(cr.lrr0, r25, r17);;
1222 RESTORE_REG(cr.lrr1, r25, r17);;
1223 ld8 r4=[r25],0x08;;
1224 ld8 r5=[r25],0x08;;
1225 ld8 r6=[r25],0x08;;
1226 ld8 r7=[r25],0x08;;
1227 ld8 r17=[r25],0x08;;
1228 mov pr=r17,-1;;
1229 RESTORE_REG(ar.lc, r25, r17);;
1230 /*
1231 * Now Restore floating point regs
1232 */
1233 ldf.fill.nta f2=[r25],16;;
1234 ldf.fill.nta f3=[r25],16;;
1235 ldf.fill.nta f4=[r25],16;;
1236 ldf.fill.nta f5=[r25],16;;
1237 ldf.fill.nta f16=[r25],16;;
1238 ldf.fill.nta f17=[r25],16;;
1239 ldf.fill.nta f18=[r25],16;;
1240 ldf.fill.nta f19=[r25],16;;
1241 ldf.fill.nta f20=[r25],16;;
1242 ldf.fill.nta f21=[r25],16;;
1243 ldf.fill.nta f22=[r25],16;;
1244 ldf.fill.nta f23=[r25],16;;
1245 ldf.fill.nta f24=[r25],16;;
1246 ldf.fill.nta f25=[r25],16;;
1247 ldf.fill.nta f26=[r25],16;;
1248 ldf.fill.nta f27=[r25],16;;
1249 ldf.fill.nta f28=[r25],16;;
1250 ldf.fill.nta f29=[r25],16;;
1251 ldf.fill.nta f30=[r25],16;;
1252 ldf.fill.nta f31=[r25],16;;
1254 /*
1255 * Now that we have done all the register restores
1256 * we are now ready for the big DIVE to SAL Land
1257 */
1258 ssm psr.ic;;
1259 srlz.d;;
1260 br.ret.sptk.many b0;;
1261 END(ia64_jump_to_sal)
1262 #endif /* CONFIG_HOTPLUG_CPU */
1264 #endif /* CONFIG_SMP */