ia64/xen-unstable

view xen/include/asm-ia64/xenkregs.h @ 16773:ac296153ea64

[IA64] Rearrange IA64_TR_ definitions to use from lower value

SDM vol2 4.1.1.1 says that:
"software should allocate contiguous translation registers starting
at slot 0 and continuing upwards."

Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
author Alex Williamson <alex.williamson@hp.com>
date Thu Jan 17 12:05:43 2008 -0700 (2008-01-17)
parents c17bfb091790
children 6f7e6608cb74
line source
1 #ifndef _ASM_IA64_XENKREGS_H
2 #define _ASM_IA64_XENKREGS_H
4 /*
5 * Translation registers:
6 */
7 #define IA64_TR_XEN_HEAP_REGS 3 /* dtr3: xen heap identity mapped regs */
8 #define IA64_TR_SHARED_INFO 4 /* dtr4: page shared with domain */
9 #define IA64_TR_MAPPED_REGS 5 /* dtr5: vcpu mapped regs */
10 #define IA64_TR_VHPT 6 /* dtr6: vhpt */
12 #define IA64_DTR_GUEST_KERNEL 7
13 #define IA64_ITR_GUEST_KERNEL 2
14 /* Processor status register bits: */
15 #define IA64_PSR_VM_BIT 46
16 #define IA64_PSR_VM (__IA64_UL(1) << IA64_PSR_VM_BIT)
18 #define IA64_DEFAULT_DCR_BITS (IA64_DCR_PP | IA64_DCR_LC | IA64_DCR_DM | \
19 IA64_DCR_DP | IA64_DCR_DK | IA64_DCR_DX | \
20 IA64_DCR_DR | IA64_DCR_DA | IA64_DCR_DD)
22 // note IA64_PSR_PK removed from following, why is this necessary?
23 #define DELIVER_PSR_SET (IA64_PSR_IC | IA64_PSR_I | \
24 IA64_PSR_DT | IA64_PSR_RT | \
25 IA64_PSR_IT | IA64_PSR_BN)
27 #define DELIVER_PSR_CLR (IA64_PSR_AC | IA64_PSR_DFL| IA64_PSR_DFH| \
28 IA64_PSR_SP | IA64_PSR_DI | IA64_PSR_SI | \
29 IA64_PSR_DB | IA64_PSR_LP | IA64_PSR_TB | \
30 IA64_PSR_CPL| IA64_PSR_MC | IA64_PSR_IS | \
31 IA64_PSR_ID | IA64_PSR_DA | IA64_PSR_DD | \
32 IA64_PSR_SS | IA64_PSR_RI | IA64_PSR_ED | IA64_PSR_IA)
34 // NO PSR_CLR IS DIFFERENT! (CPL)
35 #define IA64_PSR_CPL1 (__IA64_UL(1) << IA64_PSR_CPL1_BIT)
36 #define IA64_PSR_CPL0 (__IA64_UL(1) << IA64_PSR_CPL0_BIT)
38 /* Interruption Function State */
39 #define IA64_IFS_V_BIT 63
40 #define IA64_IFS_V (__IA64_UL(1) << IA64_IFS_V_BIT)
42 /* Interruption Status Register. */
43 #define IA64_ISR_NI_BIT 39 /* Nested interrupt. */
45 /* Page Table Address */
46 #define IA64_PTA_VE_BIT 0
47 #define IA64_PTA_SIZE_BIT 2
48 #define IA64_PTA_SIZE_LEN 6
49 #define IA64_PTA_VF_BIT 8
50 #define IA64_PTA_BASE_BIT 15
52 #define IA64_PTA_VE (__IA64_UL(1) << IA64_PTA_VE_BIT)
53 #define IA64_PTA_SIZE (__IA64_UL((1 << IA64_PTA_SIZE_LEN) - 1) << \
54 IA64_PTA_SIZE_BIT)
55 #define IA64_PTA_VF (__IA64_UL(1) << IA64_PTA_VF_BIT)
56 #define IA64_PTA_BASE (__IA64_UL(0) - ((__IA64_UL(1) << IA64_PTA_BASE_BIT)))
58 /* Some cr.itir declarations. */
59 #define IA64_ITIR_PS 2
60 #define IA64_ITIR_PS_LEN 6
61 #define IA64_ITIR_PS_MASK (((__IA64_UL(1) << IA64_ITIR_PS_LEN) - 1) \
62 << IA64_ITIR_PS)
63 #define IA64_ITIR_KEY 8
64 #define IA64_ITIR_KEY_LEN 24
65 #define IA64_ITIR_KEY_MASK (((__IA64_UL(1) << IA64_ITIR_KEY_LEN) - 1) \
66 << IA64_ITIR_KEY)
67 #define IA64_ITIR_PS_KEY(_ps, _key) (((_ps) << IA64_ITIR_PS) | \
68 (((_key) << IA64_ITIR_KEY)))
70 /* Region Register Bits */
71 #define IA64_RR_PS 2
72 #define IA64_RR_PS_LEN 6
73 #define IA64_RR_RID 8
74 #define IA64_RR_RID_LEN 24
75 #define IA64_RR_RID_MASK (((__IA64_UL(1) << IA64_RR_RID_LEN) - 1) << \
76 IA64_RR_RID
78 /* Define Protection Key Register (PKR) */
79 #define IA64_PKR_V 0
80 #define IA64_PKR_WD 1
81 #define IA64_PKR_RD 2
82 #define IA64_PKR_XD 3
83 #define IA64_PKR_MBZ0 4
84 #define IA64_PKR_KEY 8
85 #define IA64_PKR_KEY_LEN 24
86 #define IA64_PKR_MBZ1 32
88 #define IA64_PKR_VALID (1 << IA64_PKR_V)
89 #define IA64_PKR_KEY_MASK (((__IA64_UL(1) << IA64_PKR_KEY_LEN) - 1) \
90 << IA64_PKR_KEY)
92 #define XEN_IA64_NPKRS 15 /* Number of pkr's in PV */
94 /* A pkr val for the hypervisor: key = 0, valid = 1. */
95 #define XEN_IA64_PKR_VAL ((0 << IA64_PKR_KEY) | IA64_PKR_VALID)
97 #endif /* _ASM_IA64_XENKREGS_H */