ia64/xen-unstable

view xen/arch/ia64/xen/vcpu.c @ 14070:ac28d6c41e6f

[IA64] Remove unused code

In vcpu_set_psr_l, psr is set but never read. This dead code is removed.

Signed-off-by: Tristan Gingold <tgingold@free.fr>
author awilliam@xenbuild2.aw
date Wed Feb 28 09:43:09 2007 -0700 (2007-02-28)
parents 9364bea18bc4
children ea0b50ca4999
line source
1 /*
2 * Virtualized CPU functions
3 *
4 * Copyright (C) 2004-2005 Hewlett-Packard Co.
5 * Dan Magenheimer (dan.magenheimer@hp.com)
6 *
7 */
9 #include <linux/sched.h>
10 #include <public/xen.h>
11 #include <xen/mm.h>
12 #include <asm/ia64_int.h>
13 #include <asm/vcpu.h>
14 #include <asm/regionreg.h>
15 #include <asm/tlb.h>
16 #include <asm/processor.h>
17 #include <asm/delay.h>
18 #include <asm/vmx_vcpu.h>
19 #include <asm/vhpt.h>
20 #include <asm/tlbflush.h>
21 #include <asm/privop.h>
22 #include <xen/event.h>
23 #include <asm/vmx_phy_mode.h>
24 #include <asm/bundle.h>
25 #include <asm/privop_stat.h>
26 #include <asm/uaccess.h>
27 #include <asm/p2m_entry.h>
28 #include <asm/tlb_track.h>
30 /* FIXME: where these declarations should be there ? */
31 extern void getreg(unsigned long regnum, unsigned long *val, int *nat,
32 struct pt_regs *regs);
33 extern void setreg(unsigned long regnum, unsigned long val, int nat,
34 struct pt_regs *regs);
35 extern void getfpreg(unsigned long regnum, struct ia64_fpreg *fpval,
36 struct pt_regs *regs);
38 extern void setfpreg(unsigned long regnum, struct ia64_fpreg *fpval,
39 struct pt_regs *regs);
41 typedef union {
42 struct ia64_psr ia64_psr;
43 unsigned long i64;
44 } PSR;
46 // this def for vcpu_regs won't work if kernel stack is present
47 //#define vcpu_regs(vcpu) ((struct pt_regs *) vcpu->arch.regs
49 #define IA64_PTA_SZ_BIT 2
50 #define IA64_PTA_VF_BIT 8
51 #define IA64_PTA_BASE_BIT 15
52 #define IA64_PTA_LFMT (1UL << IA64_PTA_VF_BIT)
53 #define IA64_PTA_SZ(x) (x##UL << IA64_PTA_SZ_BIT)
55 unsigned long vcpu_verbose = 0;
57 /**************************************************************************
58 VCPU general register access routines
59 **************************************************************************/
60 #ifdef XEN
61 u64 vcpu_get_gr(VCPU * vcpu, unsigned long reg)
62 {
63 REGS *regs = vcpu_regs(vcpu);
64 u64 val;
66 if (!reg)
67 return 0;
68 getreg(reg, &val, 0, regs); // FIXME: handle NATs later
69 return val;
70 }
72 IA64FAULT vcpu_get_gr_nat(VCPU * vcpu, unsigned long reg, u64 * val)
73 {
74 REGS *regs = vcpu_regs(vcpu);
75 int nat;
77 getreg(reg, val, &nat, regs); // FIXME: handle NATs later
78 if (nat)
79 return IA64_NAT_CONSUMPTION_VECTOR;
80 return 0;
81 }
83 // returns:
84 // IA64_ILLOP_FAULT if the register would cause an Illegal Operation fault
85 // IA64_NO_FAULT otherwise
86 IA64FAULT vcpu_set_gr(VCPU * vcpu, unsigned long reg, u64 value, int nat)
87 {
88 REGS *regs = vcpu_regs(vcpu);
89 long sof = (regs->cr_ifs) & 0x7f;
91 if (!reg)
92 return IA64_ILLOP_FAULT;
93 if (reg >= sof + 32)
94 return IA64_ILLOP_FAULT;
95 setreg(reg, value, nat, regs); // FIXME: handle NATs later
96 return IA64_NO_FAULT;
97 }
99 IA64FAULT
100 vcpu_get_fpreg(VCPU * vcpu, unsigned long reg, struct ia64_fpreg * val)
101 {
102 REGS *regs = vcpu_regs(vcpu);
103 getfpreg(reg, val, regs); // FIXME: handle NATs later
104 return IA64_NO_FAULT;
105 }
107 IA64FAULT
108 vcpu_set_fpreg(VCPU * vcpu, unsigned long reg, struct ia64_fpreg * val)
109 {
110 REGS *regs = vcpu_regs(vcpu);
111 if (reg > 1)
112 setfpreg(reg, val, regs); // FIXME: handle NATs later
113 return IA64_NO_FAULT;
114 }
116 #else
117 // returns:
118 // IA64_ILLOP_FAULT if the register would cause an Illegal Operation fault
119 // IA64_NO_FAULT otherwise
120 IA64FAULT vcpu_set_gr(VCPU * vcpu, unsigned long reg, u64 value)
121 {
122 REGS *regs = vcpu_regs(vcpu);
123 long sof = (regs->cr_ifs) & 0x7f;
125 if (!reg)
126 return IA64_ILLOP_FAULT;
127 if (reg >= sof + 32)
128 return IA64_ILLOP_FAULT;
129 setreg(reg, value, 0, regs); // FIXME: handle NATs later
130 return IA64_NO_FAULT;
131 }
133 #endif
135 void vcpu_init_regs(struct vcpu *v)
136 {
137 struct pt_regs *regs;
139 regs = vcpu_regs(v);
140 if (VMX_DOMAIN(v)) {
141 /* dt/rt/it:1;i/ic:1, si:1, vm/bn:1, ac:1 */
142 /* Need to be expanded as macro */
143 regs->cr_ipsr = 0x501008826008;
144 /* lazy fp */
145 FP_PSR(v) = IA64_PSR_DFH;
146 regs->cr_ipsr |= IA64_PSR_DFH;
147 } else {
148 regs->cr_ipsr = ia64_getreg(_IA64_REG_PSR)
149 | IA64_PSR_BITS_TO_SET | IA64_PSR_BN;
150 regs->cr_ipsr &= ~(IA64_PSR_BITS_TO_CLEAR
151 | IA64_PSR_RI | IA64_PSR_IS);
152 // domain runs at PL2
153 regs->cr_ipsr |= 2UL << IA64_PSR_CPL0_BIT;
154 // lazy fp
155 PSCB(v, hpsr_dfh) = 1;
156 PSCB(v, hpsr_mfh) = 0;
157 regs->cr_ipsr |= IA64_PSR_DFH;
158 }
159 regs->cr_ifs = 1UL << 63; /* or clear? */
160 regs->ar_fpsr = FPSR_DEFAULT;
162 if (VMX_DOMAIN(v)) {
163 vmx_init_all_rr(v);
164 /* Virtual processor context setup */
165 VCPU(v, vpsr) = IA64_PSR_BN;
166 VCPU(v, dcr) = 0;
167 } else {
168 init_all_rr(v);
169 regs->ar_rsc |= (2 << 2); /* force PL2/3 */
170 VCPU(v, banknum) = 1;
171 VCPU(v, metaphysical_mode) = 1;
172 VCPU(v, interrupt_mask_addr) =
173 (unsigned char *)v->domain->arch.shared_info_va +
174 INT_ENABLE_OFFSET(v);
175 VCPU(v, itv) = (1 << 16); /* timer vector masked */
176 }
178 v->arch.domain_itm_last = -1L;
179 }
181 /**************************************************************************
182 VCPU privileged application register access routines
183 **************************************************************************/
185 void vcpu_load_kernel_regs(VCPU * vcpu)
186 {
187 ia64_set_kr(0, VCPU(vcpu, krs[0]));
188 ia64_set_kr(1, VCPU(vcpu, krs[1]));
189 ia64_set_kr(2, VCPU(vcpu, krs[2]));
190 ia64_set_kr(3, VCPU(vcpu, krs[3]));
191 ia64_set_kr(4, VCPU(vcpu, krs[4]));
192 ia64_set_kr(5, VCPU(vcpu, krs[5]));
193 ia64_set_kr(6, VCPU(vcpu, krs[6]));
194 ia64_set_kr(7, VCPU(vcpu, krs[7]));
195 }
197 /* GCC 4.0.2 seems not to be able to suppress this call!. */
198 #define ia64_setreg_unknown_kr() return IA64_ILLOP_FAULT
200 IA64FAULT vcpu_set_ar(VCPU * vcpu, u64 reg, u64 val)
201 {
202 if (reg == 44)
203 return vcpu_set_itc(vcpu, val);
204 else if (reg == 27)
205 return IA64_ILLOP_FAULT;
206 else if (reg == 24)
207 printk("warning: setting ar.eflg is a no-op; no IA-32 "
208 "support\n");
209 else if (reg > 7)
210 return IA64_ILLOP_FAULT;
211 else {
212 PSCB(vcpu, krs[reg]) = val;
213 ia64_set_kr(reg, val);
214 }
215 return IA64_NO_FAULT;
216 }
218 IA64FAULT vcpu_get_ar(VCPU * vcpu, u64 reg, u64 * val)
219 {
220 if (reg == 24)
221 printk("warning: getting ar.eflg is a no-op; no IA-32 "
222 "support\n");
223 else if (reg > 7)
224 return IA64_ILLOP_FAULT;
225 else
226 *val = PSCB(vcpu, krs[reg]);
227 return IA64_NO_FAULT;
228 }
230 /**************************************************************************
231 VCPU processor status register access routines
232 **************************************************************************/
234 void vcpu_set_metaphysical_mode(VCPU * vcpu, BOOLEAN newmode)
235 {
236 /* only do something if mode changes */
237 if (!!newmode ^ !!PSCB(vcpu, metaphysical_mode)) {
238 PSCB(vcpu, metaphysical_mode) = newmode;
239 if (newmode)
240 set_metaphysical_rr0();
241 else if (PSCB(vcpu, rrs[0]) != -1)
242 set_one_rr(0, PSCB(vcpu, rrs[0]));
243 }
244 }
246 IA64FAULT vcpu_reset_psr_dt(VCPU * vcpu)
247 {
248 vcpu_set_metaphysical_mode(vcpu, TRUE);
249 return IA64_NO_FAULT;
250 }
252 IA64FAULT vcpu_reset_psr_sm(VCPU * vcpu, u64 imm24)
253 {
254 struct ia64_psr psr, imm, *ipsr;
255 REGS *regs = vcpu_regs(vcpu);
257 //PRIVOP_COUNT_ADDR(regs,_RSM);
258 // TODO: All of these bits need to be virtualized
259 // TODO: Only allowed for current vcpu
260 __asm__ __volatile("mov %0=psr;;":"=r"(psr)::"memory");
261 ipsr = (struct ia64_psr *)&regs->cr_ipsr;
262 imm = *(struct ia64_psr *)&imm24;
263 // interrupt flag
264 if (imm.i)
265 vcpu->vcpu_info->evtchn_upcall_mask = 1;
266 if (imm.ic)
267 PSCB(vcpu, interrupt_collection_enabled) = 0;
268 // interrupt collection flag
269 //if (imm.ic) PSCB(vcpu,interrupt_delivery_enabled) = 0;
270 // just handle psr.up and psr.pp for now
271 if (imm24 & ~(IA64_PSR_BE | IA64_PSR_PP | IA64_PSR_UP | IA64_PSR_SP |
272 IA64_PSR_I | IA64_PSR_IC | IA64_PSR_DT |
273 IA64_PSR_DFL | IA64_PSR_DFH))
274 return IA64_ILLOP_FAULT;
275 if (imm.dfh) {
276 ipsr->dfh = PSCB(vcpu, hpsr_dfh);
277 PSCB(vcpu, vpsr_dfh) = 0;
278 }
279 if (imm.dfl)
280 ipsr->dfl = 0;
281 if (imm.pp) {
282 ipsr->pp = 1;
283 psr.pp = 1; // priv perf ctrs always enabled
284 PSCB(vcpu, vpsr_pp) = 0; // but fool the domain if it gets psr
285 }
286 if (imm.up) {
287 ipsr->up = 0;
288 psr.up = 0;
289 }
290 if (imm.sp) {
291 ipsr->sp = 0;
292 psr.sp = 0;
293 }
294 if (imm.be)
295 ipsr->be = 0;
296 if (imm.dt)
297 vcpu_set_metaphysical_mode(vcpu, TRUE);
298 __asm__ __volatile(";; mov psr.l=%0;; srlz.d"::"r"(psr):"memory");
299 return IA64_NO_FAULT;
300 }
302 IA64FAULT vcpu_set_psr_dt(VCPU * vcpu)
303 {
304 vcpu_set_metaphysical_mode(vcpu, FALSE);
305 return IA64_NO_FAULT;
306 }
308 IA64FAULT vcpu_set_psr_i(VCPU * vcpu)
309 {
310 vcpu->vcpu_info->evtchn_upcall_mask = 0;
311 PSCB(vcpu, interrupt_collection_enabled) = 1;
312 return IA64_NO_FAULT;
313 }
315 IA64FAULT vcpu_set_psr_sm(VCPU * vcpu, u64 imm24)
316 {
317 struct ia64_psr psr, imm, *ipsr;
318 REGS *regs = vcpu_regs(vcpu);
319 u64 mask, enabling_interrupts = 0;
321 //PRIVOP_COUNT_ADDR(regs,_SSM);
322 // TODO: All of these bits need to be virtualized
323 __asm__ __volatile("mov %0=psr;;":"=r"(psr)::"memory");
324 imm = *(struct ia64_psr *)&imm24;
325 ipsr = (struct ia64_psr *)&regs->cr_ipsr;
326 // just handle psr.sp,pp and psr.i,ic (and user mask) for now
327 mask =
328 IA64_PSR_PP | IA64_PSR_SP | IA64_PSR_I | IA64_PSR_IC | IA64_PSR_UM |
329 IA64_PSR_DT | IA64_PSR_DFL | IA64_PSR_DFH | IA64_PSR_BE;
330 if (imm24 & ~mask)
331 return IA64_ILLOP_FAULT;
332 if (imm.dfh) {
333 PSCB(vcpu, vpsr_dfh) = 1;
334 ipsr->dfh = 1;
335 }
336 if (imm.dfl)
337 ipsr->dfl = 1;
338 if (imm.pp) {
339 ipsr->pp = 1;
340 psr.pp = 1;
341 PSCB(vcpu, vpsr_pp) = 1;
342 }
343 if (imm.sp) {
344 ipsr->sp = 1;
345 psr.sp = 1;
346 }
347 if (imm.i) {
348 if (vcpu->vcpu_info->evtchn_upcall_mask) {
349 //printk("vcpu_set_psr_sm: psr.ic 0->1\n");
350 enabling_interrupts = 1;
351 }
352 vcpu->vcpu_info->evtchn_upcall_mask = 0;
353 }
354 if (imm.ic)
355 PSCB(vcpu, interrupt_collection_enabled) = 1;
356 // TODO: do this faster
357 if (imm.mfl) {
358 ipsr->mfl = 1;
359 psr.mfl = 1;
360 }
361 if (imm.mfh) {
362 ipsr->mfh = 1;
363 psr.mfh = 1;
364 }
365 if (imm.ac) {
366 ipsr->ac = 1;
367 psr.ac = 1;
368 }
369 if (imm.up) {
370 ipsr->up = 1;
371 psr.up = 1;
372 }
373 if (imm.be)
374 ipsr->be = 1;
375 if (imm.dt)
376 vcpu_set_metaphysical_mode(vcpu, FALSE);
377 __asm__ __volatile(";; mov psr.l=%0;; srlz.d"::"r"(psr):"memory");
378 if (enabling_interrupts &&
379 vcpu_check_pending_interrupts(vcpu) != SPURIOUS_VECTOR)
380 PSCB(vcpu, pending_interruption) = 1;
381 return IA64_NO_FAULT;
382 }
384 IA64FAULT vcpu_set_psr_l(VCPU * vcpu, u64 val)
385 {
386 struct ia64_psr newpsr, *ipsr;
387 REGS *regs = vcpu_regs(vcpu);
388 u64 enabling_interrupts = 0;
390 newpsr = *(struct ia64_psr *)&val;
391 ipsr = (struct ia64_psr *)&regs->cr_ipsr;
392 // just handle psr.up and psr.pp for now
393 //if (val & ~(IA64_PSR_PP | IA64_PSR_UP | IA64_PSR_SP))
394 // return IA64_ILLOP_FAULT;
395 // however trying to set other bits can't be an error as it is in ssm
396 if (newpsr.dfh) {
397 ipsr->dfh = 1;
398 PSCB(vcpu, vpsr_dfh) = 1;
399 } else {
400 ipsr->dfh = PSCB(vcpu, hpsr_dfh);
401 PSCB(vcpu, vpsr_dfh) = 0;
402 }
403 if (newpsr.dfl)
404 ipsr->dfl = 1;
405 if (newpsr.pp) {
406 ipsr->pp = 1;
407 PSCB(vcpu, vpsr_pp) = 1;
408 } else {
409 ipsr->pp = 1;
410 PSCB(vcpu, vpsr_pp) = 0;
411 }
412 if (newpsr.up)
413 ipsr->up = 1;
414 if (newpsr.sp)
415 ipsr->sp = 1;
416 if (newpsr.i) {
417 if (vcpu->vcpu_info->evtchn_upcall_mask)
418 enabling_interrupts = 1;
419 vcpu->vcpu_info->evtchn_upcall_mask = 0;
420 }
421 if (newpsr.ic)
422 PSCB(vcpu, interrupt_collection_enabled) = 1;
423 if (newpsr.mfl)
424 ipsr->mfl = 1;
425 if (newpsr.mfh)
426 ipsr->mfh = 1;
427 if (newpsr.ac)
428 ipsr->ac = 1;
429 if (newpsr.up)
430 ipsr->up = 1;
431 if (newpsr.dt && newpsr.rt)
432 vcpu_set_metaphysical_mode(vcpu, FALSE);
433 else
434 vcpu_set_metaphysical_mode(vcpu, TRUE);
435 if (newpsr.be)
436 ipsr->be = 1;
437 if (enabling_interrupts &&
438 vcpu_check_pending_interrupts(vcpu) != SPURIOUS_VECTOR)
439 PSCB(vcpu, pending_interruption) = 1;
440 return IA64_NO_FAULT;
441 }
443 IA64FAULT vcpu_get_psr(VCPU * vcpu, u64 * pval)
444 {
445 REGS *regs = vcpu_regs(vcpu);
446 struct ia64_psr newpsr;
448 newpsr = *(struct ia64_psr *)&regs->cr_ipsr;
449 if (!vcpu->vcpu_info->evtchn_upcall_mask)
450 newpsr.i = 1;
451 else
452 newpsr.i = 0;
453 if (PSCB(vcpu, interrupt_collection_enabled))
454 newpsr.ic = 1;
455 else
456 newpsr.ic = 0;
457 if (PSCB(vcpu, metaphysical_mode))
458 newpsr.dt = 0;
459 else
460 newpsr.dt = 1;
461 if (PSCB(vcpu, vpsr_pp))
462 newpsr.pp = 1;
463 else
464 newpsr.pp = 0;
465 newpsr.dfh = PSCB(vcpu, vpsr_dfh);
467 *pval = *(unsigned long *)&newpsr;
468 *pval &= (MASK(0, 32) | MASK(35, 2));
469 return IA64_NO_FAULT;
470 }
472 BOOLEAN vcpu_get_psr_ic(VCPU * vcpu)
473 {
474 return !!PSCB(vcpu, interrupt_collection_enabled);
475 }
477 BOOLEAN vcpu_get_psr_i(VCPU * vcpu)
478 {
479 return !vcpu->vcpu_info->evtchn_upcall_mask;
480 }
482 u64 vcpu_get_ipsr_int_state(VCPU * vcpu, u64 prevpsr)
483 {
484 u64 dcr = PSCB(vcpu, dcr);
485 PSR psr;
487 //printk("*** vcpu_get_ipsr_int_state (0x%016lx)...\n",prevpsr);
488 psr.i64 = prevpsr;
489 psr.ia64_psr.pp = 0;
490 if (dcr & IA64_DCR_PP)
491 psr.ia64_psr.pp = 1;
492 psr.ia64_psr.ic = PSCB(vcpu, interrupt_collection_enabled);
493 psr.ia64_psr.i = !vcpu->vcpu_info->evtchn_upcall_mask;
494 psr.ia64_psr.bn = PSCB(vcpu, banknum);
495 psr.ia64_psr.dfh = PSCB(vcpu, vpsr_dfh);
496 psr.ia64_psr.dt = 1;
497 psr.ia64_psr.it = 1;
498 psr.ia64_psr.rt = 1;
499 if (psr.ia64_psr.cpl == 2)
500 psr.ia64_psr.cpl = 0; // !!!! fool domain
501 // psr.pk = 1;
502 //printk("returns 0x%016lx...\n",psr.i64);
503 return psr.i64;
504 }
506 /**************************************************************************
507 VCPU control register access routines
508 **************************************************************************/
510 IA64FAULT vcpu_get_dcr(VCPU * vcpu, u64 * pval)
511 {
512 *pval = PSCB(vcpu, dcr);
513 return IA64_NO_FAULT;
514 }
516 IA64FAULT vcpu_get_iva(VCPU * vcpu, u64 * pval)
517 {
518 if (VMX_DOMAIN(vcpu))
519 *pval = PSCB(vcpu, iva) & ~0x7fffL;
520 else
521 *pval = PSCBX(vcpu, iva) & ~0x7fffL;
523 return IA64_NO_FAULT;
524 }
526 IA64FAULT vcpu_get_pta(VCPU * vcpu, u64 * pval)
527 {
528 *pval = PSCB(vcpu, pta);
529 return IA64_NO_FAULT;
530 }
532 IA64FAULT vcpu_get_ipsr(VCPU * vcpu, u64 * pval)
533 {
534 //REGS *regs = vcpu_regs(vcpu);
535 //*pval = regs->cr_ipsr;
536 *pval = PSCB(vcpu, ipsr);
537 return IA64_NO_FAULT;
538 }
540 IA64FAULT vcpu_get_isr(VCPU * vcpu, u64 * pval)
541 {
542 *pval = PSCB(vcpu, isr);
543 return IA64_NO_FAULT;
544 }
546 IA64FAULT vcpu_get_iip(VCPU * vcpu, u64 * pval)
547 {
548 //REGS *regs = vcpu_regs(vcpu);
549 //*pval = regs->cr_iip;
550 *pval = PSCB(vcpu, iip);
551 return IA64_NO_FAULT;
552 }
554 IA64FAULT vcpu_get_ifa(VCPU * vcpu, u64 * pval)
555 {
556 PRIVOP_COUNT_ADDR(vcpu_regs(vcpu), privop_inst_get_ifa);
557 *pval = PSCB(vcpu, ifa);
558 return IA64_NO_FAULT;
559 }
561 unsigned long vcpu_get_rr_ps(VCPU * vcpu, u64 vadr)
562 {
563 ia64_rr rr;
565 rr.rrval = PSCB(vcpu, rrs)[vadr >> 61];
566 return rr.ps;
567 }
569 unsigned long vcpu_get_rr_rid(VCPU * vcpu, u64 vadr)
570 {
571 ia64_rr rr;
573 rr.rrval = PSCB(vcpu, rrs)[vadr >> 61];
574 return rr.rid;
575 }
577 unsigned long vcpu_get_itir_on_fault(VCPU * vcpu, u64 ifa)
578 {
579 ia64_rr rr;
581 rr.rrval = 0;
582 rr.ps = vcpu_get_rr_ps(vcpu, ifa);
583 rr.rid = vcpu_get_rr_rid(vcpu, ifa);
584 return rr.rrval;
585 }
587 IA64FAULT vcpu_get_itir(VCPU * vcpu, u64 * pval)
588 {
589 u64 val = PSCB(vcpu, itir);
590 *pval = val;
591 return IA64_NO_FAULT;
592 }
594 IA64FAULT vcpu_get_iipa(VCPU * vcpu, u64 * pval)
595 {
596 u64 val = PSCB(vcpu, iipa);
597 // SP entry code does not save iipa yet nor does it get
598 // properly delivered in the pscb
599 // printk("*** vcpu_get_iipa: cr.iipa not fully implemented yet!!\n");
600 *pval = val;
601 return IA64_NO_FAULT;
602 }
604 IA64FAULT vcpu_get_ifs(VCPU * vcpu, u64 * pval)
605 {
606 //PSCB(vcpu,ifs) = PSCB(vcpu)->regs.cr_ifs;
607 //*pval = PSCB(vcpu,regs).cr_ifs;
608 *pval = PSCB(vcpu, ifs);
609 return IA64_NO_FAULT;
610 }
612 IA64FAULT vcpu_get_iim(VCPU * vcpu, u64 * pval)
613 {
614 u64 val = PSCB(vcpu, iim);
615 *pval = val;
616 return IA64_NO_FAULT;
617 }
619 IA64FAULT vcpu_get_iha(VCPU * vcpu, u64 * pval)
620 {
621 PRIVOP_COUNT_ADDR(vcpu_regs(vcpu), privop_inst_thash);
622 *pval = PSCB(vcpu, iha);
623 return IA64_NO_FAULT;
624 }
626 IA64FAULT vcpu_set_dcr(VCPU * vcpu, u64 val)
627 {
628 PSCB(vcpu, dcr) = val;
629 return IA64_NO_FAULT;
630 }
632 IA64FAULT vcpu_set_iva(VCPU * vcpu, u64 val)
633 {
634 if (VMX_DOMAIN(vcpu))
635 PSCB(vcpu, iva) = val & ~0x7fffL;
636 else
637 PSCBX(vcpu, iva) = val & ~0x7fffL;
639 return IA64_NO_FAULT;
640 }
642 IA64FAULT vcpu_set_pta(VCPU * vcpu, u64 val)
643 {
644 if (val & IA64_PTA_LFMT) {
645 printk("*** No support for VHPT long format yet!!\n");
646 return IA64_ILLOP_FAULT;
647 }
648 if (val & (0x3f << 9)) /* reserved fields */
649 return IA64_RSVDREG_FAULT;
650 if (val & 2) /* reserved fields */
651 return IA64_RSVDREG_FAULT;
652 PSCB(vcpu, pta) = val;
653 return IA64_NO_FAULT;
654 }
656 IA64FAULT vcpu_set_ipsr(VCPU * vcpu, u64 val)
657 {
658 PSCB(vcpu, ipsr) = val;
659 return IA64_NO_FAULT;
660 }
662 IA64FAULT vcpu_set_isr(VCPU * vcpu, u64 val)
663 {
664 PSCB(vcpu, isr) = val;
665 return IA64_NO_FAULT;
666 }
668 IA64FAULT vcpu_set_iip(VCPU * vcpu, u64 val)
669 {
670 PSCB(vcpu, iip) = val;
671 return IA64_NO_FAULT;
672 }
674 IA64FAULT vcpu_increment_iip(VCPU * vcpu)
675 {
676 REGS *regs = vcpu_regs(vcpu);
677 struct ia64_psr *ipsr = (struct ia64_psr *)&regs->cr_ipsr;
678 if (ipsr->ri == 2) {
679 ipsr->ri = 0;
680 regs->cr_iip += 16;
681 } else
682 ipsr->ri++;
683 return IA64_NO_FAULT;
684 }
686 IA64FAULT vcpu_decrement_iip(VCPU * vcpu)
687 {
688 REGS *regs = vcpu_regs(vcpu);
689 struct ia64_psr *ipsr = (struct ia64_psr *)&regs->cr_ipsr;
691 if (ipsr->ri == 0) {
692 ipsr->ri = 2;
693 regs->cr_iip -= 16;
694 } else
695 ipsr->ri--;
697 return IA64_NO_FAULT;
698 }
700 IA64FAULT vcpu_set_ifa(VCPU * vcpu, u64 val)
701 {
702 PSCB(vcpu, ifa) = val;
703 return IA64_NO_FAULT;
704 }
706 IA64FAULT vcpu_set_itir(VCPU * vcpu, u64 val)
707 {
708 PSCB(vcpu, itir) = val;
709 return IA64_NO_FAULT;
710 }
712 IA64FAULT vcpu_set_iipa(VCPU * vcpu, u64 val)
713 {
714 // SP entry code does not save iipa yet nor does it get
715 // properly delivered in the pscb
716 // printk("*** vcpu_set_iipa: cr.iipa not fully implemented yet!!\n");
717 PSCB(vcpu, iipa) = val;
718 return IA64_NO_FAULT;
719 }
721 IA64FAULT vcpu_set_ifs(VCPU * vcpu, u64 val)
722 {
723 //REGS *regs = vcpu_regs(vcpu);
724 PSCB(vcpu, ifs) = val;
725 return IA64_NO_FAULT;
726 }
728 IA64FAULT vcpu_set_iim(VCPU * vcpu, u64 val)
729 {
730 PSCB(vcpu, iim) = val;
731 return IA64_NO_FAULT;
732 }
734 IA64FAULT vcpu_set_iha(VCPU * vcpu, u64 val)
735 {
736 PSCB(vcpu, iha) = val;
737 return IA64_NO_FAULT;
738 }
740 /**************************************************************************
741 VCPU interrupt control register access routines
742 **************************************************************************/
744 void vcpu_pend_unspecified_interrupt(VCPU * vcpu)
745 {
746 PSCB(vcpu, pending_interruption) = 1;
747 }
749 void vcpu_pend_interrupt(VCPU * vcpu, u64 vector)
750 {
751 if (vector & ~0xff) {
752 printk("vcpu_pend_interrupt: bad vector\n");
753 return;
754 }
756 if (vcpu->arch.event_callback_ip) {
757 printk("Deprecated interface. Move to new event based "
758 "solution\n");
759 return;
760 }
762 if (VMX_DOMAIN(vcpu)) {
763 set_bit(vector, VCPU(vcpu, irr));
764 } else {
765 set_bit(vector, PSCBX(vcpu, irr));
766 PSCB(vcpu, pending_interruption) = 1;
767 }
768 }
770 #define IA64_TPR_MMI 0x10000
771 #define IA64_TPR_MIC 0x000f0
773 /* checks to see if a VCPU has any unmasked pending interrupts
774 * if so, returns the highest, else returns SPURIOUS_VECTOR */
775 /* NOTE: Since this gets called from vcpu_get_ivr() and the
776 * semantics of "mov rx=cr.ivr" ignore the setting of the psr.i bit,
777 * this routine also ignores pscb.interrupt_delivery_enabled
778 * and this must be checked independently; see vcpu_deliverable interrupts() */
779 u64 vcpu_check_pending_interrupts(VCPU * vcpu)
780 {
781 u64 *p, *r, bits, bitnum, mask, i, vector;
783 if (vcpu->arch.event_callback_ip)
784 return SPURIOUS_VECTOR;
786 /* Always check pending event, since guest may just ack the
787 * event injection without handle. Later guest may throw out
788 * the event itself.
789 */
790 check_start:
791 if (event_pending(vcpu) &&
792 !test_bit(vcpu->domain->shared_info->arch.evtchn_vector,
793 &PSCBX(vcpu, insvc[0])))
794 vcpu_pend_interrupt(vcpu,
795 vcpu->domain->shared_info->arch.
796 evtchn_vector);
798 p = &PSCBX(vcpu, irr[3]);
799 r = &PSCBX(vcpu, insvc[3]);
800 for (i = 3 ;; p--, r--, i--) {
801 bits = *p;
802 if (bits)
803 break; // got a potential interrupt
804 if (*r) {
805 // nothing in this word which is pending+inservice
806 // but there is one inservice which masks lower
807 return SPURIOUS_VECTOR;
808 }
809 if (i == 0) {
810 // checked all bits... nothing pending+inservice
811 return SPURIOUS_VECTOR;
812 }
813 }
814 // have a pending,deliverable interrupt... see if it is masked
815 bitnum = ia64_fls(bits);
816 //printk("XXXXXXX vcpu_check_pending_interrupts: got bitnum=%p...\n",bitnum);
817 vector = bitnum + (i * 64);
818 mask = 1L << bitnum;
819 /* sanity check for guest timer interrupt */
820 if (vector == (PSCB(vcpu, itv) & 0xff)) {
821 uint64_t now = ia64_get_itc();
822 if (now < PSCBX(vcpu, domain_itm)) {
823 // printk("Ooops, pending guest timer before its due\n");
824 PSCBX(vcpu, irr[i]) &= ~mask;
825 goto check_start;
826 }
827 }
828 //printk("XXXXXXX vcpu_check_pending_interrupts: got vector=%p...\n",vector);
829 if (*r >= mask) {
830 // masked by equal inservice
831 //printk("but masked by equal inservice\n");
832 return SPURIOUS_VECTOR;
833 }
834 if (PSCB(vcpu, tpr) & IA64_TPR_MMI) {
835 // tpr.mmi is set
836 //printk("but masked by tpr.mmi\n");
837 return SPURIOUS_VECTOR;
838 }
839 if (((PSCB(vcpu, tpr) & IA64_TPR_MIC) + 15) >= vector) {
840 //tpr.mic masks class
841 //printk("but masked by tpr.mic\n");
842 return SPURIOUS_VECTOR;
843 }
844 //printk("returned to caller\n");
845 return vector;
846 }
848 u64 vcpu_deliverable_interrupts(VCPU * vcpu)
849 {
850 return (vcpu_get_psr_i(vcpu) &&
851 vcpu_check_pending_interrupts(vcpu) != SPURIOUS_VECTOR);
852 }
854 u64 vcpu_deliverable_timer(VCPU * vcpu)
855 {
856 return (vcpu_get_psr_i(vcpu) &&
857 vcpu_check_pending_interrupts(vcpu) == PSCB(vcpu, itv));
858 }
860 IA64FAULT vcpu_get_lid(VCPU * vcpu, u64 * pval)
861 {
862 /* Use EID=0, ID=vcpu_id. */
863 *pval = vcpu->vcpu_id << 24;
864 return IA64_NO_FAULT;
865 }
867 IA64FAULT vcpu_get_ivr(VCPU * vcpu, u64 * pval)
868 {
869 int i;
870 u64 vector, mask;
872 #define HEARTBEAT_FREQ 16 // period in seconds
873 #ifdef HEARTBEAT_FREQ
874 #define N_DOMS 16 // period in seconds
875 #if 0
876 static long count[N_DOMS] = { 0 };
877 #endif
878 static long nonclockcount[N_DOMS] = { 0 };
879 unsigned domid = vcpu->domain->domain_id;
880 #endif
881 #ifdef IRQ_DEBUG
882 static char firstivr = 1;
883 static char firsttime[256];
884 if (firstivr) {
885 int i;
886 for (i = 0; i < 256; i++)
887 firsttime[i] = 1;
888 firstivr = 0;
889 }
890 #endif
892 vector = vcpu_check_pending_interrupts(vcpu);
893 if (vector == SPURIOUS_VECTOR) {
894 PSCB(vcpu, pending_interruption) = 0;
895 *pval = vector;
896 return IA64_NO_FAULT;
897 }
898 #ifdef HEARTBEAT_FREQ
899 if (domid >= N_DOMS)
900 domid = N_DOMS - 1;
901 #if 0
902 if (vector == (PSCB(vcpu, itv) & 0xff)) {
903 if (!(++count[domid] & ((HEARTBEAT_FREQ * 1024) - 1))) {
904 printk("Dom%d heartbeat... ticks=%lx,nonticks=%lx\n",
905 domid, count[domid], nonclockcount[domid]);
906 //count[domid] = 0;
907 //dump_runq();
908 }
909 }
910 #endif
911 else
912 nonclockcount[domid]++;
913 #endif
914 // now have an unmasked, pending, deliverable vector!
915 // getting ivr has "side effects"
916 #ifdef IRQ_DEBUG
917 if (firsttime[vector]) {
918 printk("*** First get_ivr on vector=%lu,itc=%lx\n",
919 vector, ia64_get_itc());
920 firsttime[vector] = 0;
921 }
922 #endif
923 /* if delivering a timer interrupt, remember domain_itm, which
924 * needs to be done before clearing irr
925 */
926 if (vector == (PSCB(vcpu, itv) & 0xff)) {
927 PSCBX(vcpu, domain_itm_last) = PSCBX(vcpu, domain_itm);
928 }
930 i = vector >> 6;
931 mask = 1L << (vector & 0x3f);
932 //printk("ZZZZZZ vcpu_get_ivr: setting insvc mask for vector %lu\n",vector);
933 PSCBX(vcpu, insvc[i]) |= mask;
934 PSCBX(vcpu, irr[i]) &= ~mask;
935 //PSCB(vcpu,pending_interruption)--;
936 *pval = vector;
937 return IA64_NO_FAULT;
938 }
940 IA64FAULT vcpu_get_tpr(VCPU * vcpu, u64 * pval)
941 {
942 *pval = PSCB(vcpu, tpr);
943 return IA64_NO_FAULT;
944 }
946 IA64FAULT vcpu_get_eoi(VCPU * vcpu, u64 * pval)
947 {
948 *pval = 0L; // reads of eoi always return 0
949 return IA64_NO_FAULT;
950 }
952 IA64FAULT vcpu_get_irr0(VCPU * vcpu, u64 * pval)
953 {
954 *pval = PSCBX(vcpu, irr[0]);
955 return IA64_NO_FAULT;
956 }
958 IA64FAULT vcpu_get_irr1(VCPU * vcpu, u64 * pval)
959 {
960 *pval = PSCBX(vcpu, irr[1]);
961 return IA64_NO_FAULT;
962 }
964 IA64FAULT vcpu_get_irr2(VCPU * vcpu, u64 * pval)
965 {
966 *pval = PSCBX(vcpu, irr[2]);
967 return IA64_NO_FAULT;
968 }
970 IA64FAULT vcpu_get_irr3(VCPU * vcpu, u64 * pval)
971 {
972 *pval = PSCBX(vcpu, irr[3]);
973 return IA64_NO_FAULT;
974 }
976 IA64FAULT vcpu_get_itv(VCPU * vcpu, u64 * pval)
977 {
978 *pval = PSCB(vcpu, itv);
979 return IA64_NO_FAULT;
980 }
982 IA64FAULT vcpu_get_pmv(VCPU * vcpu, u64 * pval)
983 {
984 *pval = PSCB(vcpu, pmv);
985 return IA64_NO_FAULT;
986 }
988 IA64FAULT vcpu_get_cmcv(VCPU * vcpu, u64 * pval)
989 {
990 *pval = PSCB(vcpu, cmcv);
991 return IA64_NO_FAULT;
992 }
994 IA64FAULT vcpu_get_lrr0(VCPU * vcpu, u64 * pval)
995 {
996 // fix this when setting values other than m-bit is supported
997 gdprintk(XENLOG_DEBUG,
998 "vcpu_get_lrr0: Unmasked interrupts unsupported\n");
999 *pval = (1L << 16);
1000 return IA64_NO_FAULT;
1003 IA64FAULT vcpu_get_lrr1(VCPU * vcpu, u64 * pval)
1005 // fix this when setting values other than m-bit is supported
1006 gdprintk(XENLOG_DEBUG,
1007 "vcpu_get_lrr1: Unmasked interrupts unsupported\n");
1008 *pval = (1L << 16);
1009 return IA64_NO_FAULT;
1012 IA64FAULT vcpu_set_lid(VCPU * vcpu, u64 val)
1014 printk("vcpu_set_lid: Setting cr.lid is unsupported\n");
1015 return IA64_ILLOP_FAULT;
1018 IA64FAULT vcpu_set_tpr(VCPU * vcpu, u64 val)
1020 if (val & 0xff00)
1021 return IA64_RSVDREG_FAULT;
1022 PSCB(vcpu, tpr) = val;
1023 /* This can unmask interrupts. */
1024 if (vcpu_check_pending_interrupts(vcpu) != SPURIOUS_VECTOR)
1025 PSCB(vcpu, pending_interruption) = 1;
1026 return IA64_NO_FAULT;
1029 IA64FAULT vcpu_set_eoi(VCPU * vcpu, u64 val)
1031 u64 *p, bits, vec, bitnum;
1032 int i;
1034 p = &PSCBX(vcpu, insvc[3]);
1035 for (i = 3; (i >= 0) && !(bits = *p); i--, p--)
1037 if (i < 0) {
1038 printk("Trying to EOI interrupt when none are in-service.\n");
1039 return IA64_NO_FAULT;
1041 bitnum = ia64_fls(bits);
1042 vec = bitnum + (i * 64);
1043 /* clear the correct bit */
1044 bits &= ~(1L << bitnum);
1045 *p = bits;
1046 /* clearing an eoi bit may unmask another pending interrupt... */
1047 if (!vcpu->vcpu_info->evtchn_upcall_mask) { // but only if enabled...
1048 // worry about this later... Linux only calls eoi
1049 // with interrupts disabled
1050 printk("Trying to EOI interrupt with interrupts enabled\n");
1052 if (vcpu_check_pending_interrupts(vcpu) != SPURIOUS_VECTOR)
1053 PSCB(vcpu, pending_interruption) = 1;
1054 //printk("YYYYY vcpu_set_eoi: Successful\n");
1055 return IA64_NO_FAULT;
1058 IA64FAULT vcpu_set_lrr0(VCPU * vcpu, u64 val)
1060 if (!(val & (1L << 16))) {
1061 printk("vcpu_set_lrr0: Unmasked interrupts unsupported\n");
1062 return IA64_ILLOP_FAULT;
1064 // no place to save this state but nothing to do anyway
1065 return IA64_NO_FAULT;
1068 IA64FAULT vcpu_set_lrr1(VCPU * vcpu, u64 val)
1070 if (!(val & (1L << 16))) {
1071 printk("vcpu_set_lrr0: Unmasked interrupts unsupported\n");
1072 return IA64_ILLOP_FAULT;
1074 // no place to save this state but nothing to do anyway
1075 return IA64_NO_FAULT;
1078 IA64FAULT vcpu_set_itv(VCPU * vcpu, u64 val)
1080 /* Check reserved fields. */
1081 if (val & 0xef00)
1082 return IA64_ILLOP_FAULT;
1083 PSCB(vcpu, itv) = val;
1084 if (val & 0x10000) {
1085 /* Disable itm. */
1086 PSCBX(vcpu, domain_itm) = 0;
1087 } else
1088 vcpu_set_next_timer(vcpu);
1089 return IA64_NO_FAULT;
1092 IA64FAULT vcpu_set_pmv(VCPU * vcpu, u64 val)
1094 if (val & 0xef00) /* reserved fields */
1095 return IA64_RSVDREG_FAULT;
1096 PSCB(vcpu, pmv) = val;
1097 return IA64_NO_FAULT;
1100 IA64FAULT vcpu_set_cmcv(VCPU * vcpu, u64 val)
1102 if (val & 0xef00) /* reserved fields */
1103 return IA64_RSVDREG_FAULT;
1104 PSCB(vcpu, cmcv) = val;
1105 return IA64_NO_FAULT;
1108 /**************************************************************************
1109 VCPU temporary register access routines
1110 **************************************************************************/
1111 u64 vcpu_get_tmp(VCPU * vcpu, u64 index)
1113 if (index > 7)
1114 return 0;
1115 return PSCB(vcpu, tmp[index]);
1118 void vcpu_set_tmp(VCPU * vcpu, u64 index, u64 val)
1120 if (index <= 7)
1121 PSCB(vcpu, tmp[index]) = val;
1124 /**************************************************************************
1125 Interval timer routines
1126 **************************************************************************/
1128 BOOLEAN vcpu_timer_disabled(VCPU * vcpu)
1130 u64 itv = PSCB(vcpu, itv);
1131 return (!itv || !!(itv & 0x10000));
1134 BOOLEAN vcpu_timer_inservice(VCPU * vcpu)
1136 u64 itv = PSCB(vcpu, itv);
1137 return test_bit(itv, PSCBX(vcpu, insvc));
1140 BOOLEAN vcpu_timer_expired(VCPU * vcpu)
1142 unsigned long domain_itm = PSCBX(vcpu, domain_itm);
1143 unsigned long now = ia64_get_itc();
1145 if (!domain_itm)
1146 return FALSE;
1147 if (now < domain_itm)
1148 return FALSE;
1149 if (vcpu_timer_disabled(vcpu))
1150 return FALSE;
1151 return TRUE;
1154 void vcpu_safe_set_itm(unsigned long val)
1156 unsigned long epsilon = 100;
1157 unsigned long flags;
1158 u64 now = ia64_get_itc();
1160 local_irq_save(flags);
1161 while (1) {
1162 //printk("*** vcpu_safe_set_itm: Setting itm to %lx, itc=%lx\n",val,now);
1163 ia64_set_itm(val);
1164 if (val > (now = ia64_get_itc()))
1165 break;
1166 val = now + epsilon;
1167 epsilon <<= 1;
1169 local_irq_restore(flags);
1172 void vcpu_set_next_timer(VCPU * vcpu)
1174 u64 d = PSCBX(vcpu, domain_itm);
1175 //u64 s = PSCBX(vcpu,xen_itm);
1176 u64 s = local_cpu_data->itm_next;
1177 u64 now = ia64_get_itc();
1179 /* gloss over the wraparound problem for now... we know it exists
1180 * but it doesn't matter right now */
1182 if (is_idle_domain(vcpu->domain)) {
1183 // printk("****** vcpu_set_next_timer called during idle!!\n");
1184 vcpu_safe_set_itm(s);
1185 return;
1187 //s = PSCBX(vcpu,xen_itm);
1188 if (d && (d > now) && (d < s)) {
1189 vcpu_safe_set_itm(d);
1190 //using_domain_as_itm++;
1191 } else {
1192 vcpu_safe_set_itm(s);
1193 //using_xen_as_itm++;
1197 IA64FAULT vcpu_set_itm(VCPU * vcpu, u64 val)
1199 //UINT now = ia64_get_itc();
1201 //if (val < now) val = now + 1000;
1202 //printk("*** vcpu_set_itm: called with %lx\n",val);
1203 PSCBX(vcpu, domain_itm) = val;
1204 vcpu_set_next_timer(vcpu);
1205 return IA64_NO_FAULT;
1208 IA64FAULT vcpu_set_itc(VCPU * vcpu, u64 val)
1210 #define DISALLOW_SETTING_ITC_FOR_NOW
1211 #ifdef DISALLOW_SETTING_ITC_FOR_NOW
1212 static int did_print;
1213 if (!did_print) {
1214 printk("vcpu_set_itc: Setting ar.itc is currently disabled "
1215 "(this message is only displayed once)\n");
1216 did_print = 1;
1218 #else
1219 u64 oldnow = ia64_get_itc();
1220 u64 olditm = PSCBX(vcpu, domain_itm);
1221 unsigned long d = olditm - oldnow;
1222 unsigned long x = local_cpu_data->itm_next - oldnow;
1224 u64 newnow = val, min_delta;
1226 local_irq_disable();
1227 if (olditm) {
1228 printk("**** vcpu_set_itc(%lx): vitm changed to %lx\n", val,
1229 newnow + d);
1230 PSCBX(vcpu, domain_itm) = newnow + d;
1232 local_cpu_data->itm_next = newnow + x;
1233 d = PSCBX(vcpu, domain_itm);
1234 x = local_cpu_data->itm_next;
1236 ia64_set_itc(newnow);
1237 if (d && (d > newnow) && (d < x)) {
1238 vcpu_safe_set_itm(d);
1239 //using_domain_as_itm++;
1240 } else {
1241 vcpu_safe_set_itm(x);
1242 //using_xen_as_itm++;
1244 local_irq_enable();
1245 #endif
1246 return IA64_NO_FAULT;
1249 IA64FAULT vcpu_get_itm(VCPU * vcpu, u64 * pval)
1251 //FIXME: Implement this
1252 printk("vcpu_get_itm: Getting cr.itm is unsupported... continuing\n");
1253 return IA64_NO_FAULT;
1254 //return IA64_ILLOP_FAULT;
1257 IA64FAULT vcpu_get_itc(VCPU * vcpu, u64 * pval)
1259 //TODO: Implement this
1260 printk("vcpu_get_itc: Getting ar.itc is unsupported\n");
1261 return IA64_ILLOP_FAULT;
1264 void vcpu_pend_timer(VCPU * vcpu)
1266 u64 itv = PSCB(vcpu, itv) & 0xff;
1268 if (vcpu_timer_disabled(vcpu))
1269 return;
1270 //if (vcpu_timer_inservice(vcpu)) return;
1271 if (PSCBX(vcpu, domain_itm_last) == PSCBX(vcpu, domain_itm)) {
1272 // already delivered an interrupt for this so
1273 // don't deliver another
1274 return;
1276 if (vcpu->arch.event_callback_ip) {
1277 /* A small window may occur when injecting vIRQ while related
1278 * handler has not been registered. Don't fire in such case.
1279 */
1280 if (vcpu->virq_to_evtchn[VIRQ_ITC]) {
1281 send_guest_vcpu_virq(vcpu, VIRQ_ITC);
1282 PSCBX(vcpu, domain_itm_last) = PSCBX(vcpu, domain_itm);
1284 } else
1285 vcpu_pend_interrupt(vcpu, itv);
1288 // returns true if ready to deliver a timer interrupt too early
1289 u64 vcpu_timer_pending_early(VCPU * vcpu)
1291 u64 now = ia64_get_itc();
1292 u64 itm = PSCBX(vcpu, domain_itm);
1294 if (vcpu_timer_disabled(vcpu))
1295 return 0;
1296 if (!itm)
1297 return 0;
1298 return (vcpu_deliverable_timer(vcpu) && (now < itm));
1301 /**************************************************************************
1302 Privileged operation emulation routines
1303 **************************************************************************/
1305 static void vcpu_force_tlb_miss(VCPU * vcpu, u64 ifa)
1307 PSCB(vcpu, ifa) = ifa;
1308 PSCB(vcpu, itir) = vcpu_get_itir_on_fault(vcpu, ifa);
1309 vcpu_thash(current, ifa, &PSCB(current, iha));
1312 IA64FAULT vcpu_force_inst_miss(VCPU * vcpu, u64 ifa)
1314 vcpu_force_tlb_miss(vcpu, ifa);
1315 return vcpu_get_rr_ve(vcpu, ifa) ? IA64_INST_TLB_VECTOR :
1316 IA64_ALT_INST_TLB_VECTOR;
1319 IA64FAULT vcpu_force_data_miss(VCPU * vcpu, u64 ifa)
1321 vcpu_force_tlb_miss(vcpu, ifa);
1322 return vcpu_get_rr_ve(vcpu, ifa) ? IA64_DATA_TLB_VECTOR :
1323 IA64_ALT_DATA_TLB_VECTOR;
1326 IA64FAULT vcpu_rfi(VCPU * vcpu)
1328 // TODO: Only allowed for current vcpu
1329 PSR psr;
1330 u64 int_enable, ifs;
1331 REGS *regs = vcpu_regs(vcpu);
1333 psr.i64 = PSCB(vcpu, ipsr);
1334 if (psr.ia64_psr.cpl < 3)
1335 psr.ia64_psr.cpl = 2;
1336 int_enable = psr.ia64_psr.i;
1337 if (psr.ia64_psr.dfh) {
1338 PSCB(vcpu, vpsr_dfh) = 1;
1339 } else {
1340 psr.ia64_psr.dfh = PSCB(vcpu, hpsr_dfh);
1341 PSCB(vcpu, vpsr_dfh) = 0;
1343 if (psr.ia64_psr.ic)
1344 PSCB(vcpu, interrupt_collection_enabled) = 1;
1345 if (psr.ia64_psr.dt && psr.ia64_psr.rt && psr.ia64_psr.it)
1346 vcpu_set_metaphysical_mode(vcpu, FALSE);
1347 else
1348 vcpu_set_metaphysical_mode(vcpu, TRUE);
1349 psr.ia64_psr.ic = 1;
1350 psr.ia64_psr.i = 1;
1351 psr.ia64_psr.dt = 1;
1352 psr.ia64_psr.rt = 1;
1353 psr.ia64_psr.it = 1;
1354 psr.ia64_psr.bn = 1;
1355 //psr.pk = 1; // checking pkeys shouldn't be a problem but seems broken
1357 ifs = PSCB(vcpu, ifs);
1358 if (ifs & 0x8000000000000000UL)
1359 regs->cr_ifs = ifs;
1361 regs->cr_ipsr = psr.i64;
1362 regs->cr_iip = PSCB(vcpu, iip);
1363 PSCB(vcpu, interrupt_collection_enabled) = 1;
1364 vcpu_bsw1(vcpu);
1365 vcpu->vcpu_info->evtchn_upcall_mask = !int_enable;
1366 return IA64_NO_FAULT;
1369 IA64FAULT vcpu_cover(VCPU * vcpu)
1371 // TODO: Only allowed for current vcpu
1372 REGS *regs = vcpu_regs(vcpu);
1374 if (!PSCB(vcpu, interrupt_collection_enabled)) {
1375 PSCB(vcpu, ifs) = regs->cr_ifs;
1377 regs->cr_ifs = 0;
1378 return IA64_NO_FAULT;
1381 IA64FAULT vcpu_thash(VCPU * vcpu, u64 vadr, u64 * pval)
1383 u64 pta = PSCB(vcpu, pta);
1384 u64 pta_sz = (pta & IA64_PTA_SZ(0x3f)) >> IA64_PTA_SZ_BIT;
1385 u64 pta_base = pta & ~((1UL << IA64_PTA_BASE_BIT) - 1);
1386 u64 Mask = (1L << pta_sz) - 1;
1387 u64 Mask_60_15 = (Mask >> 15) & 0x3fffffffffff;
1388 u64 compMask_60_15 = ~Mask_60_15;
1389 u64 rr_ps = vcpu_get_rr_ps(vcpu, vadr);
1390 u64 VHPT_offset = (vadr >> rr_ps) << 3;
1391 u64 VHPT_addr1 = vadr & 0xe000000000000000L;
1392 u64 VHPT_addr2a =
1393 ((pta_base >> 15) & 0x3fffffffffff) & compMask_60_15;
1394 u64 VHPT_addr2b =
1395 ((VHPT_offset >> 15) & 0x3fffffffffff) & Mask_60_15;
1396 u64 VHPT_addr3 = VHPT_offset & 0x7fff;
1397 u64 VHPT_addr = VHPT_addr1 | ((VHPT_addr2a | VHPT_addr2b) << 15) |
1398 VHPT_addr3;
1400 //verbose("vcpu_thash: vadr=%p, VHPT_addr=%p\n",vadr,VHPT_addr);
1401 *pval = VHPT_addr;
1402 return IA64_NO_FAULT;
1405 IA64FAULT vcpu_ttag(VCPU * vcpu, u64 vadr, u64 * padr)
1407 printk("vcpu_ttag: ttag instruction unsupported\n");
1408 return IA64_ILLOP_FAULT;
1411 int warn_region0_address = 0; // FIXME later: tie to a boot parameter?
1413 /* Return TRUE iff [b1,e1] and [b2,e2] partially or fully overlaps. */
1414 static inline int range_overlap(u64 b1, u64 e1, u64 b2, u64 e2)
1416 return (b1 <= e2) && (e1 >= b2);
1419 /* Crash domain if [base, base + page_size] and Xen virtual space overlaps.
1420 Note: LSBs of base inside page_size are ignored. */
1421 static inline void
1422 check_xen_space_overlap(const char *func, u64 base, u64 page_size)
1424 /* Overlaps can occur only in region 7.
1425 (This is an optimization to bypass all the checks). */
1426 if (REGION_NUMBER(base) != 7)
1427 return;
1429 /* Mask LSBs of base. */
1430 base &= ~(page_size - 1);
1432 /* FIXME: ideally an MCA should be generated... */
1433 if (range_overlap(HYPERVISOR_VIRT_START, HYPERVISOR_VIRT_END,
1434 base, base + page_size)
1435 || range_overlap(current->domain->arch.shared_info_va,
1436 current->domain->arch.shared_info_va
1437 + XSI_SIZE + XMAPPEDREGS_SIZE,
1438 base, base + page_size))
1439 panic_domain(NULL, "%s on Xen virtual space (%lx)\n",
1440 func, base);
1443 // FIXME: also need to check && (!trp->key || vcpu_pkr_match(trp->key))
1444 static inline int vcpu_match_tr_entry_no_p(TR_ENTRY * trp, u64 ifa,
1445 u64 rid)
1447 return trp->rid == rid
1448 && ifa >= trp->vadr && ifa <= (trp->vadr + (1L << trp->ps) - 1);
1451 static inline int vcpu_match_tr_entry(TR_ENTRY * trp, u64 ifa, u64 rid)
1453 return trp->pte.p && vcpu_match_tr_entry_no_p(trp, ifa, rid);
1456 static inline int
1457 vcpu_match_tr_entry_range(TR_ENTRY * trp, u64 rid, u64 b, u64 e)
1459 return trp->rid == rid
1460 && trp->pte.p
1461 && range_overlap(b, e, trp->vadr, trp->vadr + (1L << trp->ps) - 1);
1465 static TR_ENTRY *vcpu_tr_lookup(VCPU * vcpu, unsigned long va, u64 rid,
1466 BOOLEAN is_data)
1468 unsigned char *regions;
1469 TR_ENTRY *trp;
1470 int tr_max;
1471 int i;
1473 if (is_data) {
1474 // data
1475 regions = &vcpu->arch.dtr_regions;
1476 trp = vcpu->arch.dtrs;
1477 tr_max = sizeof(vcpu->arch.dtrs) / sizeof(vcpu->arch.dtrs[0]);
1478 } else {
1479 // instruction
1480 regions = &vcpu->arch.itr_regions;
1481 trp = vcpu->arch.itrs;
1482 tr_max = sizeof(vcpu->arch.itrs) / sizeof(vcpu->arch.itrs[0]);
1485 if (!vcpu_quick_region_check(*regions, va)) {
1486 return NULL;
1488 for (i = 0; i < tr_max; i++, trp++) {
1489 if (vcpu_match_tr_entry(trp, va, rid)) {
1490 return trp;
1493 return NULL;
1496 // return value
1497 // 0: failure
1498 // 1: success
1499 int
1500 vcpu_get_domain_bundle(VCPU * vcpu, REGS * regs, u64 gip,
1501 IA64_BUNDLE * bundle)
1503 u64 gpip; // guest pseudo phyiscal ip
1504 unsigned long vaddr;
1505 struct page_info *page;
1507 again:
1508 #if 0
1509 // Currently xen doesn't track psr.it bits.
1510 // it assumes always psr.it = 1.
1511 if (!(VCPU(vcpu, vpsr) & IA64_PSR_IT)) {
1512 gpip = gip;
1513 } else
1514 #endif
1516 unsigned long region = REGION_NUMBER(gip);
1517 unsigned long rr = PSCB(vcpu, rrs)[region];
1518 unsigned long rid = rr & RR_RID_MASK;
1519 BOOLEAN swap_rr0;
1520 TR_ENTRY *trp;
1522 // vcpu->arch.{i, d}tlb are volatile,
1523 // copy its value to the variable, tr, before use.
1524 TR_ENTRY tr;
1526 trp = vcpu_tr_lookup(vcpu, gip, rid, 0);
1527 if (trp != NULL) {
1528 tr = *trp;
1529 goto found;
1531 // When it failed to get a bundle, itlb miss is reflected.
1532 // Last itc.i value is cached to PSCBX(vcpu, itlb).
1533 tr = PSCBX(vcpu, itlb);
1534 if (vcpu_match_tr_entry(&tr, gip, rid)) {
1535 //dprintk(XENLOG_WARNING,
1536 // "%s gip 0x%lx gpip 0x%lx\n", __func__,
1537 // gip, gpip);
1538 goto found;
1540 trp = vcpu_tr_lookup(vcpu, gip, rid, 1);
1541 if (trp != NULL) {
1542 tr = *trp;
1543 goto found;
1545 #if 0
1546 tr = PSCBX(vcpu, dtlb);
1547 if (vcpu_match_tr_entry(&tr, gip, rid)) {
1548 goto found;
1550 #endif
1552 // try to access gip with guest virtual address
1553 // This may cause tlb miss. see vcpu_translate(). Be careful!
1554 swap_rr0 = (!region && PSCB(vcpu, metaphysical_mode));
1555 if (swap_rr0) {
1556 set_one_rr(0x0, PSCB(vcpu, rrs[0]));
1558 *bundle = __get_domain_bundle(gip);
1559 if (swap_rr0) {
1560 set_metaphysical_rr0();
1562 if (bundle->i64[0] == 0 && bundle->i64[1] == 0) {
1563 dprintk(XENLOG_INFO, "%s gip 0x%lx\n", __func__, gip);
1564 return 0;
1566 return 1;
1568 found:
1569 gpip = ((tr.pte.ppn >> (tr.ps - 12)) << tr.ps) |
1570 (gip & ((1 << tr.ps) - 1));
1573 vaddr = (unsigned long)domain_mpa_to_imva(vcpu->domain, gpip);
1574 page = virt_to_page(vaddr);
1575 if (get_page(page, vcpu->domain) == 0) {
1576 if (page_get_owner(page) != vcpu->domain) {
1577 // This page might be a page granted by another
1578 // domain.
1579 panic_domain(regs, "domain tries to execute foreign "
1580 "domain page which might be mapped by "
1581 "grant table.\n");
1583 goto again;
1585 *bundle = *((IA64_BUNDLE *) vaddr);
1586 put_page(page);
1587 return 1;
1590 IA64FAULT vcpu_translate(VCPU * vcpu, u64 address, BOOLEAN is_data,
1591 u64 * pteval, u64 * itir, u64 * iha)
1593 unsigned long region = address >> 61;
1594 unsigned long pta, rid, rr;
1595 union pte_flags pte;
1596 TR_ENTRY *trp;
1598 if (PSCB(vcpu, metaphysical_mode) && !(!is_data && region)) {
1599 // dom0 may generate an uncacheable physical address (msb=1)
1600 if (region && ((region != 4) || (vcpu->domain != dom0))) {
1601 // FIXME: This seems to happen even though it shouldn't. Need to track
1602 // this down, but since it has been apparently harmless, just flag it for now
1603 // panic_domain(vcpu_regs(vcpu),
1605 /*
1606 * Guest may execute itc.d and rfi with psr.dt=0
1607 * When VMM try to fetch opcode, tlb miss may happen,
1608 * At this time PSCB(vcpu,metaphysical_mode)=1,
1609 * region=5,VMM need to handle this tlb miss as if
1610 * PSCB(vcpu,metaphysical_mode)=0
1611 */
1612 printk("vcpu_translate: bad physical address: 0x%lx "
1613 "at %lx\n", address, vcpu_regs(vcpu)->cr_iip);
1615 } else {
1616 *pteval = (address & _PAGE_PPN_MASK) |
1617 __DIRTY_BITS | _PAGE_PL_2 | _PAGE_AR_RWX;
1618 *itir = PAGE_SHIFT << 2;
1619 perfc_incrc(phys_translate);
1620 return IA64_NO_FAULT;
1622 } else if (!region && warn_region0_address) {
1623 REGS *regs = vcpu_regs(vcpu);
1624 unsigned long viip = PSCB(vcpu, iip);
1625 unsigned long vipsr = PSCB(vcpu, ipsr);
1626 unsigned long iip = regs->cr_iip;
1627 unsigned long ipsr = regs->cr_ipsr;
1628 printk("vcpu_translate: bad address 0x%lx, viip=0x%lx, "
1629 "vipsr=0x%lx, iip=0x%lx, ipsr=0x%lx continuing\n",
1630 address, viip, vipsr, iip, ipsr);
1633 rr = PSCB(vcpu, rrs)[region];
1634 rid = rr & RR_RID_MASK;
1635 if (is_data) {
1636 trp = vcpu_tr_lookup(vcpu, address, rid, 1);
1637 if (trp != NULL) {
1638 *pteval = trp->pte.val;
1639 *itir = trp->itir;
1640 perfc_incrc(tr_translate);
1641 return IA64_NO_FAULT;
1644 // FIXME?: check itr's for data accesses too, else bad things happen?
1645 /* else */ {
1646 trp = vcpu_tr_lookup(vcpu, address, rid, 0);
1647 if (trp != NULL) {
1648 *pteval = trp->pte.val;
1649 *itir = trp->itir;
1650 perfc_incrc(tr_translate);
1651 return IA64_NO_FAULT;
1655 /* check 1-entry TLB */
1656 // FIXME?: check dtlb for inst accesses too, else bad things happen?
1657 trp = &vcpu->arch.dtlb;
1658 pte = trp->pte;
1659 if ( /* is_data && */ pte.p
1660 && vcpu_match_tr_entry_no_p(trp, address, rid)) {
1661 *pteval = pte.val;
1662 *itir = trp->itir;
1663 perfc_incrc(dtlb_translate);
1664 return IA64_USE_TLB;
1667 /* check guest VHPT */
1668 pta = PSCB(vcpu, pta);
1669 if (pta & IA64_PTA_VF) { /* long format VHPT - not implemented */
1670 panic_domain(vcpu_regs(vcpu), "can't do long format VHPT\n");
1671 //return is_data ? IA64_DATA_TLB_VECTOR:IA64_INST_TLB_VECTOR;
1674 *itir = rr & (RR_RID_MASK | RR_PS_MASK);
1675 // note: architecturally, iha is optionally set for alt faults but
1676 // xenlinux depends on it so should document it as part of PV interface
1677 vcpu_thash(vcpu, address, iha);
1678 if (!(rr & RR_VE_MASK) || !(pta & IA64_PTA_VE)) {
1679 REGS *regs = vcpu_regs(vcpu);
1680 // NOTE: This is specific code for linux kernel
1681 // We assume region 7 is identity mapped
1682 if (region == 7 && ia64_psr(regs)->cpl == 2) {
1683 pte.val = address & _PAGE_PPN_MASK;
1684 pte.val = pte.val | pgprot_val(PAGE_KERNEL);
1685 goto out;
1687 return is_data ? IA64_ALT_DATA_TLB_VECTOR :
1688 IA64_ALT_INST_TLB_VECTOR;
1691 /* avoid recursively walking (short format) VHPT */
1692 if (((address ^ pta) & ((itir_mask(pta) << 3) >> 3)) == 0)
1693 return is_data ? IA64_DATA_TLB_VECTOR : IA64_INST_TLB_VECTOR;
1695 if (!__access_ok(*iha)
1696 || __copy_from_user(&pte, (void *)(*iha), sizeof(pte)) != 0)
1697 // virtual VHPT walker "missed" in TLB
1698 return IA64_VHPT_FAULT;
1700 /*
1701 * Optimisation: this VHPT walker aborts on not-present pages
1702 * instead of inserting a not-present translation, this allows
1703 * vectoring directly to the miss handler.
1704 */
1705 if (!pte.p)
1706 return is_data ? IA64_DATA_TLB_VECTOR : IA64_INST_TLB_VECTOR;
1708 /* found mapping in guest VHPT! */
1709 out:
1710 *itir = rr & RR_PS_MASK;
1711 *pteval = pte.val;
1712 perfc_incrc(vhpt_translate);
1713 return IA64_NO_FAULT;
1716 IA64FAULT vcpu_tpa(VCPU * vcpu, u64 vadr, u64 * padr)
1718 u64 pteval, itir, mask, iha;
1719 IA64FAULT fault;
1721 fault = vcpu_translate(vcpu, vadr, TRUE, &pteval, &itir, &iha);
1722 if (fault == IA64_NO_FAULT || fault == IA64_USE_TLB) {
1723 mask = itir_mask(itir);
1724 *padr = (pteval & _PAGE_PPN_MASK & mask) | (vadr & ~mask);
1725 return IA64_NO_FAULT;
1727 return vcpu_force_data_miss(vcpu, vadr);
1730 IA64FAULT vcpu_tak(VCPU * vcpu, u64 vadr, u64 * key)
1732 printk("vcpu_tak: tak instruction unsupported\n");
1733 return IA64_ILLOP_FAULT;
1734 // HACK ALERT: tak does a thash for now
1735 //return vcpu_thash(vcpu,vadr,key);
1738 /**************************************************************************
1739 VCPU debug breakpoint register access routines
1740 **************************************************************************/
1742 IA64FAULT vcpu_set_dbr(VCPU * vcpu, u64 reg, u64 val)
1744 // TODO: unimplemented DBRs return a reserved register fault
1745 // TODO: Should set Logical CPU state, not just physical
1746 ia64_set_dbr(reg, val);
1747 return IA64_NO_FAULT;
1750 IA64FAULT vcpu_set_ibr(VCPU * vcpu, u64 reg, u64 val)
1752 // TODO: unimplemented IBRs return a reserved register fault
1753 // TODO: Should set Logical CPU state, not just physical
1754 ia64_set_ibr(reg, val);
1755 return IA64_NO_FAULT;
1758 IA64FAULT vcpu_get_dbr(VCPU * vcpu, u64 reg, u64 * pval)
1760 // TODO: unimplemented DBRs return a reserved register fault
1761 u64 val = ia64_get_dbr(reg);
1762 *pval = val;
1763 return IA64_NO_FAULT;
1766 IA64FAULT vcpu_get_ibr(VCPU * vcpu, u64 reg, u64 * pval)
1768 // TODO: unimplemented IBRs return a reserved register fault
1769 u64 val = ia64_get_ibr(reg);
1770 *pval = val;
1771 return IA64_NO_FAULT;
1774 /**************************************************************************
1775 VCPU performance monitor register access routines
1776 **************************************************************************/
1778 IA64FAULT vcpu_set_pmc(VCPU * vcpu, u64 reg, u64 val)
1780 // TODO: Should set Logical CPU state, not just physical
1781 // NOTE: Writes to unimplemented PMC registers are discarded
1782 #ifdef DEBUG_PFMON
1783 printk("vcpu_set_pmc(%x,%lx)\n", reg, val);
1784 #endif
1785 ia64_set_pmc(reg, val);
1786 return IA64_NO_FAULT;
1789 IA64FAULT vcpu_set_pmd(VCPU * vcpu, u64 reg, u64 val)
1791 // TODO: Should set Logical CPU state, not just physical
1792 // NOTE: Writes to unimplemented PMD registers are discarded
1793 #ifdef DEBUG_PFMON
1794 printk("vcpu_set_pmd(%x,%lx)\n", reg, val);
1795 #endif
1796 ia64_set_pmd(reg, val);
1797 return IA64_NO_FAULT;
1800 IA64FAULT vcpu_get_pmc(VCPU * vcpu, u64 reg, u64 * pval)
1802 // NOTE: Reads from unimplemented PMC registers return zero
1803 u64 val = (u64) ia64_get_pmc(reg);
1804 #ifdef DEBUG_PFMON
1805 printk("%lx=vcpu_get_pmc(%x)\n", val, reg);
1806 #endif
1807 *pval = val;
1808 return IA64_NO_FAULT;
1811 IA64FAULT vcpu_get_pmd(VCPU * vcpu, u64 reg, u64 * pval)
1813 // NOTE: Reads from unimplemented PMD registers return zero
1814 u64 val = (u64) ia64_get_pmd(reg);
1815 #ifdef DEBUG_PFMON
1816 printk("%lx=vcpu_get_pmd(%x)\n", val, reg);
1817 #endif
1818 *pval = val;
1819 return IA64_NO_FAULT;
1822 /**************************************************************************
1823 VCPU banked general register access routines
1824 **************************************************************************/
1825 #define vcpu_bsw0_unat(i,b0unat,b1unat,runat,IA64_PT_REGS_R16_SLOT) \
1826 do{ \
1827 __asm__ __volatile__ ( \
1828 ";;extr.u %0 = %3,%6,16;;\n" \
1829 "dep %1 = %0, %1, 0, 16;;\n" \
1830 "st8 [%4] = %1\n" \
1831 "extr.u %0 = %2, 16, 16;;\n" \
1832 "dep %3 = %0, %3, %6, 16;;\n" \
1833 "st8 [%5] = %3\n" \
1834 ::"r"(i),"r"(*b1unat),"r"(*b0unat),"r"(*runat),"r"(b1unat), \
1835 "r"(runat),"i"(IA64_PT_REGS_R16_SLOT):"memory"); \
1836 }while(0)
1838 IA64FAULT vcpu_bsw0(VCPU * vcpu)
1840 // TODO: Only allowed for current vcpu
1841 REGS *regs = vcpu_regs(vcpu);
1842 unsigned long *r = &regs->r16;
1843 unsigned long *b0 = &PSCB(vcpu, bank0_regs[0]);
1844 unsigned long *b1 = &PSCB(vcpu, bank1_regs[0]);
1845 unsigned long *runat = &regs->eml_unat;
1846 unsigned long *b0unat = &PSCB(vcpu, vbnat);
1847 unsigned long *b1unat = &PSCB(vcpu, vnat);
1849 unsigned long i;
1851 if (VMX_DOMAIN(vcpu)) {
1852 if (VCPU(vcpu, vpsr) & IA64_PSR_BN) {
1853 for (i = 0; i < 16; i++) {
1854 *b1++ = *r;
1855 *r++ = *b0++;
1857 vcpu_bsw0_unat(i, b0unat, b1unat, runat,
1858 IA64_PT_REGS_R16_SLOT);
1859 VCPU(vcpu, vpsr) &= ~IA64_PSR_BN;
1861 } else {
1862 if (PSCB(vcpu, banknum)) {
1863 for (i = 0; i < 16; i++) {
1864 *b1++ = *r;
1865 *r++ = *b0++;
1867 vcpu_bsw0_unat(i, b0unat, b1unat, runat,
1868 IA64_PT_REGS_R16_SLOT);
1869 PSCB(vcpu, banknum) = 0;
1872 return IA64_NO_FAULT;
1875 #define vcpu_bsw1_unat(i, b0unat, b1unat, runat, IA64_PT_REGS_R16_SLOT) \
1876 do { \
1877 __asm__ __volatile__ (";;extr.u %0 = %3,%6,16;;\n" \
1878 "dep %1 = %0, %1, 16, 16;;\n" \
1879 "st8 [%4] = %1\n" \
1880 "extr.u %0 = %2, 0, 16;;\n" \
1881 "dep %3 = %0, %3, %6, 16;;\n" \
1882 "st8 [%5] = %3\n" \
1883 ::"r"(i), "r"(*b0unat), "r"(*b1unat), \
1884 "r"(*runat), "r"(b0unat), "r"(runat), \
1885 "i"(IA64_PT_REGS_R16_SLOT): "memory"); \
1886 } while(0)
1888 IA64FAULT vcpu_bsw1(VCPU * vcpu)
1890 // TODO: Only allowed for current vcpu
1891 REGS *regs = vcpu_regs(vcpu);
1892 unsigned long *r = &regs->r16;
1893 unsigned long *b0 = &PSCB(vcpu, bank0_regs[0]);
1894 unsigned long *b1 = &PSCB(vcpu, bank1_regs[0]);
1895 unsigned long *runat = &regs->eml_unat;
1896 unsigned long *b0unat = &PSCB(vcpu, vbnat);
1897 unsigned long *b1unat = &PSCB(vcpu, vnat);
1899 unsigned long i;
1901 if (VMX_DOMAIN(vcpu)) {
1902 if (!(VCPU(vcpu, vpsr) & IA64_PSR_BN)) {
1903 for (i = 0; i < 16; i++) {
1904 *b0++ = *r;
1905 *r++ = *b1++;
1907 vcpu_bsw1_unat(i, b0unat, b1unat, runat,
1908 IA64_PT_REGS_R16_SLOT);
1909 VCPU(vcpu, vpsr) |= IA64_PSR_BN;
1911 } else {
1912 if (!PSCB(vcpu, banknum)) {
1913 for (i = 0; i < 16; i++) {
1914 *b0++ = *r;
1915 *r++ = *b1++;
1917 vcpu_bsw1_unat(i, b0unat, b1unat, runat,
1918 IA64_PT_REGS_R16_SLOT);
1919 PSCB(vcpu, banknum) = 1;
1922 return IA64_NO_FAULT;
1925 /**************************************************************************
1926 VCPU cpuid access routines
1927 **************************************************************************/
1929 IA64FAULT vcpu_get_cpuid(VCPU * vcpu, u64 reg, u64 * pval)
1931 // FIXME: This could get called as a result of a rsvd-reg fault
1932 // if reg > 3
1933 switch (reg) {
1934 case 0:
1935 memcpy(pval, "Xen/ia64", 8);
1936 break;
1937 case 1:
1938 *pval = 0;
1939 break;
1940 case 2:
1941 *pval = 0;
1942 break;
1943 case 3:
1944 *pval = ia64_get_cpuid(3);
1945 break;
1946 case 4:
1947 *pval = ia64_get_cpuid(4);
1948 break;
1949 default:
1950 if (reg > (ia64_get_cpuid(3) & 0xff))
1951 return IA64_RSVDREG_FAULT;
1952 *pval = ia64_get_cpuid(reg);
1953 break;
1955 return IA64_NO_FAULT;
1958 /**************************************************************************
1959 VCPU region register access routines
1960 **************************************************************************/
1962 unsigned long vcpu_get_rr_ve(VCPU * vcpu, u64 vadr)
1964 ia64_rr rr;
1966 rr.rrval = PSCB(vcpu, rrs)[vadr >> 61];
1967 return rr.ve;
1970 IA64FAULT vcpu_set_rr(VCPU * vcpu, u64 reg, u64 val)
1972 PSCB(vcpu, rrs)[reg >> 61] = val;
1973 // warning: set_one_rr() does it "live"
1974 set_one_rr(reg, val);
1975 return IA64_NO_FAULT;
1978 IA64FAULT vcpu_get_rr(VCPU * vcpu, u64 reg, u64 * pval)
1980 if (VMX_DOMAIN(vcpu))
1981 *pval = VMX(vcpu, vrr[reg >> 61]);
1982 else
1983 *pval = PSCB(vcpu, rrs)[reg >> 61];
1985 return IA64_NO_FAULT;
1988 /**************************************************************************
1989 VCPU protection key register access routines
1990 **************************************************************************/
1992 IA64FAULT vcpu_get_pkr(VCPU * vcpu, u64 reg, u64 * pval)
1994 #ifndef PKR_USE_FIXED
1995 printk("vcpu_get_pkr: called, not implemented yet\n");
1996 return IA64_ILLOP_FAULT;
1997 #else
1998 u64 val = (u64) ia64_get_pkr(reg);
1999 *pval = val;
2000 return IA64_NO_FAULT;
2001 #endif
2004 IA64FAULT vcpu_set_pkr(VCPU * vcpu, u64 reg, u64 val)
2006 #ifndef PKR_USE_FIXED
2007 printk("vcpu_set_pkr: called, not implemented yet\n");
2008 return IA64_ILLOP_FAULT;
2009 #else
2010 // if (reg >= NPKRS)
2011 // return IA64_ILLOP_FAULT;
2012 vcpu->pkrs[reg] = val;
2013 ia64_set_pkr(reg, val);
2014 return IA64_NO_FAULT;
2015 #endif
2018 /**************************************************************************
2019 VCPU translation register access routines
2020 **************************************************************************/
2022 static void
2023 vcpu_set_tr_entry_rid(TR_ENTRY * trp, u64 pte,
2024 u64 itir, u64 ifa, u64 rid)
2026 u64 ps;
2027 union pte_flags new_pte;
2029 trp->itir = itir;
2030 trp->rid = rid;
2031 ps = trp->ps;
2032 new_pte.val = pte;
2033 if (new_pte.pl < 2)
2034 new_pte.pl = 2;
2035 trp->vadr = ifa & ~0xfff;
2036 if (ps > 12) { // "ignore" relevant low-order bits
2037 new_pte.ppn &= ~((1UL << (ps - 12)) - 1);
2038 trp->vadr &= ~((1UL << ps) - 1);
2041 /* Atomic write. */
2042 trp->pte.val = new_pte.val;
2045 static inline void
2046 vcpu_set_tr_entry(TR_ENTRY * trp, u64 pte, u64 itir, u64 ifa)
2048 vcpu_set_tr_entry_rid(trp, pte, itir, ifa,
2049 VCPU(current, rrs[ifa >> 61]) & RR_RID_MASK);
2052 IA64FAULT vcpu_itr_d(VCPU * vcpu, u64 slot, u64 pte,
2053 u64 itir, u64 ifa)
2055 TR_ENTRY *trp;
2057 if (slot >= NDTRS)
2058 return IA64_RSVDREG_FAULT;
2060 vcpu_purge_tr_entry(&PSCBX(vcpu, dtlb));
2062 trp = &PSCBX(vcpu, dtrs[slot]);
2063 //printk("***** itr.d: setting slot %d: ifa=%p\n",slot,ifa);
2064 vcpu_set_tr_entry(trp, pte, itir, ifa);
2065 vcpu_quick_region_set(PSCBX(vcpu, dtr_regions), ifa);
2067 /*
2068 * FIXME According to spec, vhpt should be purged, but this
2069 * incurs considerable performance loss, since it is safe for
2070 * linux not to purge vhpt, vhpt purge is disabled until a
2071 * feasible way is found.
2073 * vcpu_flush_tlb_vhpt_range(ifa & itir_mask(itir), itir_ps(itir));
2074 */
2076 return IA64_NO_FAULT;
2079 IA64FAULT vcpu_itr_i(VCPU * vcpu, u64 slot, u64 pte,
2080 u64 itir, u64 ifa)
2082 TR_ENTRY *trp;
2084 if (slot >= NITRS)
2085 return IA64_RSVDREG_FAULT;
2087 vcpu_purge_tr_entry(&PSCBX(vcpu, itlb));
2089 trp = &PSCBX(vcpu, itrs[slot]);
2090 //printk("***** itr.i: setting slot %d: ifa=%p\n",slot,ifa);
2091 vcpu_set_tr_entry(trp, pte, itir, ifa);
2092 vcpu_quick_region_set(PSCBX(vcpu, itr_regions), ifa);
2094 /*
2095 * FIXME According to spec, vhpt should be purged, but this
2096 * incurs considerable performance loss, since it is safe for
2097 * linux not to purge vhpt, vhpt purge is disabled until a
2098 * feasible way is found.
2100 * vcpu_flush_tlb_vhpt_range(ifa & itir_mask(itir), itir_ps(itir));
2101 */
2103 return IA64_NO_FAULT;
2106 IA64FAULT vcpu_set_itr(VCPU * vcpu, u64 slot, u64 pte,
2107 u64 itir, u64 ifa, u64 rid)
2109 TR_ENTRY *trp;
2111 if (slot >= NITRS)
2112 return IA64_RSVDREG_FAULT;
2113 trp = &PSCBX(vcpu, itrs[slot]);
2114 vcpu_set_tr_entry_rid(trp, pte, itir, ifa, rid);
2116 /* Recompute the itr_region. */
2117 vcpu->arch.itr_regions = 0;
2118 for (trp = vcpu->arch.itrs; trp < &vcpu->arch.itrs[NITRS]; trp++)
2119 if (trp->pte.p)
2120 vcpu_quick_region_set(vcpu->arch.itr_regions,
2121 trp->vadr);
2122 return IA64_NO_FAULT;
2125 IA64FAULT vcpu_set_dtr(VCPU * vcpu, u64 slot, u64 pte,
2126 u64 itir, u64 ifa, u64 rid)
2128 TR_ENTRY *trp;
2130 if (slot >= NDTRS)
2131 return IA64_RSVDREG_FAULT;
2132 trp = &PSCBX(vcpu, dtrs[slot]);
2133 vcpu_set_tr_entry_rid(trp, pte, itir, ifa, rid);
2135 /* Recompute the dtr_region. */
2136 vcpu->arch.dtr_regions = 0;
2137 for (trp = vcpu->arch.dtrs; trp < &vcpu->arch.dtrs[NDTRS]; trp++)
2138 if (trp->pte.p)
2139 vcpu_quick_region_set(vcpu->arch.dtr_regions,
2140 trp->vadr);
2141 return IA64_NO_FAULT;
2144 /**************************************************************************
2145 VCPU translation cache access routines
2146 **************************************************************************/
2148 void
2149 vcpu_itc_no_srlz(VCPU * vcpu, u64 IorD, u64 vaddr, u64 pte,
2150 u64 mp_pte, u64 logps, struct p2m_entry *entry)
2152 unsigned long psr;
2153 unsigned long ps = (vcpu->domain == dom0) ? logps : PAGE_SHIFT;
2155 check_xen_space_overlap("itc", vaddr, 1UL << logps);
2157 // FIXME, must be inlined or potential for nested fault here!
2158 if ((vcpu->domain == dom0) && (logps < PAGE_SHIFT))
2159 panic_domain(NULL, "vcpu_itc_no_srlz: domain trying to use "
2160 "smaller page size!\n");
2162 BUG_ON(logps > PAGE_SHIFT);
2163 vcpu_tlb_track_insert_or_dirty(vcpu, vaddr, entry);
2164 psr = ia64_clear_ic();
2165 pte &= ~(_PAGE_RV2 | _PAGE_RV1); // Mask out the reserved bits.
2166 ia64_itc(IorD, vaddr, pte, ps); // FIXME: look for bigger mappings
2167 ia64_set_psr(psr);
2168 // ia64_srlz_i(); // no srls req'd, will rfi later
2169 #ifdef VHPT_GLOBAL
2170 if (vcpu->domain == dom0 && ((vaddr >> 61) == 7)) {
2171 // FIXME: this is dangerous... vhpt_flush_address ensures these
2172 // addresses never get flushed. More work needed if this
2173 // ever happens.
2174 //printk("vhpt_insert(%p,%p,%p)\n",vaddr,pte,1L<<logps);
2175 if (logps > PAGE_SHIFT)
2176 vhpt_multiple_insert(vaddr, pte, logps);
2177 else
2178 vhpt_insert(vaddr, pte, logps << 2);
2180 // even if domain pagesize is larger than PAGE_SIZE, just put
2181 // PAGE_SIZE mapping in the vhpt for now, else purging is complicated
2182 else
2183 vhpt_insert(vaddr, pte, PAGE_SHIFT << 2);
2184 #endif
2187 IA64FAULT vcpu_itc_d(VCPU * vcpu, u64 pte, u64 itir, u64 ifa)
2189 unsigned long pteval, logps = itir_ps(itir);
2190 BOOLEAN swap_rr0 = (!(ifa >> 61) && PSCB(vcpu, metaphysical_mode));
2191 struct p2m_entry entry;
2193 if (logps < PAGE_SHIFT)
2194 panic_domain(NULL, "vcpu_itc_d: domain trying to use "
2195 "smaller page size!\n");
2197 again:
2198 //itir = (itir & ~0xfc) | (PAGE_SHIFT<<2); // ignore domain's pagesize
2199 pteval = translate_domain_pte(pte, ifa, itir, &logps, &entry);
2200 if (!pteval)
2201 return IA64_ILLOP_FAULT;
2202 if (swap_rr0)
2203 set_one_rr(0x0, PSCB(vcpu, rrs[0]));
2204 vcpu_itc_no_srlz(vcpu, 2, ifa, pteval, pte, logps, &entry);
2205 if (swap_rr0)
2206 set_metaphysical_rr0();
2207 if (p2m_entry_retry(&entry)) {
2208 vcpu_flush_tlb_vhpt_range(ifa, logps);
2209 goto again;
2211 vcpu_set_tr_entry(&PSCBX(vcpu, dtlb), pte, itir, ifa);
2212 return IA64_NO_FAULT;
2215 IA64FAULT vcpu_itc_i(VCPU * vcpu, u64 pte, u64 itir, u64 ifa)
2217 unsigned long pteval, logps = itir_ps(itir);
2218 BOOLEAN swap_rr0 = (!(ifa >> 61) && PSCB(vcpu, metaphysical_mode));
2219 struct p2m_entry entry;
2221 if (logps < PAGE_SHIFT)
2222 panic_domain(NULL, "vcpu_itc_i: domain trying to use "
2223 "smaller page size!\n");
2224 again:
2225 //itir = (itir & ~0xfc) | (PAGE_SHIFT<<2); // ignore domain's pagesize
2226 pteval = translate_domain_pte(pte, ifa, itir, &logps, &entry);
2227 if (!pteval)
2228 return IA64_ILLOP_FAULT;
2229 if (swap_rr0)
2230 set_one_rr(0x0, PSCB(vcpu, rrs[0]));
2231 vcpu_itc_no_srlz(vcpu, 1, ifa, pteval, pte, logps, &entry);
2232 if (swap_rr0)
2233 set_metaphysical_rr0();
2234 if (p2m_entry_retry(&entry)) {
2235 vcpu_flush_tlb_vhpt_range(ifa, logps);
2236 goto again;
2238 vcpu_set_tr_entry(&PSCBX(vcpu, itlb), pte, itir, ifa);
2239 return IA64_NO_FAULT;
2242 IA64FAULT vcpu_ptc_l(VCPU * vcpu, u64 vadr, u64 log_range)
2244 BUG_ON(vcpu != current);
2246 check_xen_space_overlap("ptc_l", vadr, 1UL << log_range);
2248 /* Purge TC */
2249 vcpu_purge_tr_entry(&PSCBX(vcpu, dtlb));
2250 vcpu_purge_tr_entry(&PSCBX(vcpu, itlb));
2252 /* Purge all tlb and vhpt */
2253 vcpu_flush_tlb_vhpt_range(vadr, log_range);
2255 return IA64_NO_FAULT;
2258 // At privlvl=0, fc performs no access rights or protection key checks, while
2259 // at privlvl!=0, fc performs access rights checks as if it were a 1-byte
2260 // read but no protection key check. Thus in order to avoid an unexpected
2261 // access rights fault, we have to translate the virtual address to a
2262 // physical address (possibly via a metaphysical address) and do the fc
2263 // on the physical address, which is guaranteed to flush the same cache line
2264 IA64FAULT vcpu_fc(VCPU * vcpu, u64 vadr)
2266 // TODO: Only allowed for current vcpu
2267 u64 mpaddr, paddr;
2268 IA64FAULT fault;
2270 again:
2271 fault = vcpu_tpa(vcpu, vadr, &mpaddr);
2272 if (fault == IA64_NO_FAULT) {
2273 struct p2m_entry entry;
2274 paddr = translate_domain_mpaddr(mpaddr, &entry);
2275 ia64_fc(__va(paddr));
2276 if (p2m_entry_retry(&entry))
2277 goto again;
2279 return fault;
2282 IA64FAULT vcpu_ptc_e(VCPU * vcpu, u64 vadr)
2284 // Note that this only needs to be called once, i.e. the
2285 // architected loop to purge the entire TLB, should use
2286 // base = stride1 = stride2 = 0, count0 = count 1 = 1
2288 vcpu_flush_vtlb_all(current);
2290 return IA64_NO_FAULT;
2293 IA64FAULT vcpu_ptc_g(VCPU * vcpu, u64 vadr, u64 addr_range)
2295 printk("vcpu_ptc_g: called, not implemented yet\n");
2296 return IA64_ILLOP_FAULT;
2299 IA64FAULT vcpu_ptc_ga(VCPU * vcpu, u64 vadr, u64 addr_range)
2301 // FIXME: validate not flushing Xen addresses
2302 // if (Xen address) return(IA64_ILLOP_FAULT);
2303 // FIXME: ??breaks if domain PAGE_SIZE < Xen PAGE_SIZE
2304 //printk("######## vcpu_ptc_ga(%p,%p) ##############\n",vadr,addr_range);
2306 check_xen_space_overlap("ptc_ga", vadr, addr_range);
2308 domain_flush_vtlb_range(vcpu->domain, vadr, addr_range);
2310 return IA64_NO_FAULT;
2313 IA64FAULT vcpu_ptr_d(VCPU * vcpu, u64 vadr, u64 log_range)
2315 unsigned long region = vadr >> 61;
2316 u64 addr_range = 1UL << log_range;
2317 unsigned long rid, rr;
2318 int i;
2319 TR_ENTRY *trp;
2321 BUG_ON(vcpu != current);
2322 check_xen_space_overlap("ptr_d", vadr, 1UL << log_range);
2324 rr = PSCB(vcpu, rrs)[region];
2325 rid = rr & RR_RID_MASK;
2327 /* Purge TC */
2328 vcpu_purge_tr_entry(&PSCBX(vcpu, dtlb));
2330 /* Purge tr and recompute dtr_regions. */
2331 vcpu->arch.dtr_regions = 0;
2332 for (trp = vcpu->arch.dtrs, i = NDTRS; i; i--, trp++)
2333 if (vcpu_match_tr_entry_range
2334 (trp, rid, vadr, vadr + addr_range))
2335 vcpu_purge_tr_entry(trp);
2336 else if (trp->pte.p)
2337 vcpu_quick_region_set(vcpu->arch.dtr_regions,
2338 trp->vadr);
2340 vcpu_flush_tlb_vhpt_range(vadr, log_range);
2342 return IA64_NO_FAULT;
2345 IA64FAULT vcpu_ptr_i(VCPU * vcpu, u64 vadr, u64 log_range)
2347 unsigned long region = vadr >> 61;
2348 u64 addr_range = 1UL << log_range;
2349 unsigned long rid, rr;
2350 int i;
2351 TR_ENTRY *trp;
2353 BUG_ON(vcpu != current);
2354 check_xen_space_overlap("ptr_i", vadr, 1UL << log_range);
2356 rr = PSCB(vcpu, rrs)[region];
2357 rid = rr & RR_RID_MASK;
2359 /* Purge TC */
2360 vcpu_purge_tr_entry(&PSCBX(vcpu, itlb));
2362 /* Purge tr and recompute itr_regions. */
2363 vcpu->arch.itr_regions = 0;
2364 for (trp = vcpu->arch.itrs, i = NITRS; i; i--, trp++)
2365 if (vcpu_match_tr_entry_range
2366 (trp, rid, vadr, vadr + addr_range))
2367 vcpu_purge_tr_entry(trp);
2368 else if (trp->pte.p)
2369 vcpu_quick_region_set(vcpu->arch.itr_regions,
2370 trp->vadr);
2372 vcpu_flush_tlb_vhpt_range(vadr, log_range);
2374 return IA64_NO_FAULT;