ia64/xen-unstable

view extras/mini-os/include/ia64/ia64_cpu.h @ 13907:ac18d251df63

[IA64][MINIOS] Port of mini-os to ia64

ia64 specific parts of mini-os.

Minimal config:

# Kernel image file.
kernel = "mini-os.gz"
# Initial memory allocation (in megabytes) for the new domain.
memory = 64
# A name for your domain.
name = "Mini-OS"

Signed-off-by: Dietmar Hahn <dietmar.hahn@fujitsu-siemens.com>
author awilliam@xenbuild2.aw
date Thu Feb 15 13:13:36 2007 -0700 (2007-02-15)
parents
children 1fd90169f268
line source
1 /*
2 * Done by Dietmar Hahn <dietmar.hahn@fujitsu-siemens.com>
3 * This code is mostly taken from FreeBSD.
4 *
5 *
6 ****************************************************************************
7 * Copyright (c) 2000 Doug Rabson
8 * All rights reserved.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * SUCH DAMAGE.
30 *
31 */
33 #ifndef _IA64_CPU_H_
34 #define _IA64_CPU_H_
36 #include "ia64_fpu.h"
38 /*
39 * Definition of Region Register bits (RR)
40 *
41 * RR bit field positions
42 */
43 #define IA64_RR_VE 0
44 #define IA64_RR_MBZ0 1
45 #define IA64_RR_PS 2
46 #define IA64_RR_PS_LEN 6
47 #define IA64_RR_RID 8
48 #define IA64_RR_RID_LEN 24
49 #define IA64_RR_MBZ1 32
51 #define IA64_RR_IDX_POS 61
53 #define IA64_RR_VAL(size,rid) (((size) << IA64_RR_PS) | ((rid) << IA64_RR_RID))
55 /*
56 * Define Protection Key Register (PKR)
57 *
58 * PKR bit field positions
59 */
60 #define IA64_PKR_V 0
61 #define IA64_PKR_WD 1
62 #define IA64_PKR_RD 2
63 #define IA64_PKR_XD 3
64 #define IA64_PKR_MBZ0 4
65 #define IA64_PKR_KEY 8
66 #define IA64_PKR_KEY_LEN 24
67 #define IA64_PKR_MBZ1 32
69 #define IA64_PKR_VALID (1 << IA64_PKR_V)
72 /*
73 * ITIR bit field positions
74 */
76 #define IA64_ITIR_MBZ0 0
77 #define IA64_ITIR_PS 2
78 #define IA64_ITIR_PS_LEN 6
79 #define IA64_ITIR_KEY 8
80 #define IA64_ITIR_KEY_LEN 24
81 #define IA64_ITIR_MBZ1 32
82 #define IA64_ITIR_MBZ1_LEN 16
83 #define IA64_ITIR_PPN 48
84 #define IA64_ITIR_PPN_LEN 15
85 #define IA64_ITIR_MBZ2 63
87 /*
88 * Definition of PSR and IPSR bits.
89 */
90 #define IA64_PSR_BE 0x0000000000000002
91 #define IA64_PSR_UP 0x0000000000000004
92 #define IA64_PSR_AC 0x0000000000000008
93 #define IA64_PSR_MFL 0x0000000000000010
94 #define IA64_PSR_MFH_BIT 5
95 #define IA64_PSR_MFH (1 << IA64_PSR_MFH_BIT)
96 #define IA64_PSR_UMASK (IA64_PSR_BE | IA64_PSR_UP | \
97 IA64_PSR_AC | IA64_PSR_MFL | \
98 IA64_PSR_MFH)
99 #define IA64_PSR_IC_BIT 13
100 #define IA64_PSR_IC (1<<IA64_PSR_IC_BIT) /*0x0000000000002000*/
101 #define IA64_PSR_I_BIT 14
102 #define IA64_PSR_I (1<<IA64_PSR_I_BIT) /*0x0000000000004000*/
103 #define IA64_PSR_PK 0x0000000000008000
104 #define IA64_PSR_DT 0x0000000000020000
105 #define IA64_PSR_DFL 0x0000000000040000
106 #define IA64_PSR_DFH 0x0000000000080000
107 #define IA64_PSR_SP 0x0000000000100000
108 #define IA64_PSR_PP 0x0000000000200000
109 #define IA64_PSR_DI 0x0000000000400000
110 #define IA64_PSR_SI 0x0000000000800000
111 #define IA64_PSR_DB 0x0000000001000000
112 #define IA64_PSR_LP 0x0000000002000000
113 #define IA64_PSR_TB 0x0000000004000000
114 #define IA64_PSR_RT 0x0000000008000000
115 #define IA64_PSR_CPL 0x0000000300000000
116 #define IA64_PSR_CPL_KERN 0x0000000000000000
117 #define IA64_PSR_CPL_1 0x0000000100000000
118 #define IA64_PSR_CPL_2 0x0000000200000000
119 #define IA64_PSR_CPL_USER 0x0000000300000000
120 #define IA64_PSR_IS 0x0000000400000000
121 #define IA64_PSR_MC 0x0000000800000000
122 #define IA64_PSR_IT 0x0000001000000000
123 #define IA64_PSR_ID 0x0000002000000000
124 #define IA64_PSR_DA 0x0000004000000000
125 #define IA64_PSR_DD 0x0000008000000000
126 #define IA64_PSR_SS 0x0000010000000000
127 #define IA64_PSR_RI 0x0000060000000000
128 #define IA64_PSR_RI_0 0x0000000000000000
129 #define IA64_PSR_RI_1 0x0000020000000000
130 #define IA64_PSR_RI_2 0x0000040000000000
131 #define IA64_PSR_RI_SHIFT 41
132 #define IA64_PSR_ED 0x0000080000000000
133 #define IA64_PSR_BN 0x0000100000000000
134 #define IA64_PSR_IA 0x0000200000000000
137 /* Endianess of mini-os. */
138 #if defined(BIG_ENDIAN)
139 #define MOS_IA64_PSR_BE IA64_PSR_BE
140 #else
141 #define MOS_IA64_PSR_BE 0
142 #endif
144 #define STARTUP_PSR (IA64_PSR_IT | \
145 IA64_PSR_DT | IA64_PSR_RT | MOS_IA64_PSR_BE | \
146 IA64_PSR_BN | IA64_PSR_CPL_2 | IA64_PSR_AC)
148 #define MOS_SYS_PSR (IA64_PSR_IC | IA64_PSR_I | IA64_PSR_IT | \
149 IA64_PSR_DT | IA64_PSR_RT | MOS_IA64_PSR_BE | \
150 IA64_PSR_BN | IA64_PSR_CPL_2 | IA64_PSR_AC)
152 #define MOS_USR_PSR (IA64_PSR_IC | IA64_PSR_I | IA64_PSR_IT | \
153 IA64_PSR_DT | IA64_PSR_RT | MOS_IA64_PSR_BE | \
154 IA64_PSR_BN | IA64_PSR_CPL_USER | IA64_PSR_AC)
156 /*
157 * Definition of ISR bits.
158 */
159 #define IA64_ISR_CODE 0x000000000000ffff
160 #define IA64_ISR_VECTOR 0x0000000000ff0000
161 #define IA64_ISR_X 0x0000000100000000
162 #define IA64_ISR_W 0x0000000200000000
163 #define IA64_ISR_R 0x0000000400000000
164 #define IA64_ISR_NA 0x0000000800000000
165 #define IA64_ISR_SP 0x0000001000000000
166 #define IA64_ISR_RS 0x0000002000000000
167 #define IA64_ISR_IR 0x0000004000000000
168 #define IA64_ISR_NI 0x0000008000000000
169 #define IA64_ISR_SO 0x0000010000000000
170 #define IA64_ISR_EI 0x0000060000000000
171 #define IA64_ISR_EI_0 0x0000000000000000
172 #define IA64_ISR_EI_1 0x0000020000000000
173 #define IA64_ISR_EI_2 0x0000040000000000
174 #define IA64_ISR_ED 0x0000080000000000
176 /*
177 * DCR bit positions
178 */
179 #define IA64_DCR_PP 0
180 #define IA64_DCR_BE 1
181 #define IA64_DCR_LC 2
182 #define IA64_DCR_MBZ0 4
183 #define IA64_DCR_MBZ0_V 0xf
184 #define IA64_DCR_DM 8
185 #define IA64_DCR_DP 9
186 #define IA64_DCR_DK 10
187 #define IA64_DCR_DX 11
188 #define IA64_DCR_DR 12
189 #define IA64_DCR_DA 13
190 #define IA64_DCR_DD 14
191 #define IA64_DCR_DEFER_ALL 0x7f00
192 #define IA64_DCR_MBZ1 2
193 #define IA64_DCR_MBZ1_V 0xffffffffffffULL
196 /* Endianess of DCR register. */
197 #if defined(BIG_ENDIAN)
198 #define MOS_IA64_DCR_BE (1 << IA64_DCR_BE)
199 #else
200 #define MOS_IA64_DCR_BE (0 << IA64_DCR_BE)
201 #endif
203 #define IA64_DCR_DEFAULT (MOS_IA64_DCR_BE)
205 /*
206 * Vector numbers for various ia64 interrupts.
207 */
208 #define IA64_VEC_VHPT 0
209 #define IA64_VEC_ITLB 1
210 #define IA64_VEC_DTLB 2
211 #define IA64_VEC_ALT_ITLB 3
212 #define IA64_VEC_ALT_DTLB 4
213 #define IA64_VEC_NESTED_DTLB 5
214 #define IA64_VEC_IKEY_MISS 6
215 #define IA64_VEC_DKEY_MISS 7
216 #define IA64_VEC_DIRTY_BIT 8
217 #define IA64_VEC_INST_ACCESS 9
218 #define IA64_VEC_DATA_ACCESS 10
219 #define IA64_VEC_BREAK 11
220 #define IA64_VEC_EXT_INTR 12
221 #define IA64_VEC_PAGE_NOT_PRESENT 20
222 #define IA64_VEC_KEY_PERMISSION 21
223 #define IA64_VEC_INST_ACCESS_RIGHTS 22
224 #define IA64_VEC_DATA_ACCESS_RIGHTS 23
225 #define IA64_VEC_GENERAL_EXCEPTION 24
226 #define IA64_VEC_DISABLED_FP 25
227 #define IA64_VEC_NAT_CONSUMPTION 26
228 #define IA64_VEC_SPECULATION 27
229 #define IA64_VEC_DEBUG 29
230 #define IA64_VEC_UNALIGNED_REFERENCE 30
231 #define IA64_VEC_UNSUPP_DATA_REFERENCE 31
232 #define IA64_VEC_FLOATING_POINT_FAULT 32
233 #define IA64_VEC_FLOATING_POINT_TRAP 33
234 #define IA64_VEC_LOWER_PRIVILEGE_TRANSFER 34
235 #define IA64_VEC_TAKEN_BRANCH_TRAP 35
236 #define IA64_VEC_SINGLE_STEP_TRAP 36
237 #define IA64_VEC_IA32_EXCEPTION 45
238 #define IA64_VEC_IA32_INTERCEPT 46
239 #define IA64_VEC_IA32_INTERRUPT 47
241 /*
242 * Define hardware RSE Configuration Register
243 *
244 * RS Configuration (RSC) bit field positions
245 */
247 #define IA64_RSC_MODE 0
248 #define IA64_RSC_PL 2
249 #define IA64_RSC_BE 4
250 #define IA64_RSC_MBZ0 5
251 #define IA64_RSC_MBZ0_V 0x3ff
252 #define IA64_RSC_LOADRS 16
253 #define IA64_RSC_LOADRS_LEN 14
254 #define IA64_RSC_MBZ1 30
255 #define IA64_RSC_MBZ1_V 0x3ffffffffULL
257 /*
258 * RSC modes
259 */
260 #define IA64_RSC_MODE_LY (0x0) /* Lazy */
261 #define IA64_RSC_MODE_SI (0x1) /* Store intensive */
262 #define IA64_RSC_MODE_LI (0x2) /* Load intensive */
263 #define IA64_RSC_MODE_EA (0x3) /* Eager */
265 /* RSE endian mode. */
266 #if defined(BIG_ENDIAN)
267 #define MOS_IA64_RSC_BE 1 /* Big endian rse. */
268 #else
269 #define MOS_IA64_RSC_BE 0 /* Little endian rse. */
270 #endif
272 #define IA64_RSE_EAGER ((IA64_RSC_MODE_EA<<IA64_RSC_MODE) | \
273 (MOS_IA64_RSC_BE << IA64_RSC_BE) )
275 #define IA64_RSE_LAZY ((IA64_RSC_MODE_LY<<IA64_RSC_MODE) | \
276 (MOS_IA64_RSC_BE << IA64_RSC_BE) )
280 #ifndef __ASSEMBLY__
282 /* ia64 function descriptor and global pointer */
283 struct ia64_fdesc
284 {
285 uint64_t func;
286 uint64_t gp;
287 };
288 typedef struct ia64_fdesc ia64_fdesc_t;
290 #define FDESC_FUNC(fn) (((struct ia64_fdesc *) fn)->func)
291 #define FDESC_GP(fn) (((struct ia64_fdesc *) fn)->gp)
294 /*
295 * Various special ia64 instructions.
296 */
298 /*
299 * Memory Fence.
300 */
301 static __inline void
302 ia64_mf(void)
303 {
304 __asm __volatile("mf" ::: "memory");
305 }
307 static __inline void
308 ia64_mf_a(void)
309 {
310 __asm __volatile("mf.a");
311 }
313 /*
314 * Flush Cache.
315 */
316 static __inline void
317 ia64_fc(uint64_t va)
318 {
319 __asm __volatile("fc %0" :: "r"(va));
320 }
322 /*
323 * Sync instruction stream.
324 */
325 static __inline void
326 ia64_sync_i(void)
327 {
328 __asm __volatile("sync.i");
329 }
331 /*
332 * Calculate address in VHPT for va.
333 */
334 static __inline uint64_t
335 ia64_thash(uint64_t va)
336 {
337 uint64_t result;
338 __asm __volatile("thash %0=%1" : "=r" (result) : "r" (va));
339 return result;
340 }
342 /*
343 * Calculate VHPT tag for va.
344 */
345 static __inline uint64_t
346 ia64_ttag(uint64_t va)
347 {
348 uint64_t result;
349 __asm __volatile("ttag %0=%1" : "=r" (result) : "r" (va));
350 return result;
351 }
353 /*
354 * Convert virtual address to physical.
355 */
356 static __inline uint64_t
357 ia64_tpa(uint64_t va)
358 {
359 uint64_t result;
360 __asm __volatile("tpa %0=%1" : "=r" (result) : "r" (va));
361 return result;
362 }
364 /*
365 * Generate a ptc.e instruction.
366 */
367 static __inline void
368 ia64_ptc_e(uint64_t v)
369 {
370 __asm __volatile("ptc.e %0;; srlz.d;;" :: "r"(v));
371 }
373 /*
374 * Generate a ptc.g instruction.
375 */
376 static __inline void
377 ia64_ptc_g(uint64_t va, uint64_t size)
378 {
379 __asm __volatile("ptc.g %0,%1;; srlz.d;;" :: "r"(va), "r"(size<<2));
380 }
382 /*
383 * Generate a ptc.ga instruction.
384 */
385 static __inline void
386 ia64_ptc_ga(uint64_t va, uint64_t size)
387 {
388 __asm __volatile("ptc.ga %0,%1;; srlz.d;;" :: "r"(va), "r"(size<<2));
389 }
391 /*
392 * Generate a ptc.l instruction.
393 */
394 static __inline void
395 ia64_ptc_l(uint64_t va, uint64_t size)
396 {
397 __asm __volatile("ptc.l %0,%1;; srlz.d;;" :: "r"(va), "r"(size<<2));
398 }
400 /*
401 * Read the value of psr.
402 */
403 static __inline uint64_t
404 ia64_get_psr(void)
405 {
406 uint64_t result;
407 __asm __volatile("mov %0=psr;;" : "=r" (result));
408 return result;
409 }
411 static __inline void
412 ia64_set_psr(uint64_t v)
413 {
414 __asm __volatile("mov psr.l=%0" :: "r" (v));
415 }
417 static __inline void
418 ia64_srlz_d(void)
419 {
420 __asm __volatile("srlz.d;;");
421 }
423 static __inline void
424 disable_intr(void)
425 {
426 __asm __volatile ("rsm psr.ic|psr.i");
427 }
429 static __inline void
430 enable_intr(void)
431 {
432 __asm __volatile ("ssm psr.ic|psr.i");
433 }
435 /*
436 * Define accessors for application registers.
437 */
439 #define IA64_AR(name) \
440 \
441 static __inline uint64_t \
442 ia64_get_##name(void) \
443 { \
444 uint64_t result; \
445 __asm __volatile(";;mov %0=ar." #name ";;" : "=r" (result)); \
446 return result; \
447 } \
448 \
449 static __inline void \
450 ia64_set_##name(uint64_t v) \
451 { \
452 __asm __volatile("mov ar." #name "=%0" :: "r" (v)); \
453 }
455 IA64_AR(k0)
456 IA64_AR(k1)
457 IA64_AR(k2)
458 IA64_AR(k3)
459 IA64_AR(k4)
460 IA64_AR(k5)
461 IA64_AR(k6)
462 IA64_AR(k7)
464 IA64_AR(rsc)
465 IA64_AR(bsp)
466 IA64_AR(bspstore)
467 IA64_AR(rnat)
469 IA64_AR(fcr)
471 IA64_AR(eflag)
472 IA64_AR(csd)
473 IA64_AR(ssd)
474 IA64_AR(cflg)
475 IA64_AR(fsr)
476 IA64_AR(fir)
477 IA64_AR(fdr)
479 IA64_AR(ccv)
481 IA64_AR(unat)
483 IA64_AR(fpsr)
485 IA64_AR(itc)
487 IA64_AR(pfs)
488 IA64_AR(lc)
489 IA64_AR(ec)
491 /*
492 * Define accessors for control registers.
493 */
495 #define IA64_CR(name) \
496 \
497 static __inline uint64_t \
498 ia64_get_##name(void) \
499 { \
500 uint64_t result; \
501 __asm __volatile("mov %0=cr." #name : "=r" (result)); \
502 return result; \
503 } \
504 \
505 static __inline void \
506 ia64_set_##name(uint64_t v) \
507 { \
508 __asm __volatile("mov cr." #name "=%0" :: "r" (v)); \
509 }
511 IA64_CR(dcr)
512 IA64_CR(itm)
513 IA64_CR(iva)
515 IA64_CR(pta)
517 IA64_CR(ipsr)
518 IA64_CR(isr)
520 IA64_CR(iip)
521 IA64_CR(ifa)
522 IA64_CR(itir)
523 IA64_CR(iipa)
524 IA64_CR(ifs)
525 IA64_CR(iim)
526 IA64_CR(iha)
528 IA64_CR(lid)
529 IA64_CR(ivr)
530 IA64_CR(tpr)
531 IA64_CR(eoi)
532 IA64_CR(irr0)
533 IA64_CR(irr1)
534 IA64_CR(irr2)
535 IA64_CR(irr3)
536 IA64_CR(itv)
537 IA64_CR(pmv)
538 IA64_CR(cmcv)
540 IA64_CR(lrr0)
541 IA64_CR(lrr1)
543 #define IA64_GR(name) \
544 \
545 static __inline uint64_t \
546 ia64_get_##name(void) \
547 { \
548 uint64_t result; \
549 __asm __volatile("mov %0=" #name : "=r" (result)); \
550 return result; \
551 } \
552 \
553 static __inline void \
554 ia64_set_##name(uint64_t v) \
555 { \
556 __asm __volatile("mov " #name "=%0" :: "r" (v)); \
557 }
559 IA64_GR(sp)
560 IA64_GR(b0)
561 IA64_GR(r13) // tp
564 /*
565 * Write a region register.
566 */
567 static __inline void
568 ia64_set_rr(uint64_t rrbase, uint64_t v)
569 {
570 __asm __volatile("mov rr[%0]=%1;; srlz.d;;"
571 :: "r"(rrbase), "r"(v) : "memory");
572 }
574 /*
575 * Read a region register.
576 */
577 static __inline uint64_t
578 ia64_get_rr(uint64_t rrbase)
579 {
580 uint64_t v;
581 __asm __volatile("mov %1=rr[%0];;"
582 : "=r" (v) : "r"(rrbase) : "memory");
583 return v;
584 }
587 /*
588 * Read a CPUID register.
589 */
590 static __inline uint64_t
591 ia64_get_cpuid(int i)
592 {
593 uint64_t result;
594 __asm __volatile("mov %0=cpuid[%1]"
595 : "=r" (result) : "r"(i));
596 return result;
597 }
600 struct trap_frame
601 {
602 uint64_t rsc;
603 uint64_t ndirty; /* number of dirty regs */
604 uint64_t ssd;
605 uint64_t iip; /* interrupted ip */
606 uint64_t ipsr; /* interrupted psr */
607 uint64_t ifs; /* interruption func status register */
609 uint16_t trap_num; /* Trap num, index in trap_vec */
610 uint64_t cfm; /* current frame marker */
611 uint64_t pfs; /* previous function state ar64 */
612 uint64_t bsp; /* backing store pointer ar17 */
613 uint64_t rnat; /* rse nat collection ar19 */
614 uint64_t csd; /* comp and store data reg ar25 */
615 uint64_t ccv; /* comp and xchange val reg ar32 */
616 uint64_t unat; /* */
617 uint64_t fpsr; /* floating point state reg ar40 */
618 uint64_t pr; /* predicate regs 0-63 */
620 uint64_t gp; /* the gp pointer */
621 uint64_t sp; /* stack pointer */
622 uint64_t tp; /* thread pointer */
624 uint64_t r2; /* global reg 2 */
625 uint64_t r3;
626 uint64_t r8;
627 uint64_t r9;
628 uint64_t r10;
629 uint64_t r11;
630 uint64_t r14;
631 uint64_t r15;
632 uint64_t r16;
633 uint64_t r17;
634 uint64_t r18;
635 uint64_t r19;
636 uint64_t r20;
637 uint64_t r21;
638 uint64_t r22;
639 uint64_t r23;
640 uint64_t r24;
641 uint64_t r25;
642 uint64_t r26;
643 uint64_t r27;
644 uint64_t r28;
645 uint64_t r29;
646 uint64_t r30;
647 uint64_t r31;
649 uint64_t b0;
650 uint64_t b6;
651 uint64_t b7;
653 ia64_fpreg_t f6; /* floating point register 6 */
654 ia64_fpreg_t f7;
655 ia64_fpreg_t f8;
656 ia64_fpreg_t f9;
657 ia64_fpreg_t f10;
658 ia64_fpreg_t f11;
660 uint64_t ifa; /* interruption faulting address */
661 uint64_t isr; /* interruption status register */
662 uint64_t iim; /* interruption immediate register */
663 };
665 typedef struct trap_frame trap_frame_t;
668 #endif /* __ASSEMBLY__ */
670 /* Page access parameters. */
671 #define PTE_P_SHIFT 0
672 #define PTE_P 1
674 #define PTE_MA_SHIFT 2
675 #define PTE_MA_WB 0
677 #define PTE_A_SHIFT 5
678 #define PTE_A 1
679 #define PTE_D_SHIFT 6
680 #define PTE_D 1
682 #define PTE_AR_SHIFT 9
683 #define PTE_AR_R 0
684 #define PTE_AR_RX 1
685 #define PTE_AR_RW 2
686 #define PTE_AR_RWX 3
687 #define PTE_AR_R_RW 4
688 #define PTE_AR_RX_RWX 5
689 #define PTE_AR_RWX_RW 6
690 /* privilege level */
691 #define PTE_PL_SHIFT 7
692 #define PTE_PL_KERN 0 /* used for kernel */
693 /* page size */
694 #define PTE_PS_4K 12
695 #define PTE_PS_8K 13
696 #define PTE_PS_16K 14
697 #define PTE_PS_64K 16
698 #define PTE_PS_256K 18
699 #define PTE_PS_1M 20
700 #define PTE_PS_4M 22
701 #define PTE_PS_16M 24
702 #define PTE_PS_64M 26
703 #define PTE_PS_256M 28
706 /* Some offsets for ia64_pte_t. */
707 #define PTE_OFF_P 0
708 #define PTE_OFF_MA 3
709 #define PTE_OFF_A 5
710 #define PTE_OFF_D 6
711 #define PTE_OFF_PL 7
712 #define PTE_OFF_AR 9
713 #define PTE_OFF_PPN 12
714 #define PTE_OFF_ED 52
716 #if !defined(_ASM) && !defined(__ASSEMBLY__)
717 /*
718 * A short-format VHPT entry. Also matches the TLB insertion format.
719 */
720 typedef struct
721 {
722 #if defined(BIG_ENDIAN)
723 uint64_t pte_ig :11; /* bits 53..63 */
724 uint64_t pte_ed :1; /* bits 52..52 */
725 uint64_t pte_rv2:2; /* bits 50..51 */
726 uint64_t pte_ppn:38; /* bits 12..49 */
727 uint64_t pte_ar :3; /* bits 9..11 */
728 uint64_t pte_pl :2; /* bits 7..8 */
729 uint64_t pte_d :1; /* bits 6..6 */
730 uint64_t pte_a :1; /* bits 5..5 */
731 uint64_t pte_ma :3; /* bits 2..4 */
732 uint64_t pte_rv1:1; /* bits 1..1 */
733 uint64_t pte_p :1; /* bits 0..0 */
734 #else
735 uint64_t pte_p :1; /* bits 0..0 */
736 uint64_t pte_rv1:1; /* bits 1..1 */
737 uint64_t pte_ma :3; /* bits 2..4 */
738 uint64_t pte_a :1; /* bits 5..5 */
739 uint64_t pte_d :1; /* bits 6..6 */
740 uint64_t pte_pl :2; /* bits 7..8 */
741 uint64_t pte_ar :3; /* bits 9..11 */
742 uint64_t pte_ppn:38; /* bits 12..49 */
743 uint64_t pte_rv2:2; /* bits 50..51 */
744 uint64_t pte_ed :1; /* bits 52..52 */
745 uint64_t pte_ig :11; /* bits 53..63 */
746 #endif
747 } ia64_pte_t;
750 /*
751 * A long-format VHPT entry.
752 */
753 typedef struct
754 {
755 uint64_t pte_p :1; /* bits 0..0 */
756 uint64_t pte_rv1 :1; /* bits 1..1 */
757 uint64_t pte_ma :3; /* bits 2..4 */
758 uint64_t pte_a :1; /* bits 5..5 */
759 uint64_t pte_d :1; /* bits 6..6 */
760 uint64_t pte_pl :2; /* bits 7..8 */
761 uint64_t pte_ar :3; /* bits 9..11 */
762 uint64_t pte_ppn :38; /* bits 12..49 */
763 uint64_t pte_rv2 :2; /* bits 50..51 */
764 uint64_t pte_ed :1; /* bits 52..52 */
765 uint64_t pte_ig :11; /* bits 53..63 */
766 uint64_t pte_rv3 :2; /* bits 0..1 */
767 uint64_t pte_ps :6; /* bits 2..7 */
768 uint64_t pte_key :24; /* bits 8..31 */
769 uint64_t pte_rv4 :32; /* bits 32..63 */
770 uint64_t pte_tag; /* includes ti */
771 uint64_t pte_chain; /* pa of collision chain */
772 } ia64_lpte_t;
774 #endif /* __ASSEMBLY__ */
776 #endif /* _IA64_CPU_H_ */