ia64/xen-unstable

view xen/include/asm-ia64/linux-xen/asm/io.h @ 10872:aa9d157d7637

[IA64] bug fixes for recent ioports patch

Bug fixes: dom0 do not virtualize IO space, do not over-deny IO ports.

Signed-off-by: Tristan Gingold <tristan.gingold@bull.net>
author awilliam@xenbuild.aw
date Mon Jul 31 13:10:39 2006 -0600 (2006-07-31)
parents ced37bea0647
children d3f08d39e695
line source
1 #ifndef _ASM_IA64_IO_H
2 #define _ASM_IA64_IO_H
4 /*
5 * This file contains the definitions for the emulated IO instructions
6 * inb/inw/inl/outb/outw/outl and the "string versions" of the same
7 * (insb/insw/insl/outsb/outsw/outsl). You can also use "pausing"
8 * versions of the single-IO instructions (inb_p/inw_p/..).
9 *
10 * This file is not meant to be obfuscating: it's just complicated to
11 * (a) handle it all in a way that makes gcc able to optimize it as
12 * well as possible and (b) trying to avoid writing the same thing
13 * over and over again with slight variations and possibly making a
14 * mistake somewhere.
15 *
16 * Copyright (C) 1998-2003 Hewlett-Packard Co
17 * David Mosberger-Tang <davidm@hpl.hp.com>
18 * Copyright (C) 1999 Asit Mallick <asit.k.mallick@intel.com>
19 * Copyright (C) 1999 Don Dugger <don.dugger@intel.com>
20 */
22 /* We don't use IO slowdowns on the ia64, but.. */
23 #define __SLOW_DOWN_IO do { } while (0)
24 #define SLOW_DOWN_IO do { } while (0)
26 #ifdef XEN
27 #include <asm/xensystem.h>
28 #else
29 #define __IA64_UNCACHED_OFFSET 0xc000000000000000UL /* region 6 */
30 #endif
32 /*
33 * The legacy I/O space defined by the ia64 architecture supports only 65536 ports, but
34 * large machines may have multiple other I/O spaces so we can't place any a priori limit
35 * on IO_SPACE_LIMIT. These additional spaces are described in ACPI.
36 */
37 #define IO_SPACE_LIMIT 0xffffffffffffffffUL
39 #define MAX_IO_SPACES_BITS 4
40 #define MAX_IO_SPACES (1UL << MAX_IO_SPACES_BITS)
41 #define IO_SPACE_BITS 24
42 #define IO_SPACE_SIZE (1UL << IO_SPACE_BITS)
44 #define IO_SPACE_NR(port) ((port) >> IO_SPACE_BITS)
45 #define IO_SPACE_BASE(space) ((space) << IO_SPACE_BITS)
46 #define IO_SPACE_PORT(port) ((port) & (IO_SPACE_SIZE - 1))
48 #define IO_SPACE_SPARSE_ENCODING(p) ((((p) >> 2) << 12) | (p & 0xfff))
50 #ifdef XEN
51 /* Offset to IO port; do not catch error. */
52 #define IO_SPACE_SPARSE_DECODING(off) ((((off) >> 12) << 2) | (off & 0x3))
53 #define IO_SPACE_SPARSE_PORTS_PER_PAGE (0x4 << (PAGE_SHIFT - 12))
54 #endif
56 struct io_space {
57 unsigned long mmio_base; /* base in MMIO space */
58 int sparse;
59 };
61 extern struct io_space io_space[];
62 extern unsigned int num_io_spaces;
64 # ifdef __KERNEL__
66 /*
67 * All MMIO iomem cookies are in region 6; anything less is a PIO cookie:
68 * 0xCxxxxxxxxxxxxxxx MMIO cookie (return from ioremap)
69 * 0x000000001SPPPPPP PIO cookie (S=space number, P..P=port)
70 *
71 * ioread/writeX() uses the leading 1 in PIO cookies (PIO_OFFSET) to catch
72 * code that uses bare port numbers without the prerequisite pci_iomap().
73 */
74 #define PIO_OFFSET (1UL << (MAX_IO_SPACES_BITS + IO_SPACE_BITS))
75 #define PIO_MASK (PIO_OFFSET - 1)
76 #define PIO_RESERVED __IA64_UNCACHED_OFFSET
77 #define HAVE_ARCH_PIO_SIZE
79 #include <asm/intrinsics.h>
80 #include <asm/machvec.h>
81 #include <asm/page.h>
82 #include <asm/system.h>
83 #include <asm-generic/iomap.h>
85 /*
86 * Change virtual addresses to physical addresses and vv.
87 */
88 static inline unsigned long
89 virt_to_maddr (volatile void *address)
90 {
91 return (unsigned long) address - PAGE_OFFSET;
92 }
94 static inline void*
95 maddr_to_virt (unsigned long address)
96 {
97 return (void *) (address + PAGE_OFFSET);
98 }
100 #define ARCH_HAS_VALID_PHYS_ADDR_RANGE
101 extern int valid_phys_addr_range (unsigned long addr, size_t *count); /* efi.c */
103 /*
104 * The following two macros are deprecated and scheduled for removal.
105 * Please use the PCI-DMA interface defined in <asm/pci.h> instead.
106 */
107 #define bus_to_virt maddr_to_virt
108 #define virt_to_bus virt_to_maddr
109 #define page_to_bus page_to_maddr
111 # endif /* KERNEL */
113 /*
114 * Memory fence w/accept. This should never be used in code that is
115 * not IA-64 specific.
116 */
117 #define __ia64_mf_a() ia64_mfa()
119 /**
120 * ___ia64_mmiowb - I/O write barrier
121 *
122 * Ensure ordering of I/O space writes. This will make sure that writes
123 * following the barrier will arrive after all previous writes. For most
124 * ia64 platforms, this is a simple 'mf.a' instruction.
125 *
126 * See Documentation/DocBook/deviceiobook.tmpl for more information.
127 */
128 static inline void ___ia64_mmiowb(void)
129 {
130 ia64_mfa();
131 }
133 static inline void*
134 __ia64_mk_io_addr (unsigned long port)
135 {
136 struct io_space *space;
137 unsigned long offset;
139 space = &io_space[IO_SPACE_NR(port)];
140 port = IO_SPACE_PORT(port);
141 if (space->sparse)
142 offset = IO_SPACE_SPARSE_ENCODING(port);
143 else
144 offset = port;
146 return (void *) (space->mmio_base | offset);
147 }
149 #define __ia64_inb ___ia64_inb
150 #define __ia64_inw ___ia64_inw
151 #define __ia64_inl ___ia64_inl
152 #define __ia64_outb ___ia64_outb
153 #define __ia64_outw ___ia64_outw
154 #define __ia64_outl ___ia64_outl
155 #define __ia64_readb ___ia64_readb
156 #define __ia64_readw ___ia64_readw
157 #define __ia64_readl ___ia64_readl
158 #define __ia64_readq ___ia64_readq
159 #define __ia64_readb_relaxed ___ia64_readb
160 #define __ia64_readw_relaxed ___ia64_readw
161 #define __ia64_readl_relaxed ___ia64_readl
162 #define __ia64_readq_relaxed ___ia64_readq
163 #define __ia64_writeb ___ia64_writeb
164 #define __ia64_writew ___ia64_writew
165 #define __ia64_writel ___ia64_writel
166 #define __ia64_writeq ___ia64_writeq
167 #define __ia64_mmiowb ___ia64_mmiowb
169 /*
170 * For the in/out routines, we need to do "mf.a" _after_ doing the I/O access to ensure
171 * that the access has completed before executing other I/O accesses. Since we're doing
172 * the accesses through an uncachable (UC) translation, the CPU will execute them in
173 * program order. However, we still need to tell the compiler not to shuffle them around
174 * during optimization, which is why we use "volatile" pointers.
175 */
177 static inline unsigned int
178 ___ia64_inb (unsigned long port)
179 {
180 volatile unsigned char *addr = __ia64_mk_io_addr(port);
181 unsigned char ret;
183 ret = *addr;
184 __ia64_mf_a();
185 return ret;
186 }
188 static inline unsigned int
189 ___ia64_inw (unsigned long port)
190 {
191 volatile unsigned short *addr = __ia64_mk_io_addr(port);
192 unsigned short ret;
194 ret = *addr;
195 __ia64_mf_a();
196 return ret;
197 }
199 static inline unsigned int
200 ___ia64_inl (unsigned long port)
201 {
202 volatile unsigned int *addr = __ia64_mk_io_addr(port);
203 unsigned int ret;
205 ret = *addr;
206 __ia64_mf_a();
207 return ret;
208 }
210 static inline void
211 ___ia64_outb (unsigned char val, unsigned long port)
212 {
213 volatile unsigned char *addr = __ia64_mk_io_addr(port);
215 *addr = val;
216 __ia64_mf_a();
217 }
219 static inline void
220 ___ia64_outw (unsigned short val, unsigned long port)
221 {
222 volatile unsigned short *addr = __ia64_mk_io_addr(port);
224 *addr = val;
225 __ia64_mf_a();
226 }
228 static inline void
229 ___ia64_outl (unsigned int val, unsigned long port)
230 {
231 volatile unsigned int *addr = __ia64_mk_io_addr(port);
233 *addr = val;
234 __ia64_mf_a();
235 }
237 static inline void
238 __insb (unsigned long port, void *dst, unsigned long count)
239 {
240 unsigned char *dp = dst;
242 while (count--)
243 *dp++ = platform_inb(port);
244 }
246 static inline void
247 __insw (unsigned long port, void *dst, unsigned long count)
248 {
249 unsigned short *dp = dst;
251 while (count--)
252 *dp++ = platform_inw(port);
253 }
255 static inline void
256 __insl (unsigned long port, void *dst, unsigned long count)
257 {
258 unsigned int *dp = dst;
260 while (count--)
261 *dp++ = platform_inl(port);
262 }
264 static inline void
265 __outsb (unsigned long port, const void *src, unsigned long count)
266 {
267 const unsigned char *sp = src;
269 while (count--)
270 platform_outb(*sp++, port);
271 }
273 static inline void
274 __outsw (unsigned long port, const void *src, unsigned long count)
275 {
276 const unsigned short *sp = src;
278 while (count--)
279 platform_outw(*sp++, port);
280 }
282 static inline void
283 __outsl (unsigned long port, const void *src, unsigned long count)
284 {
285 const unsigned int *sp = src;
287 while (count--)
288 platform_outl(*sp++, port);
289 }
291 /*
292 * Unfortunately, some platforms are broken and do not follow the IA-64 architecture
293 * specification regarding legacy I/O support. Thus, we have to make these operations
294 * platform dependent...
295 */
296 #define __inb platform_inb
297 #define __inw platform_inw
298 #define __inl platform_inl
299 #define __outb platform_outb
300 #define __outw platform_outw
301 #define __outl platform_outl
302 #define __mmiowb platform_mmiowb
304 #define inb(p) __inb(p)
305 #define inw(p) __inw(p)
306 #define inl(p) __inl(p)
307 #define insb(p,d,c) __insb(p,d,c)
308 #define insw(p,d,c) __insw(p,d,c)
309 #define insl(p,d,c) __insl(p,d,c)
310 #define outb(v,p) __outb(v,p)
311 #define outw(v,p) __outw(v,p)
312 #define outl(v,p) __outl(v,p)
313 #define outsb(p,s,c) __outsb(p,s,c)
314 #define outsw(p,s,c) __outsw(p,s,c)
315 #define outsl(p,s,c) __outsl(p,s,c)
316 #define mmiowb() __mmiowb()
318 /*
319 * The address passed to these functions are ioremap()ped already.
320 *
321 * We need these to be machine vectors since some platforms don't provide
322 * DMA coherence via PIO reads (PCI drivers and the spec imply that this is
323 * a good idea). Writes are ok though for all existing ia64 platforms (and
324 * hopefully it'll stay that way).
325 */
326 static inline unsigned char
327 ___ia64_readb (const volatile void __iomem *addr)
328 {
329 return *(volatile unsigned char __force *)addr;
330 }
332 static inline unsigned short
333 ___ia64_readw (const volatile void __iomem *addr)
334 {
335 return *(volatile unsigned short __force *)addr;
336 }
338 static inline unsigned int
339 ___ia64_readl (const volatile void __iomem *addr)
340 {
341 return *(volatile unsigned int __force *) addr;
342 }
344 static inline unsigned long
345 ___ia64_readq (const volatile void __iomem *addr)
346 {
347 return *(volatile unsigned long __force *) addr;
348 }
350 static inline void
351 __writeb (unsigned char val, volatile void __iomem *addr)
352 {
353 *(volatile unsigned char __force *) addr = val;
354 }
356 static inline void
357 __writew (unsigned short val, volatile void __iomem *addr)
358 {
359 *(volatile unsigned short __force *) addr = val;
360 }
362 static inline void
363 __writel (unsigned int val, volatile void __iomem *addr)
364 {
365 *(volatile unsigned int __force *) addr = val;
366 }
368 static inline void
369 __writeq (unsigned long val, volatile void __iomem *addr)
370 {
371 *(volatile unsigned long __force *) addr = val;
372 }
374 #define __readb platform_readb
375 #define __readw platform_readw
376 #define __readl platform_readl
377 #define __readq platform_readq
378 #define __readb_relaxed platform_readb_relaxed
379 #define __readw_relaxed platform_readw_relaxed
380 #define __readl_relaxed platform_readl_relaxed
381 #define __readq_relaxed platform_readq_relaxed
383 #define readb(a) __readb((a))
384 #define readw(a) __readw((a))
385 #define readl(a) __readl((a))
386 #define readq(a) __readq((a))
387 #define readb_relaxed(a) __readb_relaxed((a))
388 #define readw_relaxed(a) __readw_relaxed((a))
389 #define readl_relaxed(a) __readl_relaxed((a))
390 #define readq_relaxed(a) __readq_relaxed((a))
391 #define __raw_readb readb
392 #define __raw_readw readw
393 #define __raw_readl readl
394 #define __raw_readq readq
395 #define __raw_readb_relaxed readb_relaxed
396 #define __raw_readw_relaxed readw_relaxed
397 #define __raw_readl_relaxed readl_relaxed
398 #define __raw_readq_relaxed readq_relaxed
399 #define writeb(v,a) __writeb((v), (a))
400 #define writew(v,a) __writew((v), (a))
401 #define writel(v,a) __writel((v), (a))
402 #define writeq(v,a) __writeq((v), (a))
403 #define __raw_writeb writeb
404 #define __raw_writew writew
405 #define __raw_writel writel
406 #define __raw_writeq writeq
408 #ifndef inb_p
409 # define inb_p inb
410 #endif
411 #ifndef inw_p
412 # define inw_p inw
413 #endif
414 #ifndef inl_p
415 # define inl_p inl
416 #endif
418 #ifndef outb_p
419 # define outb_p outb
420 #endif
421 #ifndef outw_p
422 # define outw_p outw
423 #endif
424 #ifndef outl_p
425 # define outl_p outl
426 #endif
428 /*
429 * An "address" in IO memory space is not clearly either an integer or a pointer. We will
430 * accept both, thus the casts.
431 *
432 * On ia-64, we access the physical I/O memory space through the uncached kernel region.
433 */
434 static inline void __iomem *
435 ioremap (unsigned long offset, unsigned long size)
436 {
437 return (void __iomem *) (__IA64_UNCACHED_OFFSET | (offset));
438 }
440 static inline void
441 iounmap (volatile void __iomem *addr)
442 {
443 }
445 #define ioremap_nocache(o,s) ioremap(o,s)
447 # ifdef __KERNEL__
449 /*
450 * String version of IO memory access ops:
451 */
452 extern void memcpy_fromio(void *dst, const volatile void __iomem *src, long n);
453 extern void memcpy_toio(volatile void __iomem *dst, const void *src, long n);
454 extern void memset_io(volatile void __iomem *s, int c, long n);
456 #define dma_cache_inv(_start,_size) do { } while (0)
457 #define dma_cache_wback(_start,_size) do { } while (0)
458 #define dma_cache_wback_inv(_start,_size) do { } while (0)
460 # endif /* __KERNEL__ */
462 /*
463 * Enabling BIO_VMERGE_BOUNDARY forces us to turn off I/O MMU bypassing. It is said that
464 * BIO-level virtual merging can give up to 4% performance boost (not verified for ia64).
465 * On the other hand, we know that I/O MMU bypassing gives ~8% performance improvement on
466 * SPECweb-like workloads on zx1-based machines. Thus, for now we favor I/O MMU bypassing
467 * over BIO-level virtual merging.
468 */
469 extern unsigned long ia64_max_iommu_merge_mask;
470 #if 1
471 #define BIO_VMERGE_BOUNDARY 0
472 #else
473 /*
474 * It makes no sense at all to have this BIO_VMERGE_BOUNDARY macro here. Should be
475 * replaced by dma_merge_mask() or something of that sort. Note: the only way
476 * BIO_VMERGE_BOUNDARY is used is to mask off bits. Effectively, our definition gets
477 * expanded into:
478 *
479 * addr & ((ia64_max_iommu_merge_mask + 1) - 1) == (addr & ia64_max_iommu_vmerge_mask)
480 *
481 * which is precisely what we want.
482 */
483 #define BIO_VMERGE_BOUNDARY (ia64_max_iommu_merge_mask + 1)
484 #endif
486 #endif /* _ASM_IA64_IO_H */