ia64/xen-unstable

view xen/include/asm-ia64/serial.h @ 3851:aa7e56a968b8

bitkeeper revision 1.1218 (4214eb5c50HeO5ayekYo8U0171lEmA)

mkbuildtree, setup.c:
update to match serial changes in common
serial.h:
new file
author djm@kirby.fc.hp.com
date Thu Feb 17 19:07:08 2005 +0000 (2005-02-17)
parents
children c2364cd47a54 487de0451d2b ddd290cc8f0d
line source
1 #ifndef __ASM_SERIAL_H__
2 #define __ASM_SERIAL_H__
4 #include <asm/regs.h>
5 #include <asm/irq.h>
6 #include <xen/serial.h>
7 #include <asm/hpsim_ssc.h>
9 #if 1
10 #define arch_serial_putc(_uart, _c) \
11 ( platform_is_hp_ski() ? (ia64_ssc(c,0,0,0,SSC_PUTCHAR), 1) : \
12 ( longs_peak_putc(c), 1 ))
13 #else
14 #define arch_serial_putc(_uart, _c) \
15 ( platform_is_hp_ski() ? (ia64_ssc(c,0,0,0,SSC_PUTCHAR), 1) : \
16 ( (inb((_uart)->io_base + LSR) & LSR_THRE) ? \
17 (outb((_c), (_uart)->io_base + THR), 1) : 0 ))
18 #endif
21 #define OPT_COM1_STR "115200"
22 #define OPT_COM2_STR ""
24 /* Register offsets */
25 #define RBR 0x00 /* receive buffer */
26 #define THR 0x00 /* transmit holding */
27 #define IER 0x01 /* interrupt enable */
28 #define IIR 0x02 /* interrupt identity */
29 #define FCR 0x02 /* FIFO control */
30 #define LCR 0x03 /* line control */
31 #define MCR 0x04 /* Modem control */
32 #define LSR 0x05 /* line status */
33 #define MSR 0x06 /* Modem status */
34 #define DLL 0x00 /* divisor latch (ls) (DLAB=1) */
35 #define DLM 0x01 /* divisor latch (ms) (DLAB=1) */
37 /* Interrupt Enable Register */
38 #define IER_ERDAI 0x01 /* rx data recv'd */
39 #define IER_ETHREI 0x02 /* tx reg. empty */
40 #define IER_ELSI 0x04 /* rx line status */
41 #define IER_EMSI 0x08 /* MODEM status */
43 /* FIFO control register */
44 #define FCR_ENABLE 0x01 /* enable FIFO */
45 #define FCR_CLRX 0x02 /* clear Rx FIFO */
46 #define FCR_CLTX 0x04 /* clear Tx FIFO */
47 #define FCR_DMA 0x10 /* enter DMA mode */
48 #define FCR_TRG1 0x00 /* Rx FIFO trig lev 1 */
49 #define FCR_TRG4 0x40 /* Rx FIFO trig lev 4 */
50 #define FCR_TRG8 0x80 /* Rx FIFO trig lev 8 */
51 #define FCR_TRG14 0xc0 /* Rx FIFO trig lev 14 */
53 /* Line control register */
54 #define LCR_DLAB 0x80 /* Divisor Latch Access */
56 /* Modem Control Register */
57 #define MCR_DTR 0x01 /* Data Terminal Ready */
58 #define MCR_RTS 0x02 /* Request to Send */
59 #define MCR_OUT2 0x08 /* OUT2: interrupt mask */
61 /* Line Status Register */
62 #define LSR_DR 0x01 /* Data ready */
63 #define LSR_OE 0x02 /* Overrun */
64 #define LSR_PE 0x04 /* Parity error */
65 #define LSR_FE 0x08 /* Framing error */
66 #define LSR_BI 0x10 /* Break */
67 #define LSR_THRE 0x20 /* Xmit hold reg empty */
68 #define LSR_TEMT 0x40 /* Xmitter empty */
69 #define LSR_ERR 0x80 /* Error */
71 /* These parity settings can be ORed directly into the LCR. */
72 #define PARITY_NONE (0<<3)
73 #define PARITY_ODD (1<<3)
74 #define PARITY_EVEN (3<<3)
75 #define PARITY_MARK (5<<3)
76 #define PARITY_SPACE (7<<3)
78 #define RXBUFSZ 32
79 #define MASK_RXBUF_IDX(_i) ((_i)&(RXBUFSZ-1))
81 #define UART_ENABLED(_u) ((_u)->baud != 0)
82 #define DISABLE_UART(_u) ((_u)->baud = 0)
84 /* 'Serial handles' are comprise the following fields. */
85 #define SERHND_IDX (1<<0) /* COM1 or COM2? */
87 unsigned char irq_serial_getc(int handle);
89 void serial_force_unlock(int handle);
91 #endif /* __ASM_SERIAL_H__ */