ia64/xen-unstable

view xen/include/asm-x86/apicdef.h @ 6552:a9873d384da4

Merge.
author adsharma@los-vmm.sc.intel.com
date Thu Aug 25 12:24:48 2005 -0700 (2005-08-25)
parents 112d44270733 fa0754a9f64f
children dfaf788ab18c
line source
1 #ifndef __ASM_APICDEF_H
2 #define __ASM_APICDEF_H
4 /*
5 * Constants for various Intel APICs. (local APIC, IOAPIC, etc.)
6 *
7 * Alan Cox <Alan.Cox@linux.org>, 1995.
8 * Ingo Molnar <mingo@redhat.com>, 1999, 2000
9 */
11 #define APIC_DEFAULT_PHYS_BASE 0xfee00000
13 #define APIC_ID 0x20
14 #define APIC_LVR 0x30
15 #define APIC_LVR_MASK 0xFF00FF
16 #define GET_APIC_VERSION(x) ((x)&0xFF)
17 #define GET_APIC_MAXLVT(x) (((x)>>16)&0xFF)
18 #define APIC_INTEGRATED(x) ((x)&0xF0)
19 #define APIC_TASKPRI 0x80
20 #define APIC_TPRI_MASK 0xFF
21 #define APIC_ARBPRI 0x90
22 #define APIC_ARBPRI_MASK 0xFF
23 #define APIC_PROCPRI 0xA0
24 #define APIC_EOI 0xB0
25 #define APIC_EIO_ACK 0x0 /* Write this to the EOI register */
26 #define APIC_RRR 0xC0
27 #define APIC_LDR 0xD0
28 #define APIC_LDR_MASK (0xFF<<24)
29 #define GET_APIC_LOGICAL_ID(x) (((x)>>24)&0xFF)
30 #define SET_APIC_LOGICAL_ID(x) (((x)<<24))
31 #define APIC_ALL_CPUS 0xFF
32 #define APIC_DFR 0xE0
33 #define APIC_DFR_CLUSTER 0x0FFFFFFFul
34 #define APIC_DFR_FLAT 0xFFFFFFFFul
35 #define APIC_SPIV 0xF0
36 #define APIC_SPIV_FOCUS_DISABLED (1<<9)
37 #define APIC_SPIV_APIC_ENABLED (1<<8)
38 #define APIC_ISR 0x100
39 #define APIC_TMR 0x180
40 #define APIC_IRR 0x200
41 #define APIC_ESR 0x280
42 #define APIC_ESR_SEND_CS 0x00001
43 #define APIC_ESR_RECV_CS 0x00002
44 #define APIC_ESR_SEND_ACC 0x00004
45 #define APIC_ESR_RECV_ACC 0x00008
46 #define APIC_ESR_SENDILL 0x00020
47 #define APIC_ESR_RECVILL 0x00040
48 #define APIC_ESR_ILLREGA 0x00080
49 #define APIC_ICR 0x300
50 #define APIC_DEST_SELF 0x40000
51 #define APIC_DEST_ALLINC 0x80000
52 #define APIC_DEST_ALLBUT 0xC0000
53 #define APIC_ICR_RR_MASK 0x30000
54 #define APIC_ICR_RR_INVALID 0x00000
55 #define APIC_ICR_RR_INPROG 0x10000
56 #define APIC_ICR_RR_VALID 0x20000
57 #define APIC_INT_LEVELTRIG 0x08000
58 #define APIC_INT_ASSERT 0x04000
59 #define APIC_ICR_BUSY 0x01000
60 #define APIC_DEST_LOGICAL 0x00800
61 #define APIC_DM_FIXED 0x00000
62 #define APIC_DM_LOWEST 0x00100
63 #define APIC_DM_SMI 0x00200
64 #define APIC_DM_REMRD 0x00300
65 #define APIC_DM_NMI 0x00400
66 #define APIC_DM_INIT 0x00500
67 #define APIC_DM_STARTUP 0x00600
68 #define APIC_DM_EXTINT 0x00700
69 #define APIC_VECTOR_MASK 0x000FF
70 #define APIC_ICR2 0x310
71 #define GET_APIC_DEST_FIELD(x) (((x)>>24)&0xFF)
72 #define SET_APIC_DEST_FIELD(x) ((x)<<24)
73 #define APIC_LVTT 0x320
74 #define APIC_LVTTHMR 0x330
75 #define APIC_LVTPC 0x340
76 #define APIC_LVT0 0x350
77 #define APIC_LVT_TIMER_BASE_MASK (0x3<<18)
78 #define GET_APIC_TIMER_BASE(x) (((x)>>18)&0x3)
79 #define SET_APIC_TIMER_BASE(x) (((x)<<18))
80 #define APIC_TIMER_BASE_CLKIN 0x0
81 #define APIC_TIMER_BASE_TMBASE 0x1
82 #define APIC_TIMER_BASE_DIV 0x2
83 #define APIC_LVT_TIMER_PERIODIC (1<<17)
84 #define APIC_LVT_MASKED (1<<16)
85 #define APIC_LVT_LEVEL_TRIGGER (1<<15)
86 #define APIC_LVT_REMOTE_IRR (1<<14)
87 #define APIC_INPUT_POLARITY (1<<13)
88 #define APIC_SEND_PENDING (1<<12)
89 #define GET_APIC_DELIVERY_MODE(x) (((x)>>8)&0x7)
90 #define SET_APIC_DELIVERY_MODE(x,y) (((x)&~0x700)|((y)<<8))
91 #define APIC_MODE_FIXED 0x0
92 #define APIC_MODE_NMI 0x4
93 #define APIC_MODE_EXINT 0x7
94 #define APIC_LVT1 0x360
95 #define APIC_LVTERR 0x370
96 #define APIC_TMICT 0x380
97 #define APIC_TMCCT 0x390
98 #define APIC_TDCR 0x3E0
99 #define APIC_TDR_DIV_TMBASE (1<<2)
100 #define APIC_TDR_DIV_1 0xB
101 #define APIC_TDR_DIV_2 0x0
102 #define APIC_TDR_DIV_4 0x1
103 #define APIC_TDR_DIV_8 0x2
104 #define APIC_TDR_DIV_16 0x3
105 #define APIC_TDR_DIV_32 0x8
106 #define APIC_TDR_DIV_64 0x9
107 #define APIC_TDR_DIV_128 0xA
109 #define APIC_BASE (fix_to_virt(FIX_APIC_BASE))
111 /* These limits are dictated by ES7000 hardware. */
112 #ifdef __i386__
113 #define MAX_IO_APICS 65
114 #else
115 #define MAX_IO_APICS 129
116 #endif
118 /*
119 * the local APIC register structure, memory mapped. Not terribly well
120 * tested, but we might eventually use this one in the future - the
121 * problem why we cannot use it right now is the P5 APIC, it has an
122 * errata which cannot take 8-bit reads and writes, only 32-bit ones ...
123 */
124 #define u32 unsigned int
126 #define lapic ((volatile struct local_apic *)APIC_BASE)
128 #ifndef __ASSEMBLY__
129 struct local_apic {
131 /*000*/ struct { u32 __reserved[4]; } __reserved_01;
133 /*010*/ struct { u32 __reserved[4]; } __reserved_02;
135 /*020*/ struct { /* APIC ID Register */
136 u32 __reserved_1 : 24,
137 phys_apic_id : 4,
138 __reserved_2 : 4;
139 u32 __reserved[3];
140 } id;
142 /*030*/ const
143 struct { /* APIC Version Register */
144 u32 version : 8,
145 __reserved_1 : 8,
146 max_lvt : 8,
147 __reserved_2 : 8;
148 u32 __reserved[3];
149 } version;
151 /*040*/ struct { u32 __reserved[4]; } __reserved_03;
153 /*050*/ struct { u32 __reserved[4]; } __reserved_04;
155 /*060*/ struct { u32 __reserved[4]; } __reserved_05;
157 /*070*/ struct { u32 __reserved[4]; } __reserved_06;
159 /*080*/ struct { /* Task Priority Register */
160 u32 priority : 8,
161 __reserved_1 : 24;
162 u32 __reserved_2[3];
163 } tpr;
165 /*090*/ const
166 struct { /* Arbitration Priority Register */
167 u32 priority : 8,
168 __reserved_1 : 24;
169 u32 __reserved_2[3];
170 } apr;
172 /*0A0*/ const
173 struct { /* Processor Priority Register */
174 u32 priority : 8,
175 __reserved_1 : 24;
176 u32 __reserved_2[3];
177 } ppr;
179 /*0B0*/ struct { /* End Of Interrupt Register */
180 u32 eoi;
181 u32 __reserved[3];
182 } eoi;
184 /*0C0*/ struct { u32 __reserved[4]; } __reserved_07;
186 /*0D0*/ struct { /* Logical Destination Register */
187 u32 __reserved_1 : 24,
188 logical_dest : 8;
189 u32 __reserved_2[3];
190 } ldr;
192 /*0E0*/ struct { /* Destination Format Register */
193 u32 __reserved_1 : 28,
194 model : 4;
195 u32 __reserved_2[3];
196 } dfr;
198 /*0F0*/ struct { /* Spurious Interrupt Vector Register */
199 u32 spurious_vector : 8,
200 apic_enabled : 1,
201 focus_cpu : 1,
202 __reserved_2 : 22;
203 u32 __reserved_3[3];
204 } svr;
206 /*100*/ struct { /* In Service Register */
207 /*170*/ u32 bitfield;
208 u32 __reserved[3];
209 } isr [8];
211 /*180*/ struct { /* Trigger Mode Register */
212 /*1F0*/ u32 bitfield;
213 u32 __reserved[3];
214 } tmr [8];
216 /*200*/ struct { /* Interrupt Request Register */
217 /*270*/ u32 bitfield;
218 u32 __reserved[3];
219 } irr [8];
221 /*280*/ union { /* Error Status Register */
222 struct {
223 u32 send_cs_error : 1,
224 receive_cs_error : 1,
225 send_accept_error : 1,
226 receive_accept_error : 1,
227 __reserved_1 : 1,
228 send_illegal_vector : 1,
229 receive_illegal_vector : 1,
230 illegal_register_address : 1,
231 __reserved_2 : 24;
232 u32 __reserved_3[3];
233 } error_bits;
234 struct {
235 u32 errors;
236 u32 __reserved_3[3];
237 } all_errors;
238 } esr;
240 /*290*/ struct { u32 __reserved[4]; } __reserved_08;
242 /*2A0*/ struct { u32 __reserved[4]; } __reserved_09;
244 /*2B0*/ struct { u32 __reserved[4]; } __reserved_10;
246 /*2C0*/ struct { u32 __reserved[4]; } __reserved_11;
248 /*2D0*/ struct { u32 __reserved[4]; } __reserved_12;
250 /*2E0*/ struct { u32 __reserved[4]; } __reserved_13;
252 /*2F0*/ struct { u32 __reserved[4]; } __reserved_14;
254 /*300*/ struct { /* Interrupt Command Register 1 */
255 u32 vector : 8,
256 delivery_mode : 3,
257 destination_mode : 1,
258 delivery_status : 1,
259 __reserved_1 : 1,
260 level : 1,
261 trigger : 1,
262 __reserved_2 : 2,
263 shorthand : 2,
264 __reserved_3 : 12;
265 u32 __reserved_4[3];
266 } icr1;
268 /*310*/ struct { /* Interrupt Command Register 2 */
269 union {
270 u32 __reserved_1 : 24,
271 phys_dest : 4,
272 __reserved_2 : 4;
273 u32 __reserved_3 : 24,
274 logical_dest : 8;
275 } dest;
276 u32 __reserved_4[3];
277 } icr2;
279 /*320*/ struct { /* LVT - Timer */
280 u32 vector : 8,
281 __reserved_1 : 4,
282 delivery_status : 1,
283 __reserved_2 : 3,
284 mask : 1,
285 timer_mode : 1,
286 __reserved_3 : 14;
287 u32 __reserved_4[3];
288 } lvt_timer;
290 /*330*/ struct { /* LVT - Thermal Sensor */
291 u32 vector : 8,
292 delivery_mode : 3,
293 __reserved_1 : 1,
294 delivery_status : 1,
295 __reserved_2 : 3,
296 mask : 1,
297 __reserved_3 : 15;
298 u32 __reserved_4[3];
299 } lvt_thermal;
301 /*340*/ struct { /* LVT - Performance Counter */
302 u32 vector : 8,
303 delivery_mode : 3,
304 __reserved_1 : 1,
305 delivery_status : 1,
306 __reserved_2 : 3,
307 mask : 1,
308 __reserved_3 : 15;
309 u32 __reserved_4[3];
310 } lvt_pc;
312 /*350*/ struct { /* LVT - LINT0 */
313 u32 vector : 8,
314 delivery_mode : 3,
315 __reserved_1 : 1,
316 delivery_status : 1,
317 polarity : 1,
318 remote_irr : 1,
319 trigger : 1,
320 mask : 1,
321 __reserved_2 : 15;
322 u32 __reserved_3[3];
323 } lvt_lint0;
325 /*360*/ struct { /* LVT - LINT1 */
326 u32 vector : 8,
327 delivery_mode : 3,
328 __reserved_1 : 1,
329 delivery_status : 1,
330 polarity : 1,
331 remote_irr : 1,
332 trigger : 1,
333 mask : 1,
334 __reserved_2 : 15;
335 u32 __reserved_3[3];
336 } lvt_lint1;
338 /*370*/ struct { /* LVT - Error */
339 u32 vector : 8,
340 __reserved_1 : 4,
341 delivery_status : 1,
342 __reserved_2 : 3,
343 mask : 1,
344 __reserved_3 : 15;
345 u32 __reserved_4[3];
346 } lvt_error;
348 /*380*/ struct { /* Timer Initial Count Register */
349 u32 initial_count;
350 u32 __reserved_2[3];
351 } timer_icr;
353 /*390*/ const
354 struct { /* Timer Current Count Register */
355 u32 curr_count;
356 u32 __reserved_2[3];
357 } timer_ccr;
359 /*3A0*/ struct { u32 __reserved[4]; } __reserved_16;
361 /*3B0*/ struct { u32 __reserved[4]; } __reserved_17;
363 /*3C0*/ struct { u32 __reserved[4]; } __reserved_18;
365 /*3D0*/ struct { u32 __reserved[4]; } __reserved_19;
367 /*3E0*/ struct { /* Timer Divide Configuration Register */
368 u32 divisor : 4,
369 __reserved_1 : 28;
370 u32 __reserved_2[3];
371 } timer_dcr;
373 /*3F0*/ struct { u32 __reserved[4]; } __reserved_20;
375 } __attribute__ ((packed));
376 #endif /* !__ASSEMBLY__ */
378 #undef u32
380 #endif