ia64/xen-unstable

view xen/arch/x86/io_apic.c @ 6552:a9873d384da4

Merge.
author adsharma@los-vmm.sc.intel.com
date Thu Aug 25 12:24:48 2005 -0700 (2005-08-25)
parents 112d44270733 fa0754a9f64f
children dfaf788ab18c
line source
1 /*
2 * Intel IO-APIC support for multi-Pentium hosts.
3 *
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
5 *
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
8 *
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
14 *
15 * Fixes
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
18 * and Rolf G. Tews
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
21 */
23 #include <xen/config.h>
24 #include <xen/lib.h>
25 #include <xen/init.h>
26 #include <xen/irq.h>
27 #include <xen/delay.h>
28 #include <xen/sched.h>
29 #include <xen/acpi.h>
30 #include <xen/keyhandler.h>
31 #include <asm/io.h>
32 #include <asm/mc146818rtc.h>
33 #include <asm/smp.h>
34 #include <asm/desc.h>
35 #include <mach_apic.h>
36 #include <io_ports.h>
38 #define make_8259A_irq(irq) (io_apic_irqs &= ~(1<<(irq)))
40 int (*ioapic_renumber_irq)(int ioapic, int irq);
41 atomic_t irq_mis_count;
43 static DEFINE_SPINLOCK(ioapic_lock);
45 int skip_ioapic_setup;
47 /*
48 * # of IRQ routing registers
49 */
50 int nr_ioapic_registers[MAX_IO_APICS];
52 /*
53 * Rough estimation of how many shared IRQs there are, can
54 * be changed anytime.
55 */
56 #define MAX_PLUS_SHARED_IRQS NR_IRQS
57 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
59 /*
60 * This is performance-critical, we want to do it O(1)
61 *
62 * the indexing order of this array favors 1:1 mappings
63 * between pins and IRQs.
64 */
66 static struct irq_pin_list {
67 int apic, pin, next;
68 } irq_2_pin[PIN_MAP_SIZE];
70 int vector_irq[NR_VECTORS] = { [0 ... NR_VECTORS - 1] = -1};
72 /*
73 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
74 * shared ISA-space IRQs, so we have to support them. We are super
75 * fast in the common case, and fast for shared ISA-space IRQs.
76 */
77 static void add_pin_to_irq(unsigned int irq, int apic, int pin)
78 {
79 static int first_free_entry = NR_IRQS;
80 struct irq_pin_list *entry = irq_2_pin + irq;
82 while (entry->next)
83 entry = irq_2_pin + entry->next;
85 if (entry->pin != -1) {
86 entry->next = first_free_entry;
87 entry = irq_2_pin + entry->next;
88 if (++first_free_entry >= PIN_MAP_SIZE)
89 panic("io_apic.c: whoops");
90 }
91 entry->apic = apic;
92 entry->pin = pin;
93 }
95 /*
96 * Reroute an IRQ to a different pin.
97 */
98 static void __init replace_pin_at_irq(unsigned int irq,
99 int oldapic, int oldpin,
100 int newapic, int newpin)
101 {
102 struct irq_pin_list *entry = irq_2_pin + irq;
104 while (1) {
105 if (entry->apic == oldapic && entry->pin == oldpin) {
106 entry->apic = newapic;
107 entry->pin = newpin;
108 }
109 if (!entry->next)
110 break;
111 entry = irq_2_pin + entry->next;
112 }
113 }
115 static void __modify_IO_APIC_irq (unsigned int irq, unsigned long enable, unsigned long disable)
116 {
117 struct irq_pin_list *entry = irq_2_pin + irq;
118 unsigned int pin, reg;
120 for (;;) {
121 pin = entry->pin;
122 if (pin == -1)
123 break;
124 reg = io_apic_read(entry->apic, 0x10 + pin*2);
125 reg &= ~disable;
126 reg |= enable;
127 io_apic_modify(entry->apic, 0x10 + pin*2, reg);
128 if (!entry->next)
129 break;
130 entry = irq_2_pin + entry->next;
131 }
132 }
134 /* mask = 1 */
135 static void __mask_IO_APIC_irq (unsigned int irq)
136 {
137 __modify_IO_APIC_irq(irq, 0x00010000, 0);
138 }
140 /* mask = 0 */
141 static void __unmask_IO_APIC_irq (unsigned int irq)
142 {
143 __modify_IO_APIC_irq(irq, 0, 0x00010000);
144 }
146 /* trigger = 0 */
147 static void __edge_IO_APIC_irq (unsigned int irq)
148 {
149 __modify_IO_APIC_irq(irq, 0, 0x00008000);
150 }
152 /* trigger = 1 */
153 static void __level_IO_APIC_irq (unsigned int irq)
154 {
155 __modify_IO_APIC_irq(irq, 0x00008000, 0);
156 }
158 static void mask_IO_APIC_irq (unsigned int irq)
159 {
160 unsigned long flags;
162 spin_lock_irqsave(&ioapic_lock, flags);
163 __mask_IO_APIC_irq(irq);
164 spin_unlock_irqrestore(&ioapic_lock, flags);
165 }
167 static void unmask_IO_APIC_irq (unsigned int irq)
168 {
169 unsigned long flags;
171 spin_lock_irqsave(&ioapic_lock, flags);
172 __unmask_IO_APIC_irq(irq);
173 spin_unlock_irqrestore(&ioapic_lock, flags);
174 }
176 void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
177 {
178 struct IO_APIC_route_entry entry;
179 unsigned long flags;
181 /* Check delivery_mode to be sure we're not clearing an SMI pin */
182 spin_lock_irqsave(&ioapic_lock, flags);
183 *(((int*)&entry) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
184 *(((int*)&entry) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
185 spin_unlock_irqrestore(&ioapic_lock, flags);
186 if (entry.delivery_mode == dest_SMI)
187 return;
189 /*
190 * Disable it in the IO-APIC irq-routing table:
191 */
192 memset(&entry, 0, sizeof(entry));
193 entry.mask = 1;
194 spin_lock_irqsave(&ioapic_lock, flags);
195 io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry) + 0));
196 io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry) + 1));
197 spin_unlock_irqrestore(&ioapic_lock, flags);
198 }
200 static void clear_IO_APIC (void)
201 {
202 int apic, pin;
204 for (apic = 0; apic < nr_ioapics; apic++)
205 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
206 clear_IO_APIC_pin(apic, pin);
207 }
209 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t cpumask)
210 {
211 unsigned long flags;
212 int pin;
213 struct irq_pin_list *entry = irq_2_pin + irq;
214 unsigned int apicid_value;
216 apicid_value = cpu_mask_to_apicid(cpumask);
217 /* Prepare to do the io_apic_write */
218 apicid_value = apicid_value << 24;
219 spin_lock_irqsave(&ioapic_lock, flags);
220 for (;;) {
221 pin = entry->pin;
222 if (pin == -1)
223 break;
224 io_apic_write(entry->apic, 0x10 + 1 + pin*2, apicid_value);
225 if (!entry->next)
226 break;
227 entry = irq_2_pin + entry->next;
228 }
229 spin_unlock_irqrestore(&ioapic_lock, flags);
230 }
232 /*
233 * Find the IRQ entry number of a certain pin.
234 */
235 static int find_irq_entry(int apic, int pin, int type)
236 {
237 int i;
239 for (i = 0; i < mp_irq_entries; i++)
240 if (mp_irqs[i].mpc_irqtype == type &&
241 (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
242 mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
243 mp_irqs[i].mpc_dstirq == pin)
244 return i;
246 return -1;
247 }
249 /*
250 * Find the pin to which IRQ[irq] (ISA) is connected
251 */
252 static int find_isa_irq_pin(int irq, int type)
253 {
254 int i;
256 for (i = 0; i < mp_irq_entries; i++) {
257 int lbus = mp_irqs[i].mpc_srcbus;
259 if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA ||
260 mp_bus_id_to_type[lbus] == MP_BUS_EISA ||
261 mp_bus_id_to_type[lbus] == MP_BUS_MCA ||
262 mp_bus_id_to_type[lbus] == MP_BUS_NEC98
263 ) &&
264 (mp_irqs[i].mpc_irqtype == type) &&
265 (mp_irqs[i].mpc_srcbusirq == irq))
267 return mp_irqs[i].mpc_dstirq;
268 }
269 return -1;
270 }
272 /*
273 * Find a specific PCI IRQ entry.
274 * Not an __init, possibly needed by modules
275 */
276 static int pin_2_irq(int idx, int apic, int pin);
278 /*
279 * This function currently is only a helper for the i386 smp boot process where
280 * we need to reprogram the ioredtbls to cater for the cpus which have come
281 * online so mask in all cases should simply be TARGET_CPUS
282 */
283 void __init setup_ioapic_dest(void)
284 {
285 int pin, ioapic, irq, irq_entry;
287 if (skip_ioapic_setup == 1)
288 return;
290 for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
291 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
292 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
293 if (irq_entry == -1)
294 continue;
295 irq = pin_2_irq(irq_entry, ioapic, pin);
296 set_ioapic_affinity_irq(irq, TARGET_CPUS);
297 }
299 }
300 }
302 /*
303 * EISA Edge/Level control register, ELCR
304 */
305 static int EISA_ELCR(unsigned int irq)
306 {
307 if (irq < 16) {
308 unsigned int port = 0x4d0 + (irq >> 3);
309 return (inb(port) >> (irq & 7)) & 1;
310 }
311 apic_printk(APIC_VERBOSE, KERN_INFO
312 "Broken MPtable reports ISA irq %d\n", irq);
313 return 0;
314 }
316 /* EISA interrupts are always polarity zero and can be edge or level
317 * trigger depending on the ELCR value. If an interrupt is listed as
318 * EISA conforming in the MP table, that means its trigger type must
319 * be read in from the ELCR */
321 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].mpc_srcbusirq))
322 #define default_EISA_polarity(idx) (0)
324 /* ISA interrupts are always polarity zero edge triggered,
325 * when listed as conforming in the MP table. */
327 #define default_ISA_trigger(idx) (0)
328 #define default_ISA_polarity(idx) (0)
330 /* PCI interrupts are always polarity one level triggered,
331 * when listed as conforming in the MP table. */
333 #define default_PCI_trigger(idx) (1)
334 #define default_PCI_polarity(idx) (1)
336 /* MCA interrupts are always polarity zero level triggered,
337 * when listed as conforming in the MP table. */
339 #define default_MCA_trigger(idx) (1)
340 #define default_MCA_polarity(idx) (0)
342 /* NEC98 interrupts are always polarity zero edge triggered,
343 * when listed as conforming in the MP table. */
345 #define default_NEC98_trigger(idx) (0)
346 #define default_NEC98_polarity(idx) (0)
348 static int __init MPBIOS_polarity(int idx)
349 {
350 int bus = mp_irqs[idx].mpc_srcbus;
351 int polarity;
353 /*
354 * Determine IRQ line polarity (high active or low active):
355 */
356 switch (mp_irqs[idx].mpc_irqflag & 3)
357 {
358 case 0: /* conforms, ie. bus-type dependent polarity */
359 {
360 switch (mp_bus_id_to_type[bus])
361 {
362 case MP_BUS_ISA: /* ISA pin */
363 {
364 polarity = default_ISA_polarity(idx);
365 break;
366 }
367 case MP_BUS_EISA: /* EISA pin */
368 {
369 polarity = default_EISA_polarity(idx);
370 break;
371 }
372 case MP_BUS_PCI: /* PCI pin */
373 {
374 polarity = default_PCI_polarity(idx);
375 break;
376 }
377 case MP_BUS_MCA: /* MCA pin */
378 {
379 polarity = default_MCA_polarity(idx);
380 break;
381 }
382 case MP_BUS_NEC98: /* NEC 98 pin */
383 {
384 polarity = default_NEC98_polarity(idx);
385 break;
386 }
387 default:
388 {
389 printk(KERN_WARNING "broken BIOS!!\n");
390 polarity = 1;
391 break;
392 }
393 }
394 break;
395 }
396 case 1: /* high active */
397 {
398 polarity = 0;
399 break;
400 }
401 case 2: /* reserved */
402 {
403 printk(KERN_WARNING "broken BIOS!!\n");
404 polarity = 1;
405 break;
406 }
407 case 3: /* low active */
408 {
409 polarity = 1;
410 break;
411 }
412 default: /* invalid */
413 {
414 printk(KERN_WARNING "broken BIOS!!\n");
415 polarity = 1;
416 break;
417 }
418 }
419 return polarity;
420 }
422 static int MPBIOS_trigger(int idx)
423 {
424 int bus = mp_irqs[idx].mpc_srcbus;
425 int trigger;
427 /*
428 * Determine IRQ trigger mode (edge or level sensitive):
429 */
430 switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
431 {
432 case 0: /* conforms, ie. bus-type dependent */
433 {
434 switch (mp_bus_id_to_type[bus])
435 {
436 case MP_BUS_ISA: /* ISA pin */
437 {
438 trigger = default_ISA_trigger(idx);
439 break;
440 }
441 case MP_BUS_EISA: /* EISA pin */
442 {
443 trigger = default_EISA_trigger(idx);
444 break;
445 }
446 case MP_BUS_PCI: /* PCI pin */
447 {
448 trigger = default_PCI_trigger(idx);
449 break;
450 }
451 case MP_BUS_MCA: /* MCA pin */
452 {
453 trigger = default_MCA_trigger(idx);
454 break;
455 }
456 case MP_BUS_NEC98: /* NEC 98 pin */
457 {
458 trigger = default_NEC98_trigger(idx);
459 break;
460 }
461 default:
462 {
463 printk(KERN_WARNING "broken BIOS!!\n");
464 trigger = 1;
465 break;
466 }
467 }
468 break;
469 }
470 case 1: /* edge */
471 {
472 trigger = 0;
473 break;
474 }
475 case 2: /* reserved */
476 {
477 printk(KERN_WARNING "broken BIOS!!\n");
478 trigger = 1;
479 break;
480 }
481 case 3: /* level */
482 {
483 trigger = 1;
484 break;
485 }
486 default: /* invalid */
487 {
488 printk(KERN_WARNING "broken BIOS!!\n");
489 trigger = 0;
490 break;
491 }
492 }
493 return trigger;
494 }
496 static inline int irq_polarity(int idx)
497 {
498 return MPBIOS_polarity(idx);
499 }
501 static inline int irq_trigger(int idx)
502 {
503 return MPBIOS_trigger(idx);
504 }
506 static int pin_2_irq(int idx, int apic, int pin)
507 {
508 int irq, i;
509 int bus = mp_irqs[idx].mpc_srcbus;
511 /*
512 * Debugging check, we are in big trouble if this message pops up!
513 */
514 if (mp_irqs[idx].mpc_dstirq != pin)
515 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
517 switch (mp_bus_id_to_type[bus])
518 {
519 case MP_BUS_ISA: /* ISA pin */
520 case MP_BUS_EISA:
521 case MP_BUS_MCA:
522 case MP_BUS_NEC98:
523 {
524 irq = mp_irqs[idx].mpc_srcbusirq;
525 break;
526 }
527 case MP_BUS_PCI: /* PCI pin */
528 {
529 /*
530 * PCI IRQs are mapped in order
531 */
532 i = irq = 0;
533 while (i < apic)
534 irq += nr_ioapic_registers[i++];
535 irq += pin;
537 /*
538 * For MPS mode, so far only needed by ES7000 platform
539 */
540 if (ioapic_renumber_irq)
541 irq = ioapic_renumber_irq(apic, irq);
543 break;
544 }
545 default:
546 {
547 printk(KERN_ERR "unknown bus type %d.\n",bus);
548 irq = 0;
549 break;
550 }
551 }
553 return irq;
554 }
556 static inline int IO_APIC_irq_trigger(int irq)
557 {
558 int apic, idx, pin;
560 for (apic = 0; apic < nr_ioapics; apic++) {
561 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
562 idx = find_irq_entry(apic,pin,mp_INT);
563 if ((idx != -1) && (irq == pin_2_irq(idx,apic,pin)))
564 return irq_trigger(idx);
565 }
566 }
567 /*
568 * nonexistent IRQs are edge default
569 */
570 return 0;
571 }
573 /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
574 u8 irq_vector[NR_IRQ_VECTORS];
576 int assign_irq_vector(int irq)
577 {
578 static int current_vector = FIRST_DEVICE_VECTOR, offset = 0;
580 BUG_ON(irq >= NR_IRQ_VECTORS);
581 if (irq != AUTO_ASSIGN && IO_APIC_VECTOR(irq) > 0)
582 return IO_APIC_VECTOR(irq);
583 next:
584 current_vector += 8;
586 /* Skip the hypercall vector. */
587 if (current_vector == HYPERCALL_VECTOR)
588 goto next;
590 /* Skip the Linux/BSD fast-trap vector. */
591 if (current_vector == 0x80)
592 goto next;
594 if (current_vector >= FIRST_SYSTEM_VECTOR) {
595 offset++;
596 if (!(offset%8))
597 return -ENOSPC;
598 current_vector = FIRST_DEVICE_VECTOR + offset;
599 }
601 vector_irq[current_vector] = irq;
602 if (irq != AUTO_ASSIGN)
603 IO_APIC_VECTOR(irq) = current_vector;
605 return current_vector;
606 }
608 static struct hw_interrupt_type ioapic_level_type;
609 static struct hw_interrupt_type ioapic_edge_type;
611 #define IOAPIC_AUTO -1
612 #define IOAPIC_EDGE 0
613 #define IOAPIC_LEVEL 1
615 static inline void ioapic_register_intr(int irq, int vector, unsigned long trigger)
616 {
617 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
618 trigger == IOAPIC_LEVEL)
619 irq_desc[vector].handler = &ioapic_level_type;
620 else
621 irq_desc[vector].handler = &ioapic_edge_type;
622 }
624 void __init setup_IO_APIC_irqs(void)
625 {
626 struct IO_APIC_route_entry entry;
627 int apic, pin, idx, irq, first_notcon = 1, vector;
628 unsigned long flags;
630 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
632 for (apic = 0; apic < nr_ioapics; apic++) {
633 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
635 /*
636 * add it to the IO-APIC irq-routing table:
637 */
638 memset(&entry,0,sizeof(entry));
640 entry.delivery_mode = INT_DELIVERY_MODE;
641 entry.dest_mode = INT_DEST_MODE;
642 entry.mask = 0; /* enable IRQ */
643 entry.dest.logical.logical_dest =
644 cpu_mask_to_apicid(TARGET_CPUS);
646 idx = find_irq_entry(apic,pin,mp_INT);
647 if (idx == -1) {
648 if (first_notcon) {
649 apic_printk(APIC_VERBOSE, KERN_DEBUG
650 " IO-APIC (apicid-pin) %d-%d",
651 mp_ioapics[apic].mpc_apicid,
652 pin);
653 first_notcon = 0;
654 } else
655 apic_printk(APIC_VERBOSE, ", %d-%d",
656 mp_ioapics[apic].mpc_apicid, pin);
657 continue;
658 }
660 entry.trigger = irq_trigger(idx);
661 entry.polarity = irq_polarity(idx);
663 if (irq_trigger(idx)) {
664 entry.trigger = 1;
665 entry.mask = 1;
666 }
668 irq = pin_2_irq(idx, apic, pin);
669 /*
670 * skip adding the timer int on secondary nodes, which causes
671 * a small but painful rift in the time-space continuum
672 */
673 if (multi_timer_check(apic, irq))
674 continue;
675 else
676 add_pin_to_irq(irq, apic, pin);
678 if (!apic && !IO_APIC_IRQ(irq))
679 continue;
681 if (IO_APIC_IRQ(irq)) {
682 vector = assign_irq_vector(irq);
683 entry.vector = vector;
684 ioapic_register_intr(irq, vector, IOAPIC_AUTO);
686 if (!apic && (irq < 16))
687 disable_8259A_irq(irq);
688 }
689 spin_lock_irqsave(&ioapic_lock, flags);
690 io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
691 io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
692 spin_unlock_irqrestore(&ioapic_lock, flags);
693 }
694 }
696 if (!first_notcon)
697 apic_printk(APIC_VERBOSE, " not connected.\n");
698 }
700 /*
701 * Set up the 8259A-master output pin:
702 */
703 void __init setup_ExtINT_IRQ0_pin(unsigned int pin, int vector)
704 {
705 struct IO_APIC_route_entry entry;
706 unsigned long flags;
708 memset(&entry,0,sizeof(entry));
710 disable_8259A_irq(0);
712 /* mask LVT0 */
713 apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
715 /*
716 * We use logical delivery to get the timer IRQ
717 * to the first CPU.
718 */
719 entry.dest_mode = INT_DEST_MODE;
720 entry.mask = 0; /* unmask IRQ now */
721 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
722 entry.delivery_mode = INT_DELIVERY_MODE;
723 entry.polarity = 0;
724 entry.trigger = 0;
725 entry.vector = vector;
727 /*
728 * The timer IRQ doesn't have to know that behind the
729 * scene we have a 8259A-master in AEOI mode ...
730 */
731 irq_desc[IO_APIC_VECTOR(0)].handler = &ioapic_edge_type;
733 /*
734 * Add it to the IO-APIC irq-routing table:
735 */
736 spin_lock_irqsave(&ioapic_lock, flags);
737 io_apic_write(0, 0x11+2*pin, *(((int *)&entry)+1));
738 io_apic_write(0, 0x10+2*pin, *(((int *)&entry)+0));
739 spin_unlock_irqrestore(&ioapic_lock, flags);
741 enable_8259A_irq(0);
742 }
744 static inline void UNEXPECTED_IO_APIC(void)
745 {
746 }
748 void __init __print_IO_APIC(void)
749 {
750 int apic, i;
751 union IO_APIC_reg_00 reg_00;
752 union IO_APIC_reg_01 reg_01;
753 union IO_APIC_reg_02 reg_02;
754 union IO_APIC_reg_03 reg_03;
755 unsigned long flags;
757 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
758 for (i = 0; i < nr_ioapics; i++)
759 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
760 mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
762 /*
763 * We are a bit conservative about what we expect. We have to
764 * know about every hardware change ASAP.
765 */
766 printk(KERN_INFO "testing the IO APIC.......................\n");
768 for (apic = 0; apic < nr_ioapics; apic++) {
770 spin_lock_irqsave(&ioapic_lock, flags);
771 reg_00.raw = io_apic_read(apic, 0);
772 reg_01.raw = io_apic_read(apic, 1);
773 if (reg_01.bits.version >= 0x10)
774 reg_02.raw = io_apic_read(apic, 2);
775 if (reg_01.bits.version >= 0x20)
776 reg_03.raw = io_apic_read(apic, 3);
777 spin_unlock_irqrestore(&ioapic_lock, flags);
779 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
780 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
781 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
782 printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type);
783 printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS);
784 if (reg_00.bits.ID >= get_physical_broadcast())
785 UNEXPECTED_IO_APIC();
786 if (reg_00.bits.__reserved_1 || reg_00.bits.__reserved_2)
787 UNEXPECTED_IO_APIC();
789 printk(KERN_DEBUG ".... register #01: %08X\n", reg_01.raw);
790 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
791 if ( (reg_01.bits.entries != 0x0f) && /* older (Neptune) boards */
792 (reg_01.bits.entries != 0x17) && /* typical ISA+PCI boards */
793 (reg_01.bits.entries != 0x1b) && /* Compaq Proliant boards */
794 (reg_01.bits.entries != 0x1f) && /* dual Xeon boards */
795 (reg_01.bits.entries != 0x22) && /* bigger Xeon boards */
796 (reg_01.bits.entries != 0x2E) &&
797 (reg_01.bits.entries != 0x3F)
798 )
799 UNEXPECTED_IO_APIC();
801 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
802 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
803 if ( (reg_01.bits.version != 0x01) && /* 82489DX IO-APICs */
804 (reg_01.bits.version != 0x10) && /* oldest IO-APICs */
805 (reg_01.bits.version != 0x11) && /* Pentium/Pro IO-APICs */
806 (reg_01.bits.version != 0x13) && /* Xeon IO-APICs */
807 (reg_01.bits.version != 0x20) /* Intel P64H (82806 AA) */
808 )
809 UNEXPECTED_IO_APIC();
810 if (reg_01.bits.__reserved_1 || reg_01.bits.__reserved_2)
811 UNEXPECTED_IO_APIC();
813 /*
814 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
815 * but the value of reg_02 is read as the previous read register
816 * value, so ignore it if reg_02 == reg_01.
817 */
818 if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
819 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
820 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
821 if (reg_02.bits.__reserved_1 || reg_02.bits.__reserved_2)
822 UNEXPECTED_IO_APIC();
823 }
825 /*
826 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
827 * or reg_03, but the value of reg_0[23] is read as the previous read
828 * register value, so ignore it if reg_03 == reg_0[12].
829 */
830 if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
831 reg_03.raw != reg_01.raw) {
832 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
833 printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT);
834 if (reg_03.bits.__reserved_1)
835 UNEXPECTED_IO_APIC();
836 }
838 printk(KERN_DEBUG ".... IRQ redirection table:\n");
840 printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol"
841 " Stat Dest Deli Vect: \n");
843 for (i = 0; i <= reg_01.bits.entries; i++) {
844 struct IO_APIC_route_entry entry;
846 spin_lock_irqsave(&ioapic_lock, flags);
847 *(((int *)&entry)+0) = io_apic_read(apic, 0x10+i*2);
848 *(((int *)&entry)+1) = io_apic_read(apic, 0x11+i*2);
849 spin_unlock_irqrestore(&ioapic_lock, flags);
851 printk(KERN_DEBUG " %02x %03X %02X ",
852 i,
853 entry.dest.logical.logical_dest,
854 entry.dest.physical.physical_dest
855 );
857 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
858 entry.mask,
859 entry.trigger,
860 entry.irr,
861 entry.polarity,
862 entry.delivery_status,
863 entry.dest_mode,
864 entry.delivery_mode,
865 entry.vector
866 );
867 }
868 }
869 printk(KERN_INFO "Using vector-based indexing\n");
870 printk(KERN_DEBUG "IRQ to pin mappings:\n");
871 for (i = 0; i < NR_IRQS; i++) {
872 struct irq_pin_list *entry = irq_2_pin + i;
873 if (entry->pin < 0)
874 continue;
875 printk(KERN_DEBUG "IRQ%d ", IO_APIC_VECTOR(i));
876 for (;;) {
877 printk("-> %d:%d", entry->apic, entry->pin);
878 if (!entry->next)
879 break;
880 entry = irq_2_pin + entry->next;
881 }
882 printk("\n");
883 }
885 printk(KERN_INFO ".................................... done.\n");
887 return;
888 }
890 void print_IO_APIC(void)
891 {
892 if (apic_verbosity != APIC_QUIET)
893 __print_IO_APIC();
894 }
896 void print_IO_APIC_keyhandler(unsigned char key)
897 {
898 __print_IO_APIC();
899 }
901 static void __init enable_IO_APIC(void)
902 {
903 union IO_APIC_reg_01 reg_01;
904 int i;
905 unsigned long flags;
907 for (i = 0; i < PIN_MAP_SIZE; i++) {
908 irq_2_pin[i].pin = -1;
909 irq_2_pin[i].next = 0;
910 }
912 /*
913 * The number of IO-APIC IRQ registers (== #pins):
914 */
915 for (i = 0; i < nr_ioapics; i++) {
916 spin_lock_irqsave(&ioapic_lock, flags);
917 reg_01.raw = io_apic_read(i, 1);
918 spin_unlock_irqrestore(&ioapic_lock, flags);
919 nr_ioapic_registers[i] = reg_01.bits.entries+1;
920 }
922 /*
923 * Do not trust the IO-APIC being empty at bootup
924 */
925 clear_IO_APIC();
926 }
928 /*
929 * Not an __init, needed by the reboot code
930 */
931 void disable_IO_APIC(void)
932 {
933 /*
934 * Clear the IO-APIC before rebooting:
935 */
936 clear_IO_APIC();
938 disconnect_bsp_APIC();
939 }
941 /*
942 * function to set the IO-APIC physical IDs based on the
943 * values stored in the MPC table.
944 *
945 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
946 */
948 #ifndef CONFIG_X86_NUMAQ
949 static void __init setup_ioapic_ids_from_mpc(void)
950 {
951 union IO_APIC_reg_00 reg_00;
952 physid_mask_t phys_id_present_map;
953 int apic;
954 int i;
955 unsigned char old_id;
956 unsigned long flags;
958 /*
959 * Don't check I/O APIC IDs for xAPIC systems. They have
960 * no meaning without the serial APIC bus.
961 */
962 if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL && boot_cpu_data.x86 < 15))
963 return;
965 /*
966 * This is broken; anything with a real cpu count has to
967 * circumvent this idiocy regardless.
968 */
969 phys_id_present_map = ioapic_phys_id_map(phys_cpu_present_map);
971 /*
972 * Set the IOAPIC ID to the value stored in the MPC table.
973 */
974 for (apic = 0; apic < nr_ioapics; apic++) {
976 /* Read the register 0 value */
977 spin_lock_irqsave(&ioapic_lock, flags);
978 reg_00.raw = io_apic_read(apic, 0);
979 spin_unlock_irqrestore(&ioapic_lock, flags);
981 old_id = mp_ioapics[apic].mpc_apicid;
983 if (mp_ioapics[apic].mpc_apicid >= get_physical_broadcast()) {
984 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
985 apic, mp_ioapics[apic].mpc_apicid);
986 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
987 reg_00.bits.ID);
988 mp_ioapics[apic].mpc_apicid = reg_00.bits.ID;
989 }
991 /*
992 * Sanity check, is the ID really free? Every APIC in a
993 * system must have a unique ID or we get lots of nice
994 * 'stuck on smp_invalidate_needed IPI wait' messages.
995 */
996 if (check_apicid_used(phys_id_present_map,
997 mp_ioapics[apic].mpc_apicid)) {
998 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
999 apic, mp_ioapics[apic].mpc_apicid);
1000 for (i = 0; i < get_physical_broadcast(); i++)
1001 if (!physid_isset(i, phys_id_present_map))
1002 break;
1003 if (i >= get_physical_broadcast())
1004 panic("Max APIC ID exceeded!\n");
1005 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1006 i);
1007 physid_set(i, phys_id_present_map);
1008 mp_ioapics[apic].mpc_apicid = i;
1009 } else {
1010 physid_mask_t tmp;
1011 tmp = apicid_to_cpu_present(mp_ioapics[apic].mpc_apicid);
1012 apic_printk(APIC_VERBOSE, "Setting %d in the "
1013 "phys_id_present_map\n",
1014 mp_ioapics[apic].mpc_apicid);
1015 physids_or(phys_id_present_map, phys_id_present_map, tmp);
1019 /*
1020 * We need to adjust the IRQ routing table
1021 * if the ID changed.
1022 */
1023 if (old_id != mp_ioapics[apic].mpc_apicid)
1024 for (i = 0; i < mp_irq_entries; i++)
1025 if (mp_irqs[i].mpc_dstapic == old_id)
1026 mp_irqs[i].mpc_dstapic
1027 = mp_ioapics[apic].mpc_apicid;
1029 /*
1030 * Read the right value from the MPC table and
1031 * write it into the ID register.
1032 */
1033 apic_printk(APIC_VERBOSE, KERN_INFO
1034 "...changing IO-APIC physical APIC ID to %d ...",
1035 mp_ioapics[apic].mpc_apicid);
1037 reg_00.bits.ID = mp_ioapics[apic].mpc_apicid;
1038 spin_lock_irqsave(&ioapic_lock, flags);
1039 io_apic_write(apic, 0, reg_00.raw);
1040 spin_unlock_irqrestore(&ioapic_lock, flags);
1042 /*
1043 * Sanity check
1044 */
1045 spin_lock_irqsave(&ioapic_lock, flags);
1046 reg_00.raw = io_apic_read(apic, 0);
1047 spin_unlock_irqrestore(&ioapic_lock, flags);
1048 if (reg_00.bits.ID != mp_ioapics[apic].mpc_apicid)
1049 printk("could not set ID!\n");
1050 else
1051 apic_printk(APIC_VERBOSE, " ok.\n");
1054 #else
1055 static void __init setup_ioapic_ids_from_mpc(void) { }
1056 #endif
1058 /*
1059 * There is a nasty bug in some older SMP boards, their mptable lies
1060 * about the timer IRQ. We do the following to work around the situation:
1062 * - timer IRQ defaults to IO-APIC IRQ
1063 * - if this function detects that timer IRQs are defunct, then we fall
1064 * back to ISA timer IRQs
1065 */
1066 static int __init timer_irq_works(void)
1068 unsigned long t1 = jiffies;
1070 local_irq_enable();
1071 /* Let ten ticks pass... */
1072 mdelay((10 * 1000) / HZ);
1074 /*
1075 * Expect a few ticks at least, to be sure some possible
1076 * glue logic does not lock up after one or two first
1077 * ticks in a non-ExtINT mode. Also the local APIC
1078 * might have cached one ExtINT interrupt. Finally, at
1079 * least one tick may be lost due to delays.
1080 */
1081 if (jiffies - t1 > 4)
1082 return 1;
1084 return 0;
1087 /*
1088 * In the SMP+IOAPIC case it might happen that there are an unspecified
1089 * number of pending IRQ events unhandled. These cases are very rare,
1090 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1091 * better to do it this way as thus we do not have to be aware of
1092 * 'pending' interrupts in the IRQ path, except at this point.
1093 */
1094 /*
1095 * Edge triggered needs to resend any interrupt
1096 * that was delayed but this is now handled in the device
1097 * independent code.
1098 */
1100 /*
1101 * Starting up a edge-triggered IO-APIC interrupt is
1102 * nasty - we need to make sure that we get the edge.
1103 * If it is already asserted for some reason, we need
1104 * return 1 to indicate that is was pending.
1106 * This is not complete - we should be able to fake
1107 * an edge even if it isn't on the 8259A...
1108 */
1109 static unsigned int startup_edge_ioapic_irq(unsigned int irq)
1111 int was_pending = 0;
1112 unsigned long flags;
1114 spin_lock_irqsave(&ioapic_lock, flags);
1115 if (irq < 16) {
1116 disable_8259A_irq(irq);
1117 if (i8259A_irq_pending(irq))
1118 was_pending = 1;
1120 __unmask_IO_APIC_irq(irq);
1121 spin_unlock_irqrestore(&ioapic_lock, flags);
1123 return was_pending;
1126 /*
1127 * Once we have recorded IRQ_PENDING already, we can mask the
1128 * interrupt for real. This prevents IRQ storms from unhandled
1129 * devices.
1130 */
1131 static void ack_edge_ioapic_irq(unsigned int irq)
1133 if ((irq_desc[IO_APIC_VECTOR(irq)].status & (IRQ_PENDING | IRQ_DISABLED))
1134 == (IRQ_PENDING | IRQ_DISABLED))
1135 mask_IO_APIC_irq(irq);
1136 ack_APIC_irq();
1139 /*
1140 * Level triggered interrupts can just be masked,
1141 * and shutting down and starting up the interrupt
1142 * is the same as enabling and disabling them -- except
1143 * with a startup need to return a "was pending" value.
1145 * Level triggered interrupts are special because we
1146 * do not touch any IO-APIC register while handling
1147 * them. We ack the APIC in the end-IRQ handler, not
1148 * in the start-IRQ-handler. Protection against reentrance
1149 * from the same interrupt is still provided, both by the
1150 * generic IRQ layer and by the fact that an unacked local
1151 * APIC does not accept IRQs.
1152 */
1153 static unsigned int startup_level_ioapic_irq (unsigned int irq)
1155 unmask_IO_APIC_irq(irq);
1157 return 0; /* don't check for pending */
1160 static void mask_and_ack_level_ioapic_irq (unsigned int irq)
1162 unsigned long v;
1163 int i;
1165 mask_IO_APIC_irq(irq);
1166 /*
1167 * It appears there is an erratum which affects at least version 0x11
1168 * of I/O APIC (that's the 82093AA and cores integrated into various
1169 * chipsets). Under certain conditions a level-triggered interrupt is
1170 * erroneously delivered as edge-triggered one but the respective IRR
1171 * bit gets set nevertheless. As a result the I/O unit expects an EOI
1172 * message but it will never arrive and further interrupts are blocked
1173 * from the source. The exact reason is so far unknown, but the
1174 * phenomenon was observed when two consecutive interrupt requests
1175 * from a given source get delivered to the same CPU and the source is
1176 * temporarily disabled in between.
1178 * A workaround is to simulate an EOI message manually. We achieve it
1179 * by setting the trigger mode to edge and then to level when the edge
1180 * trigger mode gets detected in the TMR of a local APIC for a
1181 * level-triggered interrupt. We mask the source for the time of the
1182 * operation to prevent an edge-triggered interrupt escaping meanwhile.
1183 * The idea is from Manfred Spraul. --macro
1184 */
1185 i = IO_APIC_VECTOR(irq);
1187 v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
1189 ack_APIC_irq();
1191 if (!(v & (1 << (i & 0x1f)))) {
1192 atomic_inc(&irq_mis_count);
1193 spin_lock(&ioapic_lock);
1194 __edge_IO_APIC_irq(irq);
1195 __level_IO_APIC_irq(irq);
1196 spin_unlock(&ioapic_lock);
1200 static void end_level_ioapic_irq (unsigned int irq)
1202 unmask_IO_APIC_irq(irq);
1205 static unsigned int startup_edge_ioapic_vector(unsigned int vector)
1207 int irq = vector_to_irq(vector);
1208 return startup_edge_ioapic_irq(irq);
1211 static void ack_edge_ioapic_vector(unsigned int vector)
1213 int irq = vector_to_irq(vector);
1214 ack_edge_ioapic_irq(irq);
1217 static unsigned int startup_level_ioapic_vector(unsigned int vector)
1219 int irq = vector_to_irq(vector);
1220 return startup_level_ioapic_irq (irq);
1223 static void mask_and_ack_level_ioapic_vector(unsigned int vector)
1225 int irq = vector_to_irq(vector);
1226 mask_and_ack_level_ioapic_irq(irq);
1229 static void end_level_ioapic_vector(unsigned int vector)
1231 int irq = vector_to_irq(vector);
1232 end_level_ioapic_irq(irq);
1235 static void mask_IO_APIC_vector(unsigned int vector)
1237 int irq = vector_to_irq(vector);
1238 mask_IO_APIC_irq(irq);
1241 static void unmask_IO_APIC_vector(unsigned int vector)
1243 int irq = vector_to_irq(vector);
1244 unmask_IO_APIC_irq(irq);
1247 static void set_ioapic_affinity_vector(
1248 unsigned int vector, cpumask_t cpu_mask)
1250 int irq = vector_to_irq(vector);
1251 set_ioapic_affinity_irq(irq, cpu_mask);
1254 static void disable_edge_ioapic_vector(unsigned int vector)
1258 static void end_edge_ioapic_vector(unsigned int vector)
1262 /*
1263 * Level and edge triggered IO-APIC interrupts need different handling,
1264 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
1265 * handled with the level-triggered descriptor, but that one has slightly
1266 * more overhead. Level-triggered interrupts cannot be handled with the
1267 * edge-triggered handler, without risking IRQ storms and other ugly
1268 * races.
1269 */
1270 static struct hw_interrupt_type ioapic_edge_type = {
1271 .typename = "IO-APIC-edge",
1272 .startup = startup_edge_ioapic_vector,
1273 .shutdown = disable_edge_ioapic_vector,
1274 .enable = unmask_IO_APIC_vector,
1275 .disable = disable_edge_ioapic_vector,
1276 .ack = ack_edge_ioapic_vector,
1277 .end = end_edge_ioapic_vector,
1278 .set_affinity = set_ioapic_affinity_vector,
1279 };
1281 static struct hw_interrupt_type ioapic_level_type = {
1282 .typename = "IO-APIC-level",
1283 .startup = startup_level_ioapic_vector,
1284 .shutdown = mask_IO_APIC_vector,
1285 .enable = unmask_IO_APIC_vector,
1286 .disable = mask_IO_APIC_vector,
1287 .ack = mask_and_ack_level_ioapic_vector,
1288 .end = end_level_ioapic_vector,
1289 .set_affinity = set_ioapic_affinity_vector,
1290 };
1292 static inline void init_IO_APIC_traps(void)
1294 int irq;
1295 for (irq = 0; irq < 16 ; irq++)
1296 if (IO_APIC_IRQ(irq) && !IO_APIC_VECTOR(irq))
1297 make_8259A_irq(irq);
1300 static void enable_lapic_vector(unsigned int vector)
1302 unsigned long v;
1304 v = apic_read(APIC_LVT0);
1305 apic_write_around(APIC_LVT0, v & ~APIC_LVT_MASKED);
1308 static void disable_lapic_vector(unsigned int vector)
1310 unsigned long v;
1312 v = apic_read(APIC_LVT0);
1313 apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED);
1316 static void ack_lapic_vector(unsigned int vector)
1318 ack_APIC_irq();
1321 static void end_lapic_vector(unsigned int vector) { /* nothing */ }
1323 static struct hw_interrupt_type lapic_irq_type = {
1324 .typename = "local-APIC-edge",
1325 .startup = NULL, /* startup_irq() not used for IRQ0 */
1326 .shutdown = NULL, /* shutdown_irq() not used for IRQ0 */
1327 .enable = enable_lapic_vector,
1328 .disable = disable_lapic_vector,
1329 .ack = ack_lapic_vector,
1330 .end = end_lapic_vector
1331 };
1333 /*
1334 * This looks a bit hackish but it's about the only one way of sending
1335 * a few INTA cycles to 8259As and any associated glue logic. ICR does
1336 * not support the ExtINT mode, unfortunately. We need to send these
1337 * cycles as some i82489DX-based boards have glue logic that keeps the
1338 * 8259A interrupt line asserted until INTA. --macro
1339 */
1340 static inline void unlock_ExtINT_logic(void)
1342 int pin, i;
1343 struct IO_APIC_route_entry entry0, entry1;
1344 unsigned char save_control, save_freq_select;
1345 unsigned long flags;
1347 pin = find_isa_irq_pin(8, mp_INT);
1348 if (pin == -1)
1349 return;
1351 spin_lock_irqsave(&ioapic_lock, flags);
1352 *(((int *)&entry0) + 1) = io_apic_read(0, 0x11 + 2 * pin);
1353 *(((int *)&entry0) + 0) = io_apic_read(0, 0x10 + 2 * pin);
1354 spin_unlock_irqrestore(&ioapic_lock, flags);
1355 clear_IO_APIC_pin(0, pin);
1357 memset(&entry1, 0, sizeof(entry1));
1359 entry1.dest_mode = 0; /* physical delivery */
1360 entry1.mask = 0; /* unmask IRQ now */
1361 entry1.dest.physical.physical_dest = hard_smp_processor_id();
1362 entry1.delivery_mode = dest_ExtINT;
1363 entry1.polarity = entry0.polarity;
1364 entry1.trigger = 0;
1365 entry1.vector = 0;
1367 spin_lock_irqsave(&ioapic_lock, flags);
1368 io_apic_write(0, 0x11 + 2 * pin, *(((int *)&entry1) + 1));
1369 io_apic_write(0, 0x10 + 2 * pin, *(((int *)&entry1) + 0));
1370 spin_unlock_irqrestore(&ioapic_lock, flags);
1372 save_control = CMOS_READ(RTC_CONTROL);
1373 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
1374 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
1375 RTC_FREQ_SELECT);
1376 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
1378 i = 100;
1379 while (i-- > 0) {
1380 mdelay(10);
1381 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
1382 i -= 10;
1385 CMOS_WRITE(save_control, RTC_CONTROL);
1386 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
1387 clear_IO_APIC_pin(0, pin);
1389 spin_lock_irqsave(&ioapic_lock, flags);
1390 io_apic_write(0, 0x11 + 2 * pin, *(((int *)&entry0) + 1));
1391 io_apic_write(0, 0x10 + 2 * pin, *(((int *)&entry0) + 0));
1392 spin_unlock_irqrestore(&ioapic_lock, flags);
1395 /*
1396 * This code may look a bit paranoid, but it's supposed to cooperate with
1397 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
1398 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
1399 * fanatically on his truly buggy board.
1400 */
1401 static inline void check_timer(void)
1403 int pin1, pin2;
1404 int vector;
1406 /*
1407 * get/set the timer IRQ vector:
1408 */
1409 disable_8259A_irq(0);
1410 vector = assign_irq_vector(0);
1412 irq_desc[IO_APIC_VECTOR(0)].action = irq_desc[LEGACY_VECTOR(0)].action;
1413 irq_desc[IO_APIC_VECTOR(0)].depth = 0;
1414 irq_desc[IO_APIC_VECTOR(0)].status &= ~IRQ_DISABLED;
1416 /*
1417 * Subtle, code in do_timer_interrupt() expects an AEOI
1418 * mode for the 8259A whenever interrupts are routed
1419 * through I/O APICs. Also IRQ0 has to be enabled in
1420 * the 8259A which implies the virtual wire has to be
1421 * disabled in the local APIC.
1422 */
1423 apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1424 init_8259A(1);
1425 timer_ack = 1;
1426 enable_8259A_irq(0);
1428 pin1 = find_isa_irq_pin(0, mp_INT);
1429 pin2 = find_isa_irq_pin(0, mp_ExtINT);
1431 printk(KERN_INFO "..TIMER: vector=0x%02X pin1=%d pin2=%d\n", vector, pin1, pin2);
1433 if (pin1 != -1) {
1434 /*
1435 * Ok, does IRQ0 through the IOAPIC work?
1436 */
1437 unmask_IO_APIC_irq(0);
1438 if (timer_irq_works()) {
1439 return;
1441 clear_IO_APIC_pin(0, pin1);
1442 printk(KERN_ERR "..MP-BIOS bug: 8254 timer not connected to IO-APIC\n");
1445 printk(KERN_INFO "...trying to set up timer (IRQ0) through the 8259A ... ");
1446 if (pin2 != -1) {
1447 printk("\n..... (found pin %d) ...", pin2);
1448 /*
1449 * legacy devices should be connected to IO APIC #0
1450 */
1451 setup_ExtINT_IRQ0_pin(pin2, vector);
1452 if (timer_irq_works()) {
1453 printk("works.\n");
1454 if (pin1 != -1)
1455 replace_pin_at_irq(0, 0, pin1, 0, pin2);
1456 else
1457 add_pin_to_irq(0, 0, pin2);
1458 return;
1460 /*
1461 * Cleanup, just in case ...
1462 */
1463 clear_IO_APIC_pin(0, pin2);
1465 printk(" failed.\n");
1467 if (nmi_watchdog == NMI_IO_APIC) {
1468 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
1469 nmi_watchdog = 0;
1472 printk(KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
1474 disable_8259A_irq(0);
1475 irq_desc[vector].handler = &lapic_irq_type;
1476 apic_write_around(APIC_LVT0, APIC_DM_FIXED | vector); /* Fixed mode */
1477 enable_8259A_irq(0);
1479 if (timer_irq_works()) {
1480 printk(" works.\n");
1481 return;
1483 apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector);
1484 printk(" failed.\n");
1486 printk(KERN_INFO "...trying to set up timer as ExtINT IRQ...");
1488 timer_ack = 0;
1489 init_8259A(0);
1490 make_8259A_irq(0);
1491 apic_write_around(APIC_LVT0, APIC_DM_EXTINT);
1493 unlock_ExtINT_logic();
1495 if (timer_irq_works()) {
1496 printk(" works.\n");
1497 return;
1499 printk(" failed :(.\n");
1500 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
1501 "report. Then try booting with the 'noapic' option");
1504 #define NR_IOAPIC_BIOSIDS 256
1505 static u8 ioapic_biosid_to_apic_enum[NR_IOAPIC_BIOSIDS];
1506 static void store_ioapic_biosid_mapping(void)
1508 u8 apic;
1509 memset(ioapic_biosid_to_apic_enum, ~0, NR_IOAPIC_BIOSIDS);
1510 for ( apic = 0; apic < nr_ioapics; apic++ )
1511 ioapic_biosid_to_apic_enum[mp_ioapics[apic].mpc_apicid] = apic;
1514 /*
1516 * IRQ's that are handled by the PIC in the MPS IOAPIC case.
1517 * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
1518 * Linux doesn't really care, as it's not actually used
1519 * for any interrupt handling anyway.
1520 */
1521 #define PIC_IRQS (1 << PIC_CASCADE_IR)
1523 void __init setup_IO_APIC(void)
1525 store_ioapic_biosid_mapping();
1527 enable_IO_APIC();
1529 if (acpi_ioapic)
1530 io_apic_irqs = ~0; /* all IRQs go through IOAPIC */
1531 else
1532 io_apic_irqs = ~PIC_IRQS;
1534 printk("ENABLING IO-APIC IRQs\n");
1536 /*
1537 * Set up IO-APIC IRQ routing.
1538 */
1539 if (!acpi_ioapic)
1540 setup_ioapic_ids_from_mpc();
1541 sync_Arb_IDs();
1542 setup_IO_APIC_irqs();
1543 init_IO_APIC_traps();
1544 check_timer();
1545 print_IO_APIC();
1547 register_keyhandler('z', print_IO_APIC_keyhandler, "print ioapic info");
1550 /* --------------------------------------------------------------------------
1551 ACPI-based IOAPIC Configuration
1552 -------------------------------------------------------------------------- */
1554 #ifdef CONFIG_ACPI_BOOT
1556 int __init io_apic_get_unique_id (int ioapic, int apic_id)
1558 union IO_APIC_reg_00 reg_00;
1559 static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
1560 physid_mask_t tmp;
1561 unsigned long flags;
1562 int i = 0;
1564 /*
1565 * The P4 platform supports up to 256 APIC IDs on two separate APIC
1566 * buses (one for LAPICs, one for IOAPICs), where predecessors only
1567 * supports up to 16 on one shared APIC bus.
1569 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
1570 * advantage of new APIC bus architecture.
1571 */
1573 if (physids_empty(apic_id_map))
1574 apic_id_map = ioapic_phys_id_map(phys_cpu_present_map);
1576 spin_lock_irqsave(&ioapic_lock, flags);
1577 reg_00.raw = io_apic_read(ioapic, 0);
1578 spin_unlock_irqrestore(&ioapic_lock, flags);
1580 if (apic_id >= get_physical_broadcast()) {
1581 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
1582 "%d\n", ioapic, apic_id, reg_00.bits.ID);
1583 apic_id = reg_00.bits.ID;
1586 /*
1587 * Every APIC in a system must have a unique ID or we get lots of nice
1588 * 'stuck on smp_invalidate_needed IPI wait' messages.
1589 */
1590 if (check_apicid_used(apic_id_map, apic_id)) {
1592 for (i = 0; i < get_physical_broadcast(); i++) {
1593 if (!check_apicid_used(apic_id_map, i))
1594 break;
1597 if (i == get_physical_broadcast())
1598 panic("Max apic_id exceeded!\n");
1600 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
1601 "trying %d\n", ioapic, apic_id, i);
1603 apic_id = i;
1606 tmp = apicid_to_cpu_present(apic_id);
1607 physids_or(apic_id_map, apic_id_map, tmp);
1609 if (reg_00.bits.ID != apic_id) {
1610 reg_00.bits.ID = apic_id;
1612 spin_lock_irqsave(&ioapic_lock, flags);
1613 io_apic_write(ioapic, 0, reg_00.raw);
1614 reg_00.raw = io_apic_read(ioapic, 0);
1615 spin_unlock_irqrestore(&ioapic_lock, flags);
1617 /* Sanity check */
1618 if (reg_00.bits.ID != apic_id)
1619 panic("IOAPIC[%d]: Unable change apic_id!\n", ioapic);
1622 apic_printk(APIC_VERBOSE, KERN_INFO
1623 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
1625 return apic_id;
1629 int __init io_apic_get_version (int ioapic)
1631 union IO_APIC_reg_01 reg_01;
1632 unsigned long flags;
1634 spin_lock_irqsave(&ioapic_lock, flags);
1635 reg_01.raw = io_apic_read(ioapic, 1);
1636 spin_unlock_irqrestore(&ioapic_lock, flags);
1638 return reg_01.bits.version;
1642 int __init io_apic_get_redir_entries (int ioapic)
1644 union IO_APIC_reg_01 reg_01;
1645 unsigned long flags;
1647 spin_lock_irqsave(&ioapic_lock, flags);
1648 reg_01.raw = io_apic_read(ioapic, 1);
1649 spin_unlock_irqrestore(&ioapic_lock, flags);
1651 return reg_01.bits.entries;
1655 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int edge_level, int active_high_low)
1657 struct IO_APIC_route_entry entry;
1658 unsigned long flags;
1660 if (!IO_APIC_IRQ(irq)) {
1661 printk(KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
1662 ioapic);
1663 return -EINVAL;
1666 /*
1667 * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
1668 * Note that we mask (disable) IRQs now -- these get enabled when the
1669 * corresponding device driver registers for this IRQ.
1670 */
1672 memset(&entry,0,sizeof(entry));
1674 entry.delivery_mode = INT_DELIVERY_MODE;
1675 entry.dest_mode = INT_DEST_MODE;
1676 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
1677 entry.trigger = edge_level;
1678 entry.polarity = active_high_low;
1679 entry.mask = 1;
1681 /*
1682 * IRQs < 16 are already in the irq_2_pin[] map
1683 */
1684 if (irq >= 16)
1685 add_pin_to_irq(irq, ioapic, pin);
1687 entry.vector = assign_irq_vector(irq);
1689 apic_printk(APIC_DEBUG, KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry "
1690 "(%d-%d -> 0x%x -> IRQ %d Mode:%i Active:%i)\n", ioapic,
1691 mp_ioapics[ioapic].mpc_apicid, pin, entry.vector, irq,
1692 edge_level, active_high_low);
1694 ioapic_register_intr(irq, entry.vector, edge_level);
1696 if (!ioapic && (irq < 16))
1697 disable_8259A_irq(irq);
1699 spin_lock_irqsave(&ioapic_lock, flags);
1700 io_apic_write(ioapic, 0x11+2*pin, *(((int *)&entry)+1));
1701 io_apic_write(ioapic, 0x10+2*pin, *(((int *)&entry)+0));
1702 spin_unlock_irqrestore(&ioapic_lock, flags);
1704 return 0;
1707 #endif /*CONFIG_ACPI_BOOT*/
1710 int ioapic_guest_read(int apicid, int address, u32 *pval)
1712 u32 val;
1713 int apicenum;
1714 union IO_APIC_reg_00 reg_00;
1715 unsigned long flags;
1717 if ( (apicid >= NR_IOAPIC_BIOSIDS) ||
1718 ((apicenum = ioapic_biosid_to_apic_enum[apicid]) >= nr_ioapics) )
1719 return -EINVAL;
1721 spin_lock_irqsave(&ioapic_lock, flags);
1722 val = io_apic_read(apicenum, address);
1723 spin_unlock_irqrestore(&ioapic_lock, flags);
1725 /* Rewrite APIC ID to what the BIOS originally specified. */
1726 if ( address == 0 )
1728 reg_00.raw = val;
1729 reg_00.bits.ID = apicid;
1730 val = reg_00.raw;
1733 *pval = val;
1734 return 0;
1737 int ioapic_guest_write(int apicid, int address, u32 val)
1739 int apicenum, pin, irq;
1740 struct IO_APIC_route_entry rte = { 0 };
1741 struct irq_pin_list *entry;
1742 unsigned long flags;
1744 if ( (apicid >= NR_IOAPIC_BIOSIDS) ||
1745 ((apicenum = ioapic_biosid_to_apic_enum[apicid]) >= nr_ioapics) )
1746 return -EINVAL;
1748 /* Only write to the first half of a route entry. */
1749 if ( (address < 0x10) || (address & 1) )
1750 return 0;
1752 pin = (address - 0x10) >> 1;
1754 *(u32 *)&rte = val;
1755 rte.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
1757 /*
1758 * What about weird destination types?
1759 * SMI: Ignore? Ought to be set up by the BIOS.
1760 * NMI: Ignore? Watchdog functionality is Xen's concern.
1761 * INIT: Definitely ignore: probably a guest OS bug.
1762 * ExtINT: Ignore? Linux only asserts this at start of day.
1763 * For now, print a message and return an error. We can fix up on demand.
1764 */
1765 if ( rte.delivery_mode > dest_LowestPrio )
1767 printk("ERROR: Attempt to write weird IOAPIC destination mode!\n");
1768 printk(" APIC=%d/%d, lo-reg=%x\n", apicid, pin, val);
1769 return -EINVAL;
1772 /*
1773 * The guest does not know physical APIC arrangement (flat vs. cluster).
1774 * Apply genapic conventions for this platform.
1775 */
1776 rte.delivery_mode = INT_DELIVERY_MODE;
1777 rte.dest_mode = INT_DEST_MODE;
1779 if ( rte.vector >= FIRST_DEVICE_VECTOR )
1781 /* Is there a valid irq mapped to this vector? */
1782 irq = vector_irq[rte.vector];
1783 if ( !IO_APIC_IRQ(irq) )
1784 return 0;
1786 /* Set the correct irq-handling type. */
1787 irq_desc[IO_APIC_VECTOR(irq)].handler = rte.trigger ?
1788 &ioapic_level_type: &ioapic_edge_type;
1790 /* Record the pin<->irq mapping. */
1791 for ( entry = &irq_2_pin[irq]; ; entry = &irq_2_pin[entry->next] )
1793 if ( (entry->apic == apicenum) && (entry->pin == pin) )
1794 break;
1795 if ( !entry->next )
1797 add_pin_to_irq(irq, apicenum, pin);
1798 break;
1803 spin_lock_irqsave(&ioapic_lock, flags);
1804 io_apic_write(apicenum, 0x10 + 2 * pin, *(((int *)&rte) + 0));
1805 io_apic_write(apicenum, 0x11 + 2 * pin, *(((int *)&rte) + 1));
1806 spin_unlock_irqrestore(&ioapic_lock, flags);
1808 return 0;