ia64/xen-unstable

view xen/arch/x86/apic.c @ 6552:a9873d384da4

Merge.
author adsharma@los-vmm.sc.intel.com
date Thu Aug 25 12:24:48 2005 -0700 (2005-08-25)
parents 112d44270733 fa0754a9f64f
children dfaf788ab18c
line source
1 /*
2 * based on linux-2.6.11/arch/i386/kernel/apic.c
3 *
4 * Local APIC handling, local APIC timers
5 *
6 * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 *
8 * Fixes
9 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
10 * thanks to Eric Gilmore
11 * and Rolf G. Tews
12 * for testing these extensively.
13 * Maciej W. Rozycki : Various updates and fixes.
14 * Mikael Pettersson : Power Management for UP-APIC.
15 * Pavel Machek and
16 * Mikael Pettersson : PM converted to driver model.
17 */
19 #include <xen/config.h>
20 #include <xen/perfc.h>
21 #include <xen/errno.h>
22 #include <xen/init.h>
23 #include <xen/mm.h>
24 #include <xen/sched.h>
25 #include <xen/irq.h>
26 #include <xen/delay.h>
27 #include <xen/smp.h>
28 #include <xen/softirq.h>
29 #include <asm/mc146818rtc.h>
30 #include <asm/msr.h>
31 #include <asm/atomic.h>
32 #include <asm/mpspec.h>
33 #include <asm/flushtlb.h>
34 #include <asm/hardirq.h>
35 #include <asm/apic.h>
36 #include <asm/io_apic.h>
37 #include <mach_apic.h>
38 #include <io_ports.h>
40 /*
41 * Debug level
42 */
43 int apic_verbosity;
45 /* Using APIC to generate smp_local_timer_interrupt? */
46 int using_apic_timer = 0;
48 static int enabled_via_apicbase;
50 int get_physical_broadcast(void)
51 {
52 unsigned int lvr, version;
53 lvr = apic_read(APIC_LVR);
54 version = GET_APIC_VERSION(lvr);
55 if (!APIC_INTEGRATED(version) || version >= 0x14)
56 return 0xff;
57 else
58 return 0xf;
59 }
61 int get_maxlvt(void)
62 {
63 unsigned int v, ver, maxlvt;
65 v = apic_read(APIC_LVR);
66 ver = GET_APIC_VERSION(v);
67 /* 82489DXs do not report # of LVT entries. */
68 maxlvt = APIC_INTEGRATED(ver) ? GET_APIC_MAXLVT(v) : 2;
69 return maxlvt;
70 }
72 void clear_local_APIC(void)
73 {
74 int maxlvt;
75 unsigned long v;
77 maxlvt = get_maxlvt();
79 /*
80 * Masking an LVT entry on a P6 can trigger a local APIC error
81 * if the vector is zero. Mask LVTERR first to prevent this.
82 */
83 if (maxlvt >= 3) {
84 v = ERROR_APIC_VECTOR; /* any non-zero vector will do */
85 apic_write_around(APIC_LVTERR, v | APIC_LVT_MASKED);
86 }
87 /*
88 * Careful: we have to set masks only first to deassert
89 * any level-triggered sources.
90 */
91 v = apic_read(APIC_LVTT);
92 apic_write_around(APIC_LVTT, v | APIC_LVT_MASKED);
93 v = apic_read(APIC_LVT0);
94 apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED);
95 v = apic_read(APIC_LVT1);
96 apic_write_around(APIC_LVT1, v | APIC_LVT_MASKED);
97 if (maxlvt >= 4) {
98 v = apic_read(APIC_LVTPC);
99 apic_write_around(APIC_LVTPC, v | APIC_LVT_MASKED);
100 }
102 /* lets not touch this if we didn't frob it */
103 #ifdef CONFIG_X86_MCE_P4THERMAL
104 if (maxlvt >= 5) {
105 v = apic_read(APIC_LVTTHMR);
106 apic_write_around(APIC_LVTTHMR, v | APIC_LVT_MASKED);
107 }
108 #endif
109 /*
110 * Clean APIC state for other OSs:
111 */
112 apic_write_around(APIC_LVTT, APIC_LVT_MASKED);
113 apic_write_around(APIC_LVT0, APIC_LVT_MASKED);
114 apic_write_around(APIC_LVT1, APIC_LVT_MASKED);
115 if (maxlvt >= 3)
116 apic_write_around(APIC_LVTERR, APIC_LVT_MASKED);
117 if (maxlvt >= 4)
118 apic_write_around(APIC_LVTPC, APIC_LVT_MASKED);
120 #ifdef CONFIG_X86_MCE_P4THERMAL
121 if (maxlvt >= 5)
122 apic_write_around(APIC_LVTTHMR, APIC_LVT_MASKED);
123 #endif
124 v = GET_APIC_VERSION(apic_read(APIC_LVR));
125 if (APIC_INTEGRATED(v)) { /* !82489DX */
126 if (maxlvt > 3) /* Due to Pentium errata 3AP and 11AP. */
127 apic_write(APIC_ESR, 0);
128 apic_read(APIC_ESR);
129 }
130 }
132 void __init connect_bsp_APIC(void)
133 {
134 if (pic_mode) {
135 /*
136 * Do not trust the local APIC being empty at bootup.
137 */
138 clear_local_APIC();
139 /*
140 * PIC mode, enable APIC mode in the IMCR, i.e.
141 * connect BSP's local APIC to INT and NMI lines.
142 */
143 apic_printk(APIC_VERBOSE, "leaving PIC mode, "
144 "enabling APIC mode.\n");
145 outb(0x70, 0x22);
146 outb(0x01, 0x23);
147 }
148 enable_apic_mode();
149 }
151 void disconnect_bsp_APIC(void)
152 {
153 if (pic_mode) {
154 /*
155 * Put the board back into PIC mode (has an effect
156 * only on certain older boards). Note that APIC
157 * interrupts, including IPIs, won't work beyond
158 * this point! The only exception are INIT IPIs.
159 */
160 apic_printk(APIC_VERBOSE, "disabling APIC mode, "
161 "entering PIC mode.\n");
162 outb(0x70, 0x22);
163 outb(0x00, 0x23);
164 }
165 }
167 void disable_local_APIC(void)
168 {
169 unsigned long value;
171 clear_local_APIC();
173 /*
174 * Disable APIC (implies clearing of registers
175 * for 82489DX!).
176 */
177 value = apic_read(APIC_SPIV);
178 value &= ~APIC_SPIV_APIC_ENABLED;
179 apic_write_around(APIC_SPIV, value);
181 if (enabled_via_apicbase) {
182 unsigned int l, h;
183 rdmsr(MSR_IA32_APICBASE, l, h);
184 l &= ~MSR_IA32_APICBASE_ENABLE;
185 wrmsr(MSR_IA32_APICBASE, l, h);
186 }
187 }
189 /*
190 * This is to verify that we're looking at a real local APIC.
191 * Check these against your board if the CPUs aren't getting
192 * started for no apparent reason.
193 */
194 int __init verify_local_APIC(void)
195 {
196 unsigned int reg0, reg1;
198 /*
199 * The version register is read-only in a real APIC.
200 */
201 reg0 = apic_read(APIC_LVR);
202 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0);
203 apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK);
204 reg1 = apic_read(APIC_LVR);
205 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1);
207 /*
208 * The two version reads above should print the same
209 * numbers. If the second one is different, then we
210 * poke at a non-APIC.
211 */
212 if (reg1 != reg0)
213 return 0;
215 /*
216 * Check if the version looks reasonably.
217 */
218 reg1 = GET_APIC_VERSION(reg0);
219 if (reg1 == 0x00 || reg1 == 0xff)
220 return 0;
221 reg1 = get_maxlvt();
222 if (reg1 < 0x02 || reg1 == 0xff)
223 return 0;
225 /*
226 * The ID register is read/write in a real APIC.
227 */
228 reg0 = apic_read(APIC_ID);
229 apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0);
231 /*
232 * The next two are just to see if we have sane values.
233 * They're only really relevant if we're in Virtual Wire
234 * compatibility mode, but most boxes are anymore.
235 */
236 reg0 = apic_read(APIC_LVT0);
237 apic_printk(APIC_DEBUG, "Getting LVT0: %x\n", reg0);
238 reg1 = apic_read(APIC_LVT1);
239 apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1);
241 return 1;
242 }
244 void __init sync_Arb_IDs(void)
245 {
246 /* Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 */
247 unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR));
248 if (ver >= 0x14) /* P4 or higher */
249 return;
250 /*
251 * Wait for idle.
252 */
253 apic_wait_icr_idle();
255 apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n");
256 apic_write_around(APIC_ICR, APIC_DEST_ALLINC | APIC_INT_LEVELTRIG
257 | APIC_DM_INIT);
258 }
260 extern void __error_in_apic_c (void);
262 /*
263 * An initial setup of the virtual wire mode.
264 */
265 void __init init_bsp_APIC(void)
266 {
267 unsigned long value, ver;
269 /*
270 * Don't do the setup now if we have a SMP BIOS as the
271 * through-I/O-APIC virtual wire mode might be active.
272 */
273 if (smp_found_config || !cpu_has_apic)
274 return;
276 value = apic_read(APIC_LVR);
277 ver = GET_APIC_VERSION(value);
279 /*
280 * Do not trust the local APIC being empty at bootup.
281 */
282 clear_local_APIC();
284 /*
285 * Enable APIC.
286 */
287 value = apic_read(APIC_SPIV);
288 value &= ~APIC_VECTOR_MASK;
289 value |= APIC_SPIV_APIC_ENABLED;
291 /* This bit is reserved on P4/Xeon and should be cleared */
292 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && (boot_cpu_data.x86 == 15))
293 value &= ~APIC_SPIV_FOCUS_DISABLED;
294 else
295 value |= APIC_SPIV_FOCUS_DISABLED;
296 value |= SPURIOUS_APIC_VECTOR;
297 apic_write_around(APIC_SPIV, value);
299 /*
300 * Set up the virtual wire mode.
301 */
302 apic_write_around(APIC_LVT0, APIC_DM_EXTINT);
303 value = APIC_DM_NMI;
304 if (!APIC_INTEGRATED(ver)) /* 82489DX */
305 value |= APIC_LVT_LEVEL_TRIGGER;
306 apic_write_around(APIC_LVT1, value);
307 }
309 void __init setup_local_APIC (void)
310 {
311 unsigned long oldvalue, value, ver, maxlvt;
313 /* Pound the ESR really hard over the head with a big hammer - mbligh */
314 if (esr_disable) {
315 apic_write(APIC_ESR, 0);
316 apic_write(APIC_ESR, 0);
317 apic_write(APIC_ESR, 0);
318 apic_write(APIC_ESR, 0);
319 }
321 value = apic_read(APIC_LVR);
322 ver = GET_APIC_VERSION(value);
324 if ((SPURIOUS_APIC_VECTOR & 0x0f) != 0x0f)
325 __error_in_apic_c();
327 /*
328 * Double-check whether this APIC is really registered.
329 */
330 if (!apic_id_registered())
331 BUG();
333 /*
334 * Intel recommends to set DFR, LDR and TPR before enabling
335 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
336 * document number 292116). So here it goes...
337 */
338 init_apic_ldr();
340 /*
341 * Set Task Priority to 'accept all'. We never change this
342 * later on.
343 */
344 value = apic_read(APIC_TASKPRI);
345 value &= ~APIC_TPRI_MASK;
346 apic_write_around(APIC_TASKPRI, value);
348 /*
349 * Now that we are all set up, enable the APIC
350 */
351 value = apic_read(APIC_SPIV);
352 value &= ~APIC_VECTOR_MASK;
353 /*
354 * Enable APIC
355 */
356 value |= APIC_SPIV_APIC_ENABLED;
358 /*
359 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
360 * certain networking cards. If high frequency interrupts are
361 * happening on a particular IOAPIC pin, plus the IOAPIC routing
362 * entry is masked/unmasked at a high rate as well then sooner or
363 * later IOAPIC line gets 'stuck', no more interrupts are received
364 * from the device. If focus CPU is disabled then the hang goes
365 * away, oh well :-(
366 *
367 * [ This bug can be reproduced easily with a level-triggered
368 * PCI Ne2000 networking cards and PII/PIII processors, dual
369 * BX chipset. ]
370 */
371 /*
372 * Actually disabling the focus CPU check just makes the hang less
373 * frequent as it makes the interrupt distributon model be more
374 * like LRU than MRU (the short-term load is more even across CPUs).
375 * See also the comment in end_level_ioapic_irq(). --macro
376 */
377 #if 1
378 /* Enable focus processor (bit==0) */
379 value &= ~APIC_SPIV_FOCUS_DISABLED;
380 #else
381 /* Disable focus processor (bit==1) */
382 value |= APIC_SPIV_FOCUS_DISABLED;
383 #endif
384 /*
385 * Set spurious IRQ vector
386 */
387 value |= SPURIOUS_APIC_VECTOR;
388 apic_write_around(APIC_SPIV, value);
390 /*
391 * Set up LVT0, LVT1:
392 *
393 * set up through-local-APIC on the BP's LINT0. This is not
394 * strictly necessery in pure symmetric-IO mode, but sometimes
395 * we delegate interrupts to the 8259A.
396 */
397 /*
398 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
399 */
400 value = apic_read(APIC_LVT0) & APIC_LVT_MASKED;
401 if (!smp_processor_id() && (pic_mode || !value)) {
402 value = APIC_DM_EXTINT;
403 apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n",
404 smp_processor_id());
405 } else {
406 value = APIC_DM_EXTINT | APIC_LVT_MASKED;
407 apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n",
408 smp_processor_id());
409 }
410 apic_write_around(APIC_LVT0, value);
412 /*
413 * only the BP should see the LINT1 NMI signal, obviously.
414 */
415 if (!smp_processor_id())
416 value = APIC_DM_NMI;
417 else
418 value = APIC_DM_NMI | APIC_LVT_MASKED;
419 if (!APIC_INTEGRATED(ver)) /* 82489DX */
420 value |= APIC_LVT_LEVEL_TRIGGER;
421 apic_write_around(APIC_LVT1, value);
423 if (APIC_INTEGRATED(ver) && !esr_disable) { /* !82489DX */
424 maxlvt = get_maxlvt();
425 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
426 apic_write(APIC_ESR, 0);
427 oldvalue = apic_read(APIC_ESR);
429 value = ERROR_APIC_VECTOR; // enables sending errors
430 apic_write_around(APIC_LVTERR, value);
431 /*
432 * spec says clear errors after enabling vector.
433 */
434 if (maxlvt > 3)
435 apic_write(APIC_ESR, 0);
436 value = apic_read(APIC_ESR);
437 if (value != oldvalue)
438 apic_printk(APIC_VERBOSE, "ESR value before enabling "
439 "vector: 0x%08lx after: 0x%08lx\n",
440 oldvalue, value);
441 } else {
442 if (esr_disable)
443 /*
444 * Something untraceble is creating bad interrupts on
445 * secondary quads ... for the moment, just leave the
446 * ESR disabled - we can't do anything useful with the
447 * errors anyway - mbligh
448 */
449 printk("Leaving ESR disabled.\n");
450 else
451 printk("No ESR for 82489DX.\n");
452 }
454 if (nmi_watchdog == NMI_LOCAL_APIC)
455 setup_apic_nmi_watchdog();
456 }
458 /*
459 * Detect and enable local APICs on non-SMP boards.
460 * Original code written by Keir Fraser.
461 */
463 /*
464 * Knob to control our willingness to enable the local APIC.
465 */
466 int enable_local_apic __initdata = 0; /* -1=force-disable, +1=force-enable */
468 static void __init lapic_disable(char *str)
469 {
470 enable_local_apic = -1;
471 clear_bit(X86_FEATURE_APIC, boot_cpu_data.x86_capability);
472 }
473 custom_param("nolapic", lapic_disable);
475 static void __init lapic_enable(char *str)
476 {
477 enable_local_apic = 1;
478 }
479 custom_param("lapic", lapic_enable);
481 static void __init apic_set_verbosity(char *str)
482 {
483 if (strcmp("debug", str) == 0)
484 apic_verbosity = APIC_DEBUG;
485 else if (strcmp("verbose", str) == 0)
486 apic_verbosity = APIC_VERBOSE;
487 else
488 printk(KERN_WARNING "APIC Verbosity level %s not recognised"
489 " use apic_verbosity=verbose or apic_verbosity=debug", str);
490 }
491 custom_param("apic_verbosity", apic_set_verbosity);
493 static int __init detect_init_APIC (void)
494 {
495 u32 h, l, features;
497 /* Disabled by kernel option? */
498 if (enable_local_apic < 0)
499 return -1;
501 /* Workaround for us being called before identify_cpu(). */
502 /*get_cpu_vendor(&boot_cpu_data); Not for Xen */
504 switch (boot_cpu_data.x86_vendor) {
505 case X86_VENDOR_AMD:
506 if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) ||
507 (boot_cpu_data.x86 == 15))
508 break;
509 goto no_apic;
510 case X86_VENDOR_INTEL:
511 if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 ||
512 (boot_cpu_data.x86 == 5 && cpu_has_apic))
513 break;
514 goto no_apic;
515 default:
516 goto no_apic;
517 }
519 if (!cpu_has_apic) {
520 /*
521 * Over-ride BIOS and try to enable the local
522 * APIC only if "lapic" specified.
523 */
524 if (enable_local_apic <= 0) {
525 printk("Local APIC disabled by BIOS -- "
526 "you can enable it with \"lapic\"\n");
527 return -1;
528 }
529 /*
530 * Some BIOSes disable the local APIC in the
531 * APIC_BASE MSR. This can only be done in
532 * software for Intel P6 or later and AMD K7
533 * (Model > 1) or later.
534 */
535 rdmsr(MSR_IA32_APICBASE, l, h);
536 if (!(l & MSR_IA32_APICBASE_ENABLE)) {
537 printk("Local APIC disabled by BIOS -- reenabling.\n");
538 l &= ~MSR_IA32_APICBASE_BASE;
539 l |= MSR_IA32_APICBASE_ENABLE | APIC_DEFAULT_PHYS_BASE;
540 wrmsr(MSR_IA32_APICBASE, l, h);
541 enabled_via_apicbase = 1;
542 }
543 }
544 /*
545 * The APIC feature bit should now be enabled
546 * in `cpuid'
547 */
548 features = cpuid_edx(1);
549 if (!(features & (1 << X86_FEATURE_APIC))) {
550 printk("Could not enable APIC!\n");
551 return -1;
552 }
554 set_bit(X86_FEATURE_APIC, boot_cpu_data.x86_capability);
555 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
557 /* The BIOS may have set up the APIC at some other address */
558 rdmsr(MSR_IA32_APICBASE, l, h);
559 if (l & MSR_IA32_APICBASE_ENABLE)
560 mp_lapic_addr = l & MSR_IA32_APICBASE_BASE;
562 if (nmi_watchdog != NMI_NONE)
563 nmi_watchdog = NMI_LOCAL_APIC;
565 printk("Found and enabled local APIC!\n");
567 return 0;
569 no_apic:
570 printk("No local APIC present or hardware disabled\n");
571 return -1;
572 }
574 void __init init_apic_mappings(void)
575 {
576 unsigned long apic_phys;
578 /*
579 * If no local APIC can be found then set up a fake all
580 * zeroes page to simulate the local APIC and another
581 * one for the IO-APIC.
582 */
583 if (!smp_found_config && detect_init_APIC())
584 apic_phys = __pa(alloc_xenheap_page());
585 else
586 apic_phys = mp_lapic_addr;
588 set_fixmap_nocache(FIX_APIC_BASE, apic_phys);
589 apic_printk(APIC_VERBOSE, "mapped APIC to %08lx (%08lx)\n", APIC_BASE,
590 apic_phys);
592 /*
593 * Fetch the APIC ID of the BSP in case we have a
594 * default configuration (or the MP table is broken).
595 */
596 if (boot_cpu_physical_apicid == -1U)
597 boot_cpu_physical_apicid = GET_APIC_ID(apic_read(APIC_ID));
599 #ifdef CONFIG_X86_IO_APIC
600 {
601 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
602 int i;
604 for (i = 0; i < nr_ioapics; i++) {
605 if (smp_found_config) {
606 ioapic_phys = mp_ioapics[i].mpc_apicaddr;
607 if (!ioapic_phys) {
608 printk(KERN_ERR
609 "WARNING: bogus zero IO-APIC "
610 "address found in MPTABLE, "
611 "disabling IO/APIC support!\n");
612 smp_found_config = 0;
613 skip_ioapic_setup = 1;
614 goto fake_ioapic_page;
615 }
616 } else {
617 fake_ioapic_page:
618 ioapic_phys = __pa(alloc_xenheap_page());
619 }
620 set_fixmap_nocache(idx, ioapic_phys);
621 apic_printk(APIC_VERBOSE, "mapped IOAPIC to %08lx (%08lx)\n",
622 __fix_to_virt(idx), ioapic_phys);
623 idx++;
624 }
625 }
626 #endif
627 }
629 /*****************************************************************************
630 * APIC calibration
631 *
632 * The APIC is programmed in bus cycles.
633 * Timeout values should specified in real time units.
634 * The "cheapest" time source is the cyclecounter.
635 *
636 * Thus, we need a mappings from: bus cycles <- cycle counter <- system time
637 *
638 * The calibration is currently a bit shoddy since it requires the external
639 * timer chip to generate periodic timer interupts.
640 *****************************************************************************/
642 /* used for system time scaling */
643 static unsigned long bus_freq; /* KAF: pointer-size avoids compile warns. */
644 static u32 bus_cycle; /* length of one bus cycle in pico-seconds */
645 static u32 bus_scale; /* scaling factor convert ns to bus cycles */
647 /*
648 * The timer chip is already set up at HZ interrupts per second here,
649 * but we do not accept timer interrupts yet. We only allow the BP
650 * to calibrate.
651 */
652 static unsigned int __init get_8254_timer_count(void)
653 {
654 /*extern spinlock_t i8253_lock;*/
655 /*unsigned long flags;*/
657 unsigned int count;
659 /*spin_lock_irqsave(&i8253_lock, flags);*/
661 outb_p(0x00, PIT_MODE);
662 count = inb_p(PIT_CH0);
663 count |= inb_p(PIT_CH0) << 8;
665 /*spin_unlock_irqrestore(&i8253_lock, flags);*/
667 return count;
668 }
670 /* next tick in 8254 can be caught by catching timer wraparound */
671 static void __init wait_8254_wraparound(void)
672 {
673 unsigned int curr_count, prev_count;
675 curr_count = get_8254_timer_count();
676 do {
677 prev_count = curr_count;
678 curr_count = get_8254_timer_count();
680 /* workaround for broken Mercury/Neptune */
681 if (prev_count >= curr_count + 0x100)
682 curr_count = get_8254_timer_count();
684 } while (prev_count >= curr_count);
685 }
687 /*
688 * Default initialization for 8254 timers. If we use other timers like HPET,
689 * we override this later
690 */
691 void (*wait_timer_tick)(void) __initdata = wait_8254_wraparound;
693 /*
694 * This function sets up the local APIC timer, with a timeout of
695 * 'clocks' APIC bus clock. During calibration we actually call
696 * this function twice on the boot CPU, once with a bogus timeout
697 * value, second time for real. The other (noncalibrating) CPUs
698 * call this function only once, with the real, calibrated value.
699 *
700 * We do reads before writes even if unnecessary, to get around the
701 * P5 APIC double write bug.
702 */
704 #define APIC_DIVISOR 1
706 void __setup_APIC_LVTT(unsigned int clocks)
707 {
708 unsigned int lvtt_value, tmp_value, ver;
710 ver = GET_APIC_VERSION(apic_read(APIC_LVR));
711 /* NB. Xen uses local APIC timer in one-shot mode. */
712 lvtt_value = /*APIC_LVT_TIMER_PERIODIC |*/ LOCAL_TIMER_VECTOR;
713 if (!APIC_INTEGRATED(ver))
714 lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV);
715 apic_write_around(APIC_LVTT, lvtt_value);
717 tmp_value = apic_read(APIC_TDCR);
718 apic_write_around(APIC_TDCR, (tmp_value | APIC_TDR_DIV_1));
720 apic_write_around(APIC_TMICT, clocks/APIC_DIVISOR);
721 }
723 static void __init setup_APIC_timer(unsigned int clocks)
724 {
725 unsigned long flags;
726 local_irq_save(flags);
727 __setup_APIC_LVTT(clocks);
728 local_irq_restore(flags);
729 }
731 /*
732 * In this function we calibrate APIC bus clocks to the external
733 * timer. Unfortunately we cannot use jiffies and the timer irq
734 * to calibrate, since some later bootup code depends on getting
735 * the first irq? Ugh.
736 *
737 * We want to do the calibration only once since we
738 * want to have local timer irqs syncron. CPUs connected
739 * by the same APIC bus have the very same bus frequency.
740 * And we want to have irqs off anyways, no accidental
741 * APIC irq that way.
742 */
744 int __init calibrate_APIC_clock(void)
745 {
746 unsigned long long t1 = 0, t2 = 0;
747 long tt1, tt2;
748 long result;
749 int i;
750 const int LOOPS = HZ/10;
752 apic_printk(APIC_VERBOSE, "calibrating APIC timer ...\n");
754 /*
755 * Put whatever arbitrary (but long enough) timeout
756 * value into the APIC clock, we just want to get the
757 * counter running for calibration.
758 */
759 __setup_APIC_LVTT(1000000000);
761 /*
762 * The timer chip counts down to zero. Let's wait
763 * for a wraparound to start exact measurement:
764 * (the current tick might have been already half done)
765 */
766 wait_timer_tick();
768 /*
769 * We wrapped around just now. Let's start:
770 */
771 if (cpu_has_tsc)
772 rdtscll(t1);
773 tt1 = apic_read(APIC_TMCCT);
775 /*
776 * Let's wait LOOPS wraprounds:
777 */
778 for (i = 0; i < LOOPS; i++)
779 wait_timer_tick();
781 tt2 = apic_read(APIC_TMCCT);
782 if (cpu_has_tsc)
783 rdtscll(t2);
785 /*
786 * The APIC bus clock counter is 32 bits only, it
787 * might have overflown, but note that we use signed
788 * longs, thus no extra care needed.
789 *
790 * underflown to be exact, as the timer counts down ;)
791 */
793 result = (tt1-tt2)*APIC_DIVISOR/LOOPS;
795 if (cpu_has_tsc)
796 apic_printk(APIC_VERBOSE, "..... CPU clock speed is "
797 "%ld.%04ld MHz.\n",
798 ((long)(t2-t1)/LOOPS)/(1000000/HZ),
799 ((long)(t2-t1)/LOOPS)%(1000000/HZ));
801 apic_printk(APIC_VERBOSE, "..... host bus clock speed is "
802 "%ld.%04ld MHz.\n",
803 result/(1000000/HZ),
804 result%(1000000/HZ));
806 /* set up multipliers for accurate timer code */
807 bus_freq = result*HZ;
808 bus_cycle = (u32) (1000000000000LL/bus_freq); /* in pico seconds */
809 bus_scale = (1000*262144)/bus_cycle;
811 apic_printk(APIC_VERBOSE, "..... bus_scale = 0x%08X\n", bus_scale);
812 /* reset APIC to zero timeout value */
813 __setup_APIC_LVTT(0);
815 return result;
816 }
819 static unsigned int calibration_result;
821 void __init setup_boot_APIC_clock(void)
822 {
823 apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n");
824 using_apic_timer = 1;
826 local_irq_disable();
828 calibration_result = calibrate_APIC_clock();
829 /*
830 * Now set up the timer for real.
831 */
832 setup_APIC_timer(calibration_result);
834 local_irq_enable();
835 }
837 void __init setup_secondary_APIC_clock(void)
838 {
839 setup_APIC_timer(calibration_result);
840 }
842 void __init disable_APIC_timer(void)
843 {
844 if (using_apic_timer) {
845 unsigned long v;
847 v = apic_read(APIC_LVTT);
848 apic_write_around(APIC_LVTT, v | APIC_LVT_MASKED);
849 }
850 }
852 void enable_APIC_timer(void)
853 {
854 if (using_apic_timer) {
855 unsigned long v;
857 v = apic_read(APIC_LVTT);
858 apic_write_around(APIC_LVTT, v & ~APIC_LVT_MASKED);
859 }
860 }
862 #undef APIC_DIVISOR
864 /*
865 * reprogram the APIC timer. Timeoutvalue is in ns from start of boot
866 * returns 1 on success
867 * returns 0 if the timeout value is too small or in the past.
868 */
869 int reprogram_ac_timer(s_time_t timeout)
870 {
871 s_time_t now;
872 s_time_t expire;
873 u64 apic_tmict;
875 /*
876 * We use this value because we don't trust zero (we think it may just
877 * cause an immediate interrupt). At least this is guaranteed to hold it
878 * off for ages (esp. since the clock ticks on bus clock, not cpu clock!).
879 */
880 if ( timeout == 0 )
881 {
882 apic_tmict = 0xffffffff;
883 goto reprogram;
884 }
886 now = NOW();
887 expire = timeout - now; /* value from now */
889 if ( expire <= 0 )
890 {
891 Dprintk("APICT[%02d] Timeout in the past 0x%08X%08X > 0x%08X%08X\n",
892 smp_processor_id(), (u32)(now>>32),
893 (u32)now, (u32)(timeout>>32),(u32)timeout);
894 return 0;
895 }
897 /*
898 * If we don't have local APIC then we just poll the timer list off the
899 * PIT interrupt. Cheesy but good enough to work on eg. VMware :-)
900 */
901 if ( !cpu_has_apic )
902 return 1;
904 /* conversion to bus units */
905 apic_tmict = (((u64)bus_scale) * expire)>>18;
907 if ( apic_tmict >= 0xffffffff )
908 {
909 Dprintk("APICT[%02d] Timeout value too large\n", smp_processor_id());
910 apic_tmict = 0xffffffff;
911 }
913 if ( apic_tmict == 0 )
914 {
915 Dprintk("APICT[%02d] timeout value too small\n", smp_processor_id());
916 return 0;
917 }
919 reprogram:
920 /* Program the timer. */
921 apic_write(APIC_TMICT, (unsigned long)apic_tmict);
923 return 1;
924 }
926 void smp_apic_timer_interrupt(struct cpu_user_regs * regs)
927 {
928 ack_APIC_irq();
929 perfc_incrc(apic_timer);
930 raise_softirq(AC_TIMER_SOFTIRQ);
931 }
933 /*
934 * This interrupt should _never_ happen with our APIC/SMP architecture
935 */
936 asmlinkage void smp_spurious_interrupt(struct cpu_user_regs *regs)
937 {
938 unsigned long v;
940 /*
941 * Check if this really is a spurious interrupt and ACK it
942 * if it is a vectored one. Just in case...
943 * Spurious interrupts should not be ACKed.
944 */
945 v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1));
946 if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f)))
947 ack_APIC_irq();
949 /* see sw-dev-man vol 3, chapter 7.4.13.5 */
950 printk(KERN_INFO "spurious APIC interrupt on CPU#%d, should never happen.\n",
951 smp_processor_id());
952 }
954 /*
955 * This interrupt should never happen with our APIC/SMP architecture
956 */
958 asmlinkage void smp_error_interrupt(struct cpu_user_regs *regs)
959 {
960 unsigned long v, v1;
962 /* First tickle the hardware, only then report what went on. -- REW */
963 v = apic_read(APIC_ESR);
964 apic_write(APIC_ESR, 0);
965 v1 = apic_read(APIC_ESR);
966 ack_APIC_irq();
967 atomic_inc(&irq_err_count);
969 /* Here is what the APIC error bits mean:
970 0: Send CS error
971 1: Receive CS error
972 2: Send accept error
973 3: Receive accept error
974 4: Reserved
975 5: Send illegal vector
976 6: Received illegal vector
977 7: Illegal register address
978 */
979 printk (KERN_DEBUG "APIC error on CPU%d: %02lx(%02lx)\n",
980 smp_processor_id(), v , v1);
981 }
983 /*
984 * This initializes the IO-APIC and APIC hardware if this is
985 * a UP kernel.
986 */
987 int __init APIC_init_uniprocessor (void)
988 {
989 if (enable_local_apic < 0)
990 clear_bit(X86_FEATURE_APIC, boot_cpu_data.x86_capability);
992 if (!smp_found_config && !cpu_has_apic)
993 return -1;
995 /*
996 * Complain if the BIOS pretends there is one.
997 */
998 if (!cpu_has_apic && APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) {
999 printk(KERN_ERR "BIOS bug, local APIC #%d not detected!...\n",
1000 boot_cpu_physical_apicid);
1001 return -1;
1004 verify_local_APIC();
1006 connect_bsp_APIC();
1008 phys_cpu_present_map = physid_mask_of_physid(boot_cpu_physical_apicid);
1010 setup_local_APIC();
1012 if (nmi_watchdog == NMI_LOCAL_APIC)
1013 check_nmi_watchdog();
1014 #ifdef CONFIG_X86_IO_APIC
1015 if (smp_found_config)
1016 if (!skip_ioapic_setup && nr_ioapics)
1017 setup_IO_APIC();
1018 #endif
1019 setup_boot_APIC_clock();
1021 return 0;