ia64/xen-unstable

view xen/arch/ia64/patch/linux-2.6.11/kregs.h @ 6552:a9873d384da4

Merge.
author adsharma@los-vmm.sc.intel.com
date Thu Aug 25 12:24:48 2005 -0700 (2005-08-25)
parents 112d44270733 fa0754a9f64f
children
line source
1 --- /home/adsharma/disk2/xen-ia64/xeno-unstable-rebase.bk/xen/../../linux-2.6.11/include/asm-ia64/kregs.h 2005-03-01 23:37:49.000000000 -0800
2 +++ /home/adsharma/disk2/xen-ia64/xeno-unstable-rebase.bk/xen/include/asm-ia64/kregs.h 2005-05-18 12:40:50.000000000 -0700
3 @@ -29,8 +29,21 @@
4 */
5 #define IA64_TR_KERNEL 0 /* itr0, dtr0: maps kernel image (code & data) */
6 #define IA64_TR_PALCODE 1 /* itr1: maps PALcode as required by EFI */
7 +#ifdef CONFIG_VTI
8 +#define IA64_TR_XEN_IN_DOM 6 /* itr6, dtr6: Double mapping for xen image in domain space */
9 +#endif // CONFIG_VTI
10 #define IA64_TR_PERCPU_DATA 1 /* dtr1: percpu data */
11 #define IA64_TR_CURRENT_STACK 2 /* dtr2: maps kernel's memory- & register-stacks */
12 +#ifdef XEN
13 +#define IA64_TR_SHARED_INFO 3 /* dtr3: page shared with domain */
14 +#define IA64_TR_VHPT 4 /* dtr4: vhpt */
15 +#define IA64_TR_ARCH_INFO 5
16 +#ifdef CONFIG_VTI
17 +#define IA64_TR_VHPT_IN_DOM 5 /* dtr5: Double mapping for vhpt table in domain space */
18 +#define IA64_TR_RR7_SWITCH_STUB 7 /* dtr7: mapping for rr7 switch stub */
19 +#define IA64_TEMP_PHYSICAL 8 /* itr8, dtr8: temp mapping for guest physical memory 256M */
20 +#endif // CONFIG_VTI
21 +#endif
23 /* Processor status register bits: */
24 #define IA64_PSR_BE_BIT 1
25 @@ -66,6 +78,9 @@
26 #define IA64_PSR_ED_BIT 43
27 #define IA64_PSR_BN_BIT 44
28 #define IA64_PSR_IA_BIT 45
29 +#ifdef CONFIG_VTI
30 +#define IA64_PSR_VM_BIT 46
31 +#endif // CONFIG_VTI
33 /* A mask of PSR bits that we generally don't want to inherit across a clone2() or an
34 execve(). Only list flags here that need to be cleared/set for BOTH clone2() and
35 @@ -107,6 +122,9 @@
36 #define IA64_PSR_ED (__IA64_UL(1) << IA64_PSR_ED_BIT)
37 #define IA64_PSR_BN (__IA64_UL(1) << IA64_PSR_BN_BIT)
38 #define IA64_PSR_IA (__IA64_UL(1) << IA64_PSR_IA_BIT)
39 +#ifdef CONFIG_VTI
40 +#define IA64_PSR_VM (__IA64_UL(1) << IA64_PSR_VM_BIT)
41 +#endif // CONFIG_VTI
43 /* User mask bits: */
44 #define IA64_PSR_UM (IA64_PSR_BE | IA64_PSR_UP | IA64_PSR_AC | IA64_PSR_MFL | IA64_PSR_MFH)
45 @@ -160,4 +178,21 @@
46 #define IA64_ISR_CODE_LFETCH 4
47 #define IA64_ISR_CODE_PROBEF 5
49 +#ifdef XEN
50 +/* Interruption Function State */
51 +#define IA64_IFS_V_BIT 63
52 +#define IA64_IFS_V (__IA64_UL(1) << IA64_IFS_V_BIT)
53 +
54 +/* Page Table Address */
55 +#define IA64_PTA_VE_BIT 0
56 +#define IA64_PTA_SIZE_BIT 2
57 +#define IA64_PTA_VF_BIT 8
58 +#define IA64_PTA_BASE_BIT 15
59 +
60 +#define IA64_PTA_VE (__IA64_UL(1) << IA64_PTA_VE_BIT)
61 +#define IA64_PTA_SIZE (__IA64_UL(0x3f) << IA64_PTA_SIZE_BIT)
62 +#define IA64_PTA_VF (__IA64_UL(1) << IA64_PTA_VF_BIT)
63 +#define IA64_PTA_BASE (__IA64_UL(0) - ((__IA64_UL(1) << IA64_PTA_BASE_BIT)))
64 +#endif
65 +
66 #endif /* _ASM_IA64_kREGS_H */