ia64/xen-unstable

view xen/arch/ia64/asm-xsi-offsets.c @ 6552:a9873d384da4

Merge.
author adsharma@los-vmm.sc.intel.com
date Thu Aug 25 12:24:48 2005 -0700 (2005-08-25)
parents 112d44270733 fa0754a9f64f
children dfaf788ab18c
line source
1 /* -*- Mode:C; c-basic-offset:4; tab-width:4; indent-tabs-mode:nil -*- */
2 /*
3 * asm-xsi-offsets.c_
4 * Copyright (c) 2005, Intel Corporation.
5 * Kun Tian (Kevin Tian) <kevin.tian@intel.com>
6 * Eddie Dong <eddie.dong@intel.com>
7 * Fred Yang <fred.yang@intel.com>
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms and conditions of the GNU General Public License,
11 * version 2, as published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * more details.
17 *
18 * You should have received a copy of the GNU General Public License along with
19 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
20 * Place - Suite 330, Boston, MA 02111-1307 USA.
21 *
22 */
24 /*
25 * Generate definitions needed by assembly language modules.
26 * This code generates raw asm output which is post-processed
27 * to extract and format the required data.
28 */
30 #include <xen/config.h>
31 #include <xen/sched.h>
32 #include <asm/processor.h>
33 #include <asm/ptrace.h>
34 #include <public/xen.h>
35 #ifdef CONFIG_VTI
36 #include <asm/tlb.h>
37 #include <asm/regs.h>
38 #endif // CONFIG_VTI
40 #define task_struct vcpu
42 #define DEFINE(sym, val) \
43 asm volatile("\n->" #sym " %0 " #val : : "i" (val))
45 #define BLANK() asm volatile("\n->" : : )
47 #define OFFSET(_sym, _str, _mem) \
48 DEFINE(_sym, offsetof(_str, _mem));
50 void foo(void)
51 {
53 DEFINE(XSI_BASE, SHARED_ARCHINFO_ADDR);
55 DEFINE(XSI_PSR_I_OFS, offsetof(mapped_regs_t, interrupt_delivery_enabled));
56 DEFINE(XSI_PSR_I, (SHARED_ARCHINFO_ADDR+offsetof(mapped_regs_t, interrupt_delivery_enabled)));
57 DEFINE(XSI_IPSR, (SHARED_ARCHINFO_ADDR+offsetof(mapped_regs_t, ipsr)));
58 DEFINE(XSI_IPSR_OFS, offsetof(mapped_regs_t, ipsr));
59 DEFINE(XSI_IIP_OFS, offsetof(mapped_regs_t, iip));
60 DEFINE(XSI_IIP, (SHARED_ARCHINFO_ADDR+offsetof(mapped_regs_t, iip)));
61 DEFINE(XSI_IFS_OFS, offsetof(mapped_regs_t, ifs));
62 DEFINE(XSI_IFS, (SHARED_ARCHINFO_ADDR+offsetof(mapped_regs_t, ifs)));
63 DEFINE(XSI_PRECOVER_IFS_OFS, offsetof(mapped_regs_t, precover_ifs));
64 DEFINE(XSI_PRECOVER_IFS, (SHARED_ARCHINFO_ADDR+offsetof(mapped_regs_t, precover_ifs)));
65 DEFINE(XSI_ISR_OFS, offsetof(mapped_regs_t, isr));
66 DEFINE(XSI_ISR, (SHARED_ARCHINFO_ADDR+offsetof(mapped_regs_t, isr)));
67 DEFINE(XSI_IFA_OFS, offsetof(mapped_regs_t, ifa));
68 DEFINE(XSI_IFA, (SHARED_ARCHINFO_ADDR+offsetof(mapped_regs_t, ifa)));
69 DEFINE(XSI_IIPA_OFS, offsetof(mapped_regs_t, iipa));
70 DEFINE(XSI_IIPA, (SHARED_ARCHINFO_ADDR+offsetof(mapped_regs_t, iipa)));
71 DEFINE(XSI_IIM_OFS, offsetof(mapped_regs_t, iim));
72 DEFINE(XSI_IIM, (SHARED_ARCHINFO_ADDR+offsetof(mapped_regs_t, iim)));
73 DEFINE(XSI_TPR_OFS, offsetof(mapped_regs_t, tpr));
74 DEFINE(XSI_TPR, (SHARED_ARCHINFO_ADDR+offsetof(mapped_regs_t, tpr)));
75 DEFINE(XSI_IHA_OFS, offsetof(mapped_regs_t, iha));
76 DEFINE(XSI_IHA, (SHARED_ARCHINFO_ADDR+offsetof(mapped_regs_t, iha)));
77 DEFINE(XSI_ITIR_OFS, offsetof(mapped_regs_t, itir));
78 DEFINE(XSI_ITIR, (SHARED_ARCHINFO_ADDR+offsetof(mapped_regs_t, itir)));
79 DEFINE(XSI_ITV_OFS, offsetof(mapped_regs_t, itv));
80 DEFINE(XSI_ITV, (SHARED_ARCHINFO_ADDR+offsetof(mapped_regs_t, itv)));
81 DEFINE(XSI_PTA_OFS, offsetof(mapped_regs_t, pta));
82 DEFINE(XSI_PTA, (SHARED_ARCHINFO_ADDR+offsetof(mapped_regs_t, pta)));
83 DEFINE(XSI_PSR_IC_OFS, offsetof(mapped_regs_t, interrupt_collection_enabled));
84 DEFINE(XSI_PSR_IC, (SHARED_ARCHINFO_ADDR+offsetof(mapped_regs_t, interrupt_collection_enabled)));
85 DEFINE(XSI_PEND_OFS, offsetof(mapped_regs_t, pending_interruption));
86 DEFINE(XSI_PEND, (SHARED_ARCHINFO_ADDR+offsetof(mapped_regs_t, pending_interruption)));
87 DEFINE(XSI_INCOMPL_REGFR_OFS, offsetof(mapped_regs_t, incomplete_regframe));
88 DEFINE(XSI_INCOMPL_REGFR, (SHARED_ARCHINFO_ADDR+offsetof(mapped_regs_t, incomplete_regframe)));
89 DEFINE(XSI_DELIV_MASK0_OFS, offsetof(mapped_regs_t, delivery_mask[0]));
90 DEFINE(XSI_DELIV_MASK0, (SHARED_ARCHINFO_ADDR+offsetof(mapped_regs_t, delivery_mask[0])));
91 DEFINE(XSI_METAPHYS_OFS, offsetof(mapped_regs_t, metaphysical_mode));
92 DEFINE(XSI_METAPHYS, (SHARED_ARCHINFO_ADDR+offsetof(mapped_regs_t, metaphysical_mode)));
94 DEFINE(XSI_BANKNUM_OFS, offsetof(mapped_regs_t, banknum));
95 DEFINE(XSI_BANKNUM, (SHARED_ARCHINFO_ADDR+offsetof(mapped_regs_t, banknum)));
97 DEFINE(XSI_BANK0_R16_OFS, offsetof(mapped_regs_t, bank0_regs[0]));
98 DEFINE(XSI_BANK0_R16, (SHARED_ARCHINFO_ADDR+offsetof(mapped_regs_t, bank0_regs[0])));
99 DEFINE(XSI_BANK1_R16_OFS, offsetof(mapped_regs_t, bank1_regs[0]));
100 DEFINE(XSI_BANK1_R16, (SHARED_ARCHINFO_ADDR+offsetof(mapped_regs_t, bank1_regs[0])));
101 DEFINE(XSI_RR0_OFS, offsetof(mapped_regs_t, rrs[0]));
102 DEFINE(XSI_RR0, (SHARED_ARCHINFO_ADDR+offsetof(mapped_regs_t, rrs[0])));
103 DEFINE(XSI_KR0_OFS, offsetof(mapped_regs_t, krs[0]));
104 DEFINE(XSI_KR0, (SHARED_ARCHINFO_ADDR+offsetof(mapped_regs_t, krs[0])));
105 DEFINE(XSI_PKR0_OFS, offsetof(mapped_regs_t, pkrs[0]));
106 DEFINE(XSI_PKR0, (SHARED_ARCHINFO_ADDR+offsetof(mapped_regs_t, pkrs[0])));
107 DEFINE(XSI_TMP0_OFS, offsetof(mapped_regs_t, tmp[0]));
108 DEFINE(XSI_TMP0, (SHARED_ARCHINFO_ADDR+offsetof(mapped_regs_t, tmp[0])));
110 }