ia64/xen-unstable

view linux-2.6-xen-sparse/arch/xen/i386/kernel/head.S @ 6552:a9873d384da4

Merge.
author adsharma@los-vmm.sc.intel.com
date Thu Aug 25 12:24:48 2005 -0700 (2005-08-25)
parents 112d44270733 fa0754a9f64f
children dfaf788ab18c
line source
2 #include <linux/config.h>
4 .section __xen_guest
5 .ascii "GUEST_OS=linux,GUEST_VER=2.6"
6 .ascii ",XEN_VER=3.0"
7 .ascii ",VIRT_BASE=0xC0000000"
8 #ifdef CONFIG_X86_PAE
9 .ascii ",PAE=yes"
10 #else
11 .ascii ",PAE=no"
12 #endif
13 #ifdef CONFIG_XEN_SHADOW_MODE
14 .ascii ",SHADOW=translate"
15 #endif
16 .ascii ",LOADER=generic"
17 .byte 0
19 .text
20 #include <linux/threads.h>
21 #include <linux/linkage.h>
22 #include <asm/segment.h>
23 #include <asm/thread_info.h>
24 #include <asm/asm_offsets.h>
25 #include <asm-xen/xen-public/arch-x86_32.h>
27 /*
28 * References to members of the new_cpu_data structure.
29 */
31 #define X86 new_cpu_data+CPUINFO_x86
32 #define X86_VENDOR new_cpu_data+CPUINFO_x86_vendor
33 #define X86_MODEL new_cpu_data+CPUINFO_x86_model
34 #define X86_MASK new_cpu_data+CPUINFO_x86_mask
35 #define X86_HARD_MATH new_cpu_data+CPUINFO_hard_math
36 #define X86_CPUID new_cpu_data+CPUINFO_cpuid_level
37 #define X86_CAPABILITY new_cpu_data+CPUINFO_x86_capability
38 #define X86_VENDOR_ID new_cpu_data+CPUINFO_x86_vendor_id
40 ENTRY(startup_32)
41 cld
43 /* Copy the necessary stuff from xen_start_info structure. */
44 mov $xen_start_info_union,%edi
45 mov $512,%ecx
46 rep movsl
48 #ifdef CONFIG_SMP
49 ENTRY(startup_32_smp)
50 cld
51 #endif /* CONFIG_SMP */
53 /* Set up the stack pointer */
54 lss stack_start,%esp
56 checkCPUtype:
58 /* get vendor info */
59 xorl %eax,%eax # call CPUID with 0 -> return vendor ID
60 cpuid
61 movl %eax,X86_CPUID # save CPUID level
62 movl %ebx,X86_VENDOR_ID # lo 4 chars
63 movl %edx,X86_VENDOR_ID+4 # next 4 chars
64 movl %ecx,X86_VENDOR_ID+8 # last 4 chars
66 movl $1,%eax # Use the CPUID instruction to get CPU type
67 cpuid
68 movb %al,%cl # save reg for future use
69 andb $0x0f,%ah # mask processor family
70 movb %ah,X86
71 andb $0xf0,%al # mask model
72 shrb $4,%al
73 movb %al,X86_MODEL
74 andb $0x0f,%cl # mask mask revision
75 movb %cl,X86_MASK
76 movl %edx,X86_CAPABILITY
78 incb ready
80 xorl %eax,%eax # Clear FS/GS and LDT
81 movl %eax,%fs
82 movl %eax,%gs
83 cld # gcc2 wants the direction flag cleared at all times
85 #ifdef CONFIG_SMP
86 movb ready, %cl
87 cmpb $1,%cl
88 je 1f # the first CPU calls start_kernel
89 # all other CPUs call initialize_secondary
90 call initialize_secondary
91 jmp L6
92 1:
93 #endif /* CONFIG_SMP */
94 call start_kernel
95 L6:
96 jmp L6 # main should never return here, but
97 # just in case, we know what happens.
99 ENTRY(lgdt_finish)
100 movl $(__KERNEL_DS),%eax # reload all the segment registers
101 movw %ax,%ss # after changing gdt.
103 movl $(__USER_DS),%eax # DS/ES contains default USER segment
104 movw %ax,%ds
105 movw %ax,%es
107 popl %eax # reload CS by intersegment return
108 pushl $(__KERNEL_CS)
109 pushl %eax
110 lret
112 ENTRY(stack_start)
113 .long init_thread_union+THREAD_SIZE
114 .long __BOOT_DS
116 ready: .byte 0
118 .globl idt_descr
119 .globl cpu_gdt_descr
121 ALIGN
122 .word 0 # 32-bit align idt_desc.address
123 idt_descr:
124 .word IDT_ENTRIES*8-1 # idt contains 256 entries
125 .long idt_table
127 # boot GDT descriptor (later on used by CPU#0):
128 .word 0 # 32 bit align gdt_desc.address
129 cpu_gdt_descr:
130 .word GDT_SIZE
131 .long cpu_gdt_table
133 .fill NR_CPUS-1,8,0 # space for the other GDT descriptors
135 .org 0x1000
136 ENTRY(empty_zero_page)
138 .org 0x2000
139 ENTRY(cpu_gdt_table)
140 .quad 0x0000000000000000 /* NULL descriptor */
141 .quad 0x0000000000000000 /* 0x0b reserved */
142 .quad 0x0000000000000000 /* 0x13 reserved */
143 .quad 0x0000000000000000 /* 0x1b reserved */
144 .quad 0x0000000000000000 /* 0x20 unused */
145 .quad 0x0000000000000000 /* 0x28 unused */
146 .quad 0x0000000000000000 /* 0x33 TLS entry 1 */
147 .quad 0x0000000000000000 /* 0x3b TLS entry 2 */
148 .quad 0x0000000000000000 /* 0x43 TLS entry 3 */
149 .quad 0x0000000000000000 /* 0x4b reserved */
150 .quad 0x0000000000000000 /* 0x53 reserved */
151 .quad 0x0000000000000000 /* 0x5b reserved */
153 #ifdef CONFIG_X86_PAE
154 .quad 0x00cfbb00000067ff /* 0x60 kernel 4GB code at 0x00000000 */
155 .quad 0x00cfb300000067ff /* 0x68 kernel 4GB data at 0x00000000 */
156 .quad 0x00cffb00000067ff /* 0x73 user 4GB code at 0x00000000 */
157 .quad 0x00cff300000067ff /* 0x7b user 4GB data at 0x00000000 */
158 #else
159 .quad 0x00cfbb000000c3ff /* 0x60 kernel 4GB code at 0x00000000 */
160 .quad 0x00cfb3000000c3ff /* 0x68 kernel 4GB data at 0x00000000 */
161 .quad 0x00cffb000000c3ff /* 0x73 user 4GB code at 0x00000000 */
162 .quad 0x00cff3000000c3ff /* 0x7b user 4GB data at 0x00000000 */
163 #endif
165 .quad 0x0000000000000000 /* 0x80 TSS descriptor */
166 .quad 0x0000000000000000 /* 0x88 LDT descriptor */
168 /* Segments used for calling PnP BIOS */
169 .quad 0x0000000000000000 /* 0x90 32-bit code */
170 .quad 0x0000000000000000 /* 0x98 16-bit code */
171 .quad 0x0000000000000000 /* 0xa0 16-bit data */
172 .quad 0x0000000000000000 /* 0xa8 16-bit data */
173 .quad 0x0000000000000000 /* 0xb0 16-bit data */
174 /*
175 * The APM segments have byte granularity and their bases
176 * and limits are set at run time.
177 */
178 .quad 0x0000000000000000 /* 0xb8 APM CS code */
179 .quad 0x0000000000000000 /* 0xc0 APM CS 16 code (16 bit) */
180 .quad 0x0000000000000000 /* 0xc8 APM DS data */
182 .quad 0x0000000000000000 /* 0xd0 - unused */
183 .quad 0x0000000000000000 /* 0xd8 - unused */
184 .quad 0x0000000000000000 /* 0xe0 - unused */
185 .quad 0x0000000000000000 /* 0xe8 - unused */
186 .quad 0x0000000000000000 /* 0xf0 - unused */
187 .quad 0x0000000000000000 /* 0xf8 - GDT entry 31: double-fault TSS */
188 .fill GDT_ENTRIES-32,8,0
190 .org 0x3000
191 ENTRY(default_ldt)
193 .org 0x4000
194 /*
195 * Real beginning of normal "text" segment
196 */
197 ENTRY(stext)
198 ENTRY(_stext)