ia64/xen-unstable

view xen/include/public/arch-x86/hvm/save.h @ 16153:a87d94be1172

Split xen/include/public/hvm/save.h into common part and x86 specific part.
Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
author Keir Fraser <keir@xensource.com>
date Thu Oct 18 10:58:36 2007 +0100 (2007-10-18)
parents
children 5a451d2c36bc
line source
1 /*
2 * Structure definitions for HVM state that is held by Xen and must
3 * be saved along with the domain's memory and device-model state.
4 *
5 * Copyright (c) 2007 XenSource Ltd.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to
9 * deal in the Software without restriction, including without limitation the
10 * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
11 * sell copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
20 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
24 */
26 #ifndef __XEN_PUBLIC_HVM_SAVE_X86_H__
27 #define __XEN_PUBLIC_HVM_SAVE_X86_H__
29 /*
30 * Save/restore header: general info about the save file.
31 */
33 #define HVM_FILE_MAGIC 0x54381286
34 #define HVM_FILE_VERSION 0x00000001
36 struct hvm_save_header {
37 uint32_t magic; /* Must be HVM_FILE_MAGIC */
38 uint32_t version; /* File format version */
39 uint64_t changeset; /* Version of Xen that saved this file */
40 uint32_t cpuid; /* CPUID[0x01][%eax] on the saving machine */
41 uint32_t pad0;
42 };
44 DECLARE_HVM_SAVE_TYPE(HEADER, 1, struct hvm_save_header);
47 /*
48 * Processor
49 */
51 struct hvm_hw_cpu {
52 uint8_t fpu_regs[512];
54 uint64_t rax;
55 uint64_t rbx;
56 uint64_t rcx;
57 uint64_t rdx;
58 uint64_t rbp;
59 uint64_t rsi;
60 uint64_t rdi;
61 uint64_t rsp;
62 uint64_t r8;
63 uint64_t r9;
64 uint64_t r10;
65 uint64_t r11;
66 uint64_t r12;
67 uint64_t r13;
68 uint64_t r14;
69 uint64_t r15;
71 uint64_t rip;
72 uint64_t rflags;
74 uint64_t cr0;
75 uint64_t cr2;
76 uint64_t cr3;
77 uint64_t cr4;
79 uint64_t dr0;
80 uint64_t dr1;
81 uint64_t dr2;
82 uint64_t dr3;
83 uint64_t dr6;
84 uint64_t dr7;
86 uint32_t cs_sel;
87 uint32_t ds_sel;
88 uint32_t es_sel;
89 uint32_t fs_sel;
90 uint32_t gs_sel;
91 uint32_t ss_sel;
92 uint32_t tr_sel;
93 uint32_t ldtr_sel;
95 uint32_t cs_limit;
96 uint32_t ds_limit;
97 uint32_t es_limit;
98 uint32_t fs_limit;
99 uint32_t gs_limit;
100 uint32_t ss_limit;
101 uint32_t tr_limit;
102 uint32_t ldtr_limit;
103 uint32_t idtr_limit;
104 uint32_t gdtr_limit;
106 uint64_t cs_base;
107 uint64_t ds_base;
108 uint64_t es_base;
109 uint64_t fs_base;
110 uint64_t gs_base;
111 uint64_t ss_base;
112 uint64_t tr_base;
113 uint64_t ldtr_base;
114 uint64_t idtr_base;
115 uint64_t gdtr_base;
117 uint32_t cs_arbytes;
118 uint32_t ds_arbytes;
119 uint32_t es_arbytes;
120 uint32_t fs_arbytes;
121 uint32_t gs_arbytes;
122 uint32_t ss_arbytes;
123 uint32_t tr_arbytes;
124 uint32_t ldtr_arbytes;
126 uint32_t sysenter_cs;
127 uint32_t padding0;
129 uint64_t sysenter_esp;
130 uint64_t sysenter_eip;
132 /* msr for em64t */
133 uint64_t shadow_gs;
135 /* msr content saved/restored. */
136 uint64_t msr_flags;
137 uint64_t msr_lstar;
138 uint64_t msr_star;
139 uint64_t msr_cstar;
140 uint64_t msr_syscall_mask;
141 uint64_t msr_efer;
143 /* guest's idea of what rdtsc() would return */
144 uint64_t tsc;
146 /* pending event, if any */
147 union {
148 uint32_t pending_event;
149 struct {
150 uint8_t pending_vector:8;
151 uint8_t pending_type:3;
152 uint8_t pending_error_valid:1;
153 uint32_t pending_reserved:19;
154 uint8_t pending_valid:1;
155 };
156 };
157 /* error code for pending event */
158 uint32_t error_code;
159 };
161 DECLARE_HVM_SAVE_TYPE(CPU, 2, struct hvm_hw_cpu);
164 /*
165 * PIC
166 */
168 struct hvm_hw_vpic {
169 /* IR line bitmasks. */
170 uint8_t irr;
171 uint8_t imr;
172 uint8_t isr;
174 /* Line IRx maps to IRQ irq_base+x */
175 uint8_t irq_base;
177 /*
178 * Where are we in ICW2-4 initialisation (0 means no init in progress)?
179 * Bits 0-1 (=x): Next write at A=1 sets ICW(x+1).
180 * Bit 2: ICW1.IC4 (1 == ICW4 included in init sequence)
181 * Bit 3: ICW1.SNGL (0 == ICW3 included in init sequence)
182 */
183 uint8_t init_state:4;
185 /* IR line with highest priority. */
186 uint8_t priority_add:4;
188 /* Reads from A=0 obtain ISR or IRR? */
189 uint8_t readsel_isr:1;
191 /* Reads perform a polling read? */
192 uint8_t poll:1;
194 /* Automatically clear IRQs from the ISR during INTA? */
195 uint8_t auto_eoi:1;
197 /* Automatically rotate IRQ priorities during AEOI? */
198 uint8_t rotate_on_auto_eoi:1;
200 /* Exclude slave inputs when considering in-service IRQs? */
201 uint8_t special_fully_nested_mode:1;
203 /* Special mask mode excludes masked IRs from AEOI and priority checks. */
204 uint8_t special_mask_mode:1;
206 /* Is this a master PIC or slave PIC? (NB. This is not programmable.) */
207 uint8_t is_master:1;
209 /* Edge/trigger selection. */
210 uint8_t elcr;
212 /* Virtual INT output. */
213 uint8_t int_output;
214 };
216 DECLARE_HVM_SAVE_TYPE(PIC, 3, struct hvm_hw_vpic);
219 /*
220 * IO-APIC
221 */
223 #ifdef __ia64__
224 #define VIOAPIC_IS_IOSAPIC 1
225 #define VIOAPIC_NUM_PINS 24
226 #else
227 #define VIOAPIC_NUM_PINS 48 /* 16 ISA IRQs, 32 non-legacy PCI IRQS. */
228 #endif
230 struct hvm_hw_vioapic {
231 uint64_t base_address;
232 uint32_t ioregsel;
233 uint32_t id;
234 union vioapic_redir_entry
235 {
236 uint64_t bits;
237 struct {
238 uint8_t vector;
239 uint8_t delivery_mode:3;
240 uint8_t dest_mode:1;
241 uint8_t delivery_status:1;
242 uint8_t polarity:1;
243 uint8_t remote_irr:1;
244 uint8_t trig_mode:1;
245 uint8_t mask:1;
246 uint8_t reserve:7;
247 #if !VIOAPIC_IS_IOSAPIC
248 uint8_t reserved[4];
249 uint8_t dest_id;
250 #else
251 uint8_t reserved[3];
252 uint16_t dest_id;
253 #endif
254 } fields;
255 } redirtbl[VIOAPIC_NUM_PINS];
256 };
258 DECLARE_HVM_SAVE_TYPE(IOAPIC, 4, struct hvm_hw_vioapic);
261 /*
262 * LAPIC
263 */
265 struct hvm_hw_lapic {
266 uint64_t apic_base_msr;
267 uint32_t disabled; /* VLAPIC_xx_DISABLED */
268 uint32_t timer_divisor;
269 };
271 DECLARE_HVM_SAVE_TYPE(LAPIC, 5, struct hvm_hw_lapic);
273 struct hvm_hw_lapic_regs {
274 /* A 4k page of register state */
275 uint8_t data[0x400];
276 };
278 DECLARE_HVM_SAVE_TYPE(LAPIC_REGS, 6, struct hvm_hw_lapic_regs);
281 /*
282 * IRQs
283 */
285 struct hvm_hw_pci_irqs {
286 /*
287 * Virtual interrupt wires for a single PCI bus.
288 * Indexed by: device*4 + INTx#.
289 */
290 union {
291 DECLARE_BITMAP(i, 32*4);
292 uint64_t pad[2];
293 };
294 };
296 DECLARE_HVM_SAVE_TYPE(PCI_IRQ, 7, struct hvm_hw_pci_irqs);
298 struct hvm_hw_isa_irqs {
299 /*
300 * Virtual interrupt wires for ISA devices.
301 * Indexed by ISA IRQ (assumes no ISA-device IRQ sharing).
302 */
303 union {
304 DECLARE_BITMAP(i, 16);
305 uint64_t pad[1];
306 };
307 };
309 DECLARE_HVM_SAVE_TYPE(ISA_IRQ, 8, struct hvm_hw_isa_irqs);
311 struct hvm_hw_pci_link {
312 /*
313 * PCI-ISA interrupt router.
314 * Each PCI <device:INTx#> is 'wire-ORed' into one of four links using
315 * the traditional 'barber's pole' mapping ((device + INTx#) & 3).
316 * The router provides a programmable mapping from each link to a GSI.
317 */
318 uint8_t route[4];
319 uint8_t pad0[4];
320 };
322 DECLARE_HVM_SAVE_TYPE(PCI_LINK, 9, struct hvm_hw_pci_link);
324 /*
325 * PIT
326 */
328 struct hvm_hw_pit {
329 struct hvm_hw_pit_channel {
330 uint32_t count; /* can be 65536 */
331 uint16_t latched_count;
332 uint8_t count_latched;
333 uint8_t status_latched;
334 uint8_t status;
335 uint8_t read_state;
336 uint8_t write_state;
337 uint8_t write_latch;
338 uint8_t rw_mode;
339 uint8_t mode;
340 uint8_t bcd; /* not supported */
341 uint8_t gate; /* timer start */
342 } channels[3]; /* 3 x 16 bytes */
343 uint32_t speaker_data_on;
344 uint32_t pad0;
345 };
347 DECLARE_HVM_SAVE_TYPE(PIT, 10, struct hvm_hw_pit);
350 /*
351 * RTC
352 */
354 #define RTC_CMOS_SIZE 14
355 struct hvm_hw_rtc {
356 /* CMOS bytes */
357 uint8_t cmos_data[RTC_CMOS_SIZE];
358 /* Index register for 2-part operations */
359 uint8_t cmos_index;
360 uint8_t pad0;
361 };
363 DECLARE_HVM_SAVE_TYPE(RTC, 11, struct hvm_hw_rtc);
366 /*
367 * HPET
368 */
370 #define HPET_TIMER_NUM 3 /* 3 timers supported now */
371 struct hvm_hw_hpet {
372 /* Memory-mapped, software visible registers */
373 uint64_t capability; /* capabilities */
374 uint64_t res0; /* reserved */
375 uint64_t config; /* configuration */
376 uint64_t res1; /* reserved */
377 uint64_t isr; /* interrupt status reg */
378 uint64_t res2[25]; /* reserved */
379 uint64_t mc64; /* main counter */
380 uint64_t res3; /* reserved */
381 struct { /* timers */
382 uint64_t config; /* configuration/cap */
383 uint64_t cmp; /* comparator */
384 uint64_t fsb; /* FSB route, not supported now */
385 uint64_t res4; /* reserved */
386 } timers[HPET_TIMER_NUM];
387 uint64_t res5[4*(24-HPET_TIMER_NUM)]; /* reserved, up to 0x3ff */
389 /* Hidden register state */
390 uint64_t period[HPET_TIMER_NUM]; /* Last value written to comparator */
391 };
393 DECLARE_HVM_SAVE_TYPE(HPET, 12, struct hvm_hw_hpet);
396 /*
397 * PM timer
398 */
400 struct hvm_hw_pmtimer {
401 uint32_t tmr_val; /* PM_TMR_BLK.TMR_VAL: 32bit free-running counter */
402 uint16_t pm1a_sts; /* PM1a_EVT_BLK.PM1a_STS: status register */
403 uint16_t pm1a_en; /* PM1a_EVT_BLK.PM1a_EN: enable register */
404 };
406 DECLARE_HVM_SAVE_TYPE(PMTIMER, 13, struct hvm_hw_pmtimer);
408 /*
409 * Largest type-code in use
410 */
411 #define HVM_SAVE_CODE_MAX 13
413 #endif /* __XEN_PUBLIC_HVM_SAVE_X86_H__ */