ia64/xen-unstable

view xen/drivers/pci/quirks.c @ 4554:a7679ebfe9cc

bitkeeper revision 1.1159.258.99 (42641f67D11Zf7wIb-qAVu9io6tamQ)

[PATCH] IO-APIC in drivers/pci/quirks.c

This patch moves the IO-APIC include inside #ifdef CONFIG_X86_IO_APIC , which
is how Linux 2.6 has it. This is needed for architectures without
asm/io_apic.h. I've verified that x86 still builds; please apply.

Signed-off-by: Hollis Blanchard <hollisb@us.ibm.com>

===== xen/drivers/pci/quirks.c 1.9 vs edited =====
author hollisb@us.ibm.com[iap10]
date Mon Apr 18 20:58:15 2005 +0000 (2005-04-18)
parents 0e23f01219c6
children a01199a95070 3b3304b0c738
line source
1 /*
2 * $Id: quirks.c,v 1.5 1998/05/02 19:24:14 mj Exp $
3 *
4 * This file contains work-arounds for many known PCI hardware
5 * bugs. Devices present only on certain architectures (host
6 * bridges et cetera) should be handled in arch-specific code.
7 *
8 * Copyright (c) 1999 Martin Mares <mj@ucw.cz>
9 *
10 * The bridge optimization stuff has been removed. If you really
11 * have a silly BIOS which is unable to set your host bridge right,
12 * use the PowerTweak utility (see http://powertweak.sourceforge.net).
13 */
15 #include <xen/config.h>
16 #include <xen/types.h>
17 #include <xen/kernel.h>
18 #include <xen/pci.h>
19 #include <xen/init.h>
20 #include <xen/delay.h>
22 #undef DEBUG
24 /* Deal with broken BIOS'es that neglect to enable passive release,
25 which can cause problems in combination with the 82441FX/PPro MTRRs */
26 static void __init quirk_passive_release(struct pci_dev *dev)
27 {
28 struct pci_dev *d = NULL;
29 unsigned char dlc;
31 /* We have to make sure a particular bit is set in the PIIX3
32 ISA bridge, so we have to go out and find it. */
33 while ((d = pci_find_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) {
34 pci_read_config_byte(d, 0x82, &dlc);
35 if (!(dlc & 1<<1)) {
36 printk(KERN_ERR "PCI: PIIX3: Enabling Passive Release on %s\n", d->slot_name);
37 dlc |= 1<<1;
38 pci_write_config_byte(d, 0x82, dlc);
39 }
40 }
41 }
43 /* The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a workaround
44 but VIA don't answer queries. If you happen to have good contacts at VIA
45 ask them for me please -- Alan
47 This appears to be BIOS not version dependent. So presumably there is a
48 chipset level fix */
51 int isa_dma_bridge_buggy; /* Exported */
53 static void __init quirk_isa_dma_hangs(struct pci_dev *dev)
54 {
55 if (!isa_dma_bridge_buggy) {
56 isa_dma_bridge_buggy=1;
57 printk(KERN_INFO "Activating ISA DMA hang workarounds.\n");
58 }
59 }
61 int pci_pci_problems;
63 /*
64 * Chipsets where PCI->PCI transfers vanish or hang
65 */
67 static void __init quirk_nopcipci(struct pci_dev *dev)
68 {
69 if((pci_pci_problems&PCIPCI_FAIL)==0)
70 {
71 printk(KERN_INFO "Disabling direct PCI/PCI transfers.\n");
72 pci_pci_problems|=PCIPCI_FAIL;
73 }
74 }
76 /*
77 * Triton requires workarounds to be used by the drivers
78 */
80 static void __init quirk_triton(struct pci_dev *dev)
81 {
82 if((pci_pci_problems&PCIPCI_TRITON)==0)
83 {
84 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");
85 pci_pci_problems|=PCIPCI_TRITON;
86 }
87 }
89 /*
90 * VIA Apollo KT133 needs PCI latency patch
91 * Made according to a windows driver based patch by George E. Breese
92 * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm
93 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for the info on which
94 * Mr Breese based his work.
95 *
96 * Updated based on further information from the site and also on
97 * information provided by VIA
98 */
99 static void __init quirk_vialatency(struct pci_dev *dev)
100 {
101 struct pci_dev *p;
102 u8 rev;
103 u8 busarb;
104 /* Ok we have a potential problem chipset here. Now see if we have
105 a buggy southbridge */
107 p=pci_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL);
108 if(p!=NULL)
109 {
110 pci_read_config_byte(p, PCI_CLASS_REVISION, &rev);
111 /* 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; thanks Dan Hollis */
112 /* Check for buggy part revisions */
113 if (rev < 0x40 || rev > 0x42)
114 return;
115 }
116 else
117 {
118 p = pci_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL);
119 if(p==NULL) /* No problem parts */
120 return;
121 pci_read_config_byte(p, PCI_CLASS_REVISION, &rev);
122 /* Check for buggy part revisions */
123 if (rev < 0x10 || rev > 0x12)
124 return;
125 }
127 /*
128 * Ok we have the problem. Now set the PCI master grant to
129 * occur every master grant. The apparent bug is that under high
130 * PCI load (quite common in Linux of course) you can get data
131 * loss when the CPU is held off the bus for 3 bus master requests
132 * This happens to include the IDE controllers....
133 *
134 * VIA only apply this fix when an SB Live! is present but under
135 * both Linux and Windows this isnt enough, and we have seen
136 * corruption without SB Live! but with things like 3 UDMA IDE
137 * controllers. So we ignore that bit of the VIA recommendation..
138 */
140 pci_read_config_byte(dev, 0x76, &busarb);
141 /* Set bit 4 and bi 5 of byte 76 to 0x01
142 "Master priority rotation on every PCI master grant */
143 busarb &= ~(1<<5);
144 busarb |= (1<<4);
145 pci_write_config_byte(dev, 0x76, busarb);
146 printk(KERN_INFO "Applying VIA southbridge workaround.\n");
147 }
149 /*
150 * VIA Apollo VP3 needs ETBF on BT848/878
151 */
153 static void __init quirk_viaetbf(struct pci_dev *dev)
154 {
155 if((pci_pci_problems&PCIPCI_VIAETBF)==0)
156 {
157 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");
158 pci_pci_problems|=PCIPCI_VIAETBF;
159 }
160 }
161 static void __init quirk_vsfx(struct pci_dev *dev)
162 {
163 if((pci_pci_problems&PCIPCI_VSFX)==0)
164 {
165 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");
166 pci_pci_problems|=PCIPCI_VSFX;
167 }
168 }
170 /*
171 * Ali Magik requires workarounds to be used by the drivers
172 * that DMA to AGP space. Latency must be set to 0xA and triton
173 * workaround applied too
174 * [Info kindly provided by ALi]
175 */
177 static void __init quirk_alimagik(struct pci_dev *dev)
178 {
179 if((pci_pci_problems&PCIPCI_ALIMAGIK)==0)
180 {
181 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");
182 pci_pci_problems|=PCIPCI_ALIMAGIK|PCIPCI_TRITON;
183 }
184 }
186 /*
187 * Natoma has some interesting boundary conditions with Zoran stuff
188 * at least
189 */
191 static void __init quirk_natoma(struct pci_dev *dev)
192 {
193 if((pci_pci_problems&PCIPCI_NATOMA)==0)
194 {
195 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");
196 pci_pci_problems|=PCIPCI_NATOMA;
197 }
198 }
200 /*
201 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M.
202 * If it's needed, re-allocate the region.
203 */
205 static void __init quirk_s3_64M(struct pci_dev *dev)
206 {
207 struct resource *r = &dev->resource[0];
209 if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) {
210 r->start = 0;
211 r->end = 0x3ffffff;
212 }
213 }
215 static void __init quirk_io_region(struct pci_dev *dev, unsigned region, unsigned size, int nr)
216 {
217 region &= ~(size-1);
218 if (region) {
219 struct resource *res = dev->resource + nr;
221 res->name = dev->name;
222 res->start = region;
223 res->end = region + size - 1;
224 res->flags = IORESOURCE_IO;
225 pci_claim_resource(dev, nr);
226 }
227 }
229 /*
230 * ATI Northbridge setups MCE the processor if you even
231 * read somewhere between 0x3b0->0x3bb or read 0x3d3
232 */
234 static void __devinit quirk_ati_exploding_mce(struct pci_dev *dev)
235 {
236 printk(KERN_INFO "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb.\n");
237 request_region(0x3b0, 0x0C, "RadeonIGP");
238 request_region(0x3d3, 0x01, "RadeonIGP");
239 }
241 /*
242 * Let's make the southbridge information explicit instead
243 * of having to worry about people probing the ACPI areas,
244 * for example.. (Yes, it happens, and if you read the wrong
245 * ACPI register it will put the machine to sleep with no
246 * way of waking it up again. Bummer).
247 *
248 * ALI M7101: Two IO regions pointed to by words at
249 * 0xE0 (64 bytes of ACPI registers)
250 * 0xE2 (32 bytes of SMB registers)
251 */
252 static void __init quirk_ali7101_acpi(struct pci_dev *dev)
253 {
254 u16 region;
256 pci_read_config_word(dev, 0xE0, &region);
257 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES);
258 pci_read_config_word(dev, 0xE2, &region);
259 quirk_io_region(dev, region, 32, PCI_BRIDGE_RESOURCES+1);
260 }
262 /*
263 * PIIX4 ACPI: Two IO regions pointed to by longwords at
264 * 0x40 (64 bytes of ACPI registers)
265 * 0x90 (32 bytes of SMB registers)
266 */
267 static void __init quirk_piix4_acpi(struct pci_dev *dev)
268 {
269 u32 region;
271 pci_read_config_dword(dev, 0x40, &region);
272 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES);
273 pci_read_config_dword(dev, 0x90, &region);
274 quirk_io_region(dev, region, 32, PCI_BRIDGE_RESOURCES+1);
275 }
277 /*
278 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at
279 * 0x40 (128 bytes of ACPI, GPIO & TCO registers)
280 * 0x58 (64 bytes of GPIO I/O space)
281 */
282 static void __devinit quirk_ich4_lpc_acpi(struct pci_dev *dev)
283 {
284 u32 region;
286 pci_read_config_dword(dev, 0x40, &region);
287 quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES);
289 pci_read_config_dword(dev, 0x58, &region);
290 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES+1);
291 }
293 /*
294 * VIA ACPI: One IO region pointed to by longword at
295 * 0x48 or 0x20 (256 bytes of ACPI registers)
296 */
297 static void __init quirk_vt82c586_acpi(struct pci_dev *dev)
298 {
299 u8 rev;
300 u32 region;
302 pci_read_config_byte(dev, PCI_CLASS_REVISION, &rev);
303 if (rev & 0x10) {
304 pci_read_config_dword(dev, 0x48, &region);
305 region &= PCI_BASE_ADDRESS_IO_MASK;
306 quirk_io_region(dev, region, 256, PCI_BRIDGE_RESOURCES);
307 }
308 }
310 /*
311 * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at
312 * 0x48 (256 bytes of ACPI registers)
313 * 0x70 (128 bytes of hardware monitoring register)
314 * 0x90 (16 bytes of SMB registers)
315 */
316 static void __init quirk_vt82c686_acpi(struct pci_dev *dev)
317 {
318 u16 hm;
319 u32 smb;
321 quirk_vt82c586_acpi(dev);
323 pci_read_config_word(dev, 0x70, &hm);
324 hm &= PCI_BASE_ADDRESS_IO_MASK;
325 quirk_io_region(dev, hm, 128, PCI_BRIDGE_RESOURCES + 1);
327 pci_read_config_dword(dev, 0x90, &smb);
328 smb &= PCI_BASE_ADDRESS_IO_MASK;
329 quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 2);
330 }
333 #ifdef CONFIG_X86_IO_APIC
335 #include <asm/io_apic.h>
337 /*
338 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip
339 * devices to the external APIC.
340 *
341 * TODO: When we have device-specific interrupt routers,
342 * this code will go away from quirks.
343 */
344 static void __init quirk_via_ioapic(struct pci_dev *dev)
345 {
346 u8 tmp;
348 if (nr_ioapics < 1)
349 tmp = 0; /* nothing routed to external APIC */
350 else
351 tmp = 0x1f; /* all known bits (4-0) routed to external APIC */
353 printk(KERN_INFO "PCI: %sbling Via external APIC routing\n",
354 tmp == 0 ? "Disa" : "Ena");
356 /* Offset 0x58: External APIC IRQ output control */
357 pci_write_config_byte (dev, 0x58, tmp);
358 }
360 #endif /* CONFIG_X86_IO_APIC */
363 /*
364 * Via 686A/B: The PCI_INTERRUPT_LINE register for the on-chip
365 * devices, USB0/1, AC97, MC97, and ACPI, has an unusual feature:
366 * when written, it makes an internal connection to the PIC.
367 * For these devices, this register is defined to be 4 bits wide.
368 * Normally this is fine. However for IO-APIC motherboards, or
369 * non-x86 architectures (yes Via exists on PPC among other places),
370 * we must mask the PCI_INTERRUPT_LINE value versus 0xf to get
371 * interrupts delivered properly.
372 *
373 * TODO: When we have device-specific interrupt routers,
374 * quirk_via_irqpic will go away from quirks.
375 */
377 /*
378 * FIXME: it is questionable that quirk_via_acpi
379 * is needed. It shows up as an ISA bridge, and does not
380 * support the PCI_INTERRUPT_LINE register at all. Therefore
381 * it seems like setting the pci_dev's 'irq' to the
382 * value of the ACPI SCI interrupt is only done for convenience.
383 * -jgarzik
384 */
385 static void __init quirk_via_acpi(struct pci_dev *d)
386 {
387 /*
388 * VIA ACPI device: SCI IRQ line in PCI config byte 0x42
389 */
390 u8 irq;
391 pci_read_config_byte(d, 0x42, &irq);
392 irq &= 0xf;
393 if (irq && (irq != 2))
394 d->irq = irq;
395 }
397 static void __init quirk_via_irqpic(struct pci_dev *dev)
398 {
399 u8 irq, new_irq = dev->irq & 0xf;
401 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
403 if (new_irq != irq) {
404 printk(KERN_INFO "PCI: Via IRQ fixup for %s, from %d to %d\n",
405 dev->slot_name, irq, new_irq);
407 udelay(15);
408 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq);
409 }
410 }
413 /*
414 * PIIX3 USB: We have to disable USB interrupts that are
415 * hardwired to PIRQD# and may be shared with an
416 * external device.
417 *
418 * Legacy Support Register (LEGSUP):
419 * bit13: USB PIRQ Enable (USBPIRQDEN),
420 * bit4: Trap/SMI On IRQ Enable (USBSMIEN).
421 *
422 * We mask out all r/wc bits, too.
423 */
424 static void __init quirk_piix3_usb(struct pci_dev *dev)
425 {
426 u16 legsup;
428 pci_read_config_word(dev, 0xc0, &legsup);
429 legsup &= 0x50ef;
430 pci_write_config_word(dev, 0xc0, legsup);
431 }
433 /*
434 * VIA VT82C598 has its device ID settable and many BIOSes
435 * set it to the ID of VT82C597 for backward compatibility.
436 * We need to switch it off to be able to recognize the real
437 * type of the chip.
438 */
439 static void __init quirk_vt82c598_id(struct pci_dev *dev)
440 {
441 pci_write_config_byte(dev, 0xfc, 0);
442 pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device);
443 }
445 /*
446 * CardBus controllers have a legacy base address that enables them
447 * to respond as i82365 pcmcia controllers. We don't want them to
448 * do this even if the Linux CardBus driver is not loaded, because
449 * the Linux i82365 driver does not (and should not) handle CardBus.
450 */
451 static void __init quirk_cardbus_legacy(struct pci_dev *dev)
452 {
453 if ((PCI_CLASS_BRIDGE_CARDBUS << 8) ^ dev->class)
454 return;
455 pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0);
456 }
458 /*
459 * The AMD io apic can hang the box when an apic irq is masked.
460 * We check all revs >= B0 (yet not in the pre production!) as the bug
461 * is currently marked NoFix
462 *
463 * We have multiple reports of hangs with this chipset that went away with
464 * noapic specified. For the moment we assume its the errata. We may be wrong
465 * of course. However the advice is demonstrably good even if so..
466 */
468 static void __init quirk_amd_ioapic(struct pci_dev *dev)
469 {
470 u8 rev;
472 pci_read_config_byte(dev, PCI_REVISION_ID, &rev);
473 if(rev >= 0x02)
474 {
475 printk(KERN_WARNING "I/O APIC: AMD Errata #22 may be present. In the event of instability try\n");
476 printk(KERN_WARNING " : booting with the \"noapic\" option.\n");
477 }
478 }
480 /*
481 * Following the PCI ordering rules is optional on the AMD762. I'm not
482 * sure what the designers were smoking but let's not inhale...
483 *
484 * To be fair to AMD, it follows the spec by default, its BIOS people
485 * who turn it off!
486 */
488 static void __init quirk_amd_ordering(struct pci_dev *dev)
489 {
490 u32 pcic;
491 pci_read_config_dword(dev, 0x4C, &pcic);
492 if((pcic&6)!=6)
493 {
494 pcic |= 6;
495 printk(KERN_WARNING "BIOS failed to enable PCI standards compliance, fixing this error.\n");
496 pci_write_config_dword(dev, 0x4C, pcic);
497 pci_read_config_dword(dev, 0x84, &pcic);
498 pcic |= (1<<23); /* Required in this mode */
499 pci_write_config_dword(dev, 0x84, pcic);
500 }
501 }
503 #ifdef CONFIG_X86_IO_APIC
505 #define AMD8131_revA0 0x01
506 #define AMD8131_revB0 0x11
507 #define AMD8131_MISC 0x40
508 #define AMD8131_NIOAMODE_BIT 0
510 static void __init quirk_amd_8131_ioapic(struct pci_dev *dev)
511 {
512 unsigned char revid, tmp;
514 if (nr_ioapics == 0)
515 return;
517 pci_read_config_byte(dev, PCI_REVISION_ID, &revid);
518 if (revid == AMD8131_revA0 || revid == AMD8131_revB0) {
519 printk(KERN_INFO "Fixing up AMD8131 IOAPIC mode\n");
520 pci_read_config_byte( dev, AMD8131_MISC, &tmp);
521 tmp &= ~(1 << AMD8131_NIOAMODE_BIT);
522 pci_write_config_byte( dev, AMD8131_MISC, tmp);
523 }
524 }
525 #endif
528 /*
529 * DreamWorks provided workaround for Dunord I-3000 problem
530 *
531 * This card decodes and responds to addresses not apparently
532 * assigned to it. We force a larger allocation to ensure that
533 * nothing gets put too close to it.
534 */
536 static void __init quirk_dunord ( struct pci_dev * dev )
537 {
538 struct resource * r = & dev -> resource [ 1 ];
539 r -> start = 0;
540 r -> end = 0xffffff;
541 }
543 static void __init quirk_transparent_bridge(struct pci_dev *dev)
544 {
545 dev->transparent = 1;
546 }
548 /*
549 * Common misconfiguration of the MediaGX/Geode PCI master that will
550 * reduce PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1
551 * datasheets found at http://www.national.com/ds/GX for info on what
552 * these bits do. <christer@weinigel.se>
553 */
555 static void __init quirk_mediagx_master(struct pci_dev *dev)
556 {
557 u8 reg;
558 pci_read_config_byte(dev, 0x41, &reg);
559 if (reg & 2) {
560 reg &= ~2;
561 printk(KERN_INFO "PCI: Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n", reg);
562 pci_write_config_byte(dev, 0x41, reg);
563 }
564 }
566 /*
567 * As per PCI spec, ignore base address registers 0-3 of the IDE controllers
568 * running in Compatible mode (bits 0 and 2 in the ProgIf for primary and
569 * secondary channels respectively). If the device reports Compatible mode
570 * but does use BAR0-3 for address decoding, we assume that firmware has
571 * programmed these BARs with standard values (0x1f0,0x3f4 and 0x170,0x374).
572 * Exceptions (if they exist) must be handled in chip/architecture specific
573 * fixups.
574 *
575 * Note: for non x86 people. You may need an arch specific quirk to handle
576 * moving IDE devices to native mode as well. Some plug in card devices power
577 * up in compatible mode and assume the BIOS will adjust them.
578 *
579 * Q: should we load the 0x1f0,0x3f4 into the registers or zap them as
580 * we do now ? We don't want is pci_enable_device to come along
581 * and assign new resources. Both approaches work for that.
582 */
584 static void __devinit quirk_ide_bases(struct pci_dev *dev)
585 {
586 struct resource *res;
587 int first_bar = 2, last_bar = 0;
589 if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE)
590 return;
592 res = &dev->resource[0];
594 /* primary channel: ProgIf bit 0, BAR0, BAR1 */
595 if (!(dev->class & 1) && (res[0].flags || res[1].flags)) {
596 res[0].start = res[0].end = res[0].flags = 0;
597 res[1].start = res[1].end = res[1].flags = 0;
598 first_bar = 0;
599 last_bar = 1;
600 }
602 /* secondary channel: ProgIf bit 2, BAR2, BAR3 */
603 if (!(dev->class & 4) && (res[2].flags || res[3].flags)) {
604 res[2].start = res[2].end = res[2].flags = 0;
605 res[3].start = res[3].end = res[3].flags = 0;
606 last_bar = 3;
607 }
609 if (!last_bar)
610 return;
612 printk(KERN_INFO "PCI: Ignoring BAR%d-%d of IDE controller %s\n",
613 first_bar, last_bar, dev->slot_name);
614 }
616 /*
617 * Ensure C0 rev restreaming is off. This is normally done by
618 * the BIOS but in the odd case it is not the results are corruption
619 * hence the presence of a Linux check
620 */
622 static void __init quirk_disable_pxb(struct pci_dev *pdev)
623 {
624 u16 config;
625 u8 rev;
627 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev);
628 if(rev != 0x04) /* Only C0 requires this */
629 return;
630 pci_read_config_word(pdev, 0x40, &config);
631 if(config & (1<<6))
632 {
633 config &= ~(1<<6);
634 pci_write_config_word(pdev, 0x40, config);
635 printk(KERN_INFO "PCI: C0 revision 450NX. Disabling PCI restreaming.\n");
636 }
637 }
639 /*
640 * VIA northbridges care about PCI_INTERRUPT_LINE
641 */
643 int interrupt_line_quirk;
645 static void __init quirk_via_bridge(struct pci_dev *pdev)
646 {
647 if(pdev->devfn == 0)
648 interrupt_line_quirk = 1;
649 }
651 /*
652 * Serverworks CSB5 IDE does not fully support native mode
653 */
654 static void __init quirk_svwks_csb5ide(struct pci_dev *pdev)
655 {
656 u8 prog;
657 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
658 if (prog & 5) {
659 prog &= ~5;
660 pdev->class &= ~5;
661 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
662 /* need to re-assign BARs for compat mode */
663 quirk_ide_bases(pdev);
664 }
665 }
667 /*
668 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge
669 * is not activated. The myth is that Asus said that they do not want the
670 * users to be irritated by just another PCI Device in the Win98 device
671 * manager. (see the file prog/hotplug/README.p4b in the lm_sensors
672 * package 2.7.0 for details)
673 *
674 * The SMBus PCI Device can be activated by setting a bit in the ICH LPC
675 * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it
676 * becomes necessary to do this tweak in two steps -- I've chosen the Host
677 * bridge as trigger.
678 */
680 static int __initdata asus_hides_smbus = 0;
682 static void __init asus_hides_smbus_hostbridge(struct pci_dev *dev)
683 {
684 if (likely(dev->subsystem_vendor != PCI_VENDOR_ID_ASUSTEK))
685 return;
687 if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB)
688 switch(dev->subsystem_device) {
689 case 0x8070: /* P4B */
690 case 0x8088: /* P4B533 */
691 asus_hides_smbus = 1;
692 }
693 if ((dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) &&
694 (dev->subsystem_device == 0x80b2)) /* P4PE */
695 asus_hides_smbus = 1;
696 if ((dev->device == PCI_DEVICE_ID_INTEL_82850_HB) &&
697 (dev->subsystem_device == 0x8030)) /* P4T533 */
698 asus_hides_smbus = 1;
699 if ((dev->device == PCI_DEVICE_ID_INTEL_7205_0) &&
700 (dev->subsystem_device == 0x8070)) /* P4G8X Deluxe */
701 asus_hides_smbus = 1;
702 return;
703 }
705 static void __init asus_hides_smbus_lpc(struct pci_dev *dev)
706 {
707 u16 val;
709 if (likely(!asus_hides_smbus))
710 return;
712 pci_read_config_word(dev, 0xF2, &val);
713 if (val & 0x8) {
714 pci_write_config_word(dev, 0xF2, val & (~0x8));
715 pci_read_config_word(dev, 0xF2, &val);
716 if(val & 0x8)
717 printk(KERN_INFO "PCI: i801 SMBus device continues to play 'hide and seek'! 0x%x\n", val);
718 else
719 printk(KERN_INFO "PCI: Enabled i801 SMBus device\n");
720 }
721 }
723 /*
724 * The main table of quirks.
725 */
727 static struct pci_fixup pci_fixups[] __initdata = {
728 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord },
729 { PCI_FIXUP_FINAL, PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release },
730 { PCI_FIXUP_FINAL, PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release },
731 /*
732 * Its not totally clear which chipsets are the problematic ones
733 * We know 82C586 and 82C596 variants are affected.
734 */
735 { PCI_FIXUP_FINAL, PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs },
736 { PCI_FIXUP_FINAL, PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs },
737 { PCI_FIXUP_FINAL, PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs },
738 { PCI_FIXUP_FINAL, PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb },
739 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M },
740 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M },
741 { PCI_FIXUP_FINAL, PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton },
742 { PCI_FIXUP_FINAL, PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton },
743 { PCI_FIXUP_FINAL, PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton },
744 { PCI_FIXUP_FINAL, PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton },
745 { PCI_FIXUP_FINAL, PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma },
746 { PCI_FIXUP_FINAL, PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma },
747 { PCI_FIXUP_FINAL, PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma },
748 { PCI_FIXUP_FINAL, PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma },
749 { PCI_FIXUP_FINAL, PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma },
750 { PCI_FIXUP_FINAL, PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma },
751 { PCI_FIXUP_FINAL, PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik },
752 { PCI_FIXUP_FINAL, PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik },
753 { PCI_FIXUP_FINAL, PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci },
754 { PCI_FIXUP_FINAL, PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci },
755 { PCI_FIXUP_FINAL, PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency },
756 { PCI_FIXUP_FINAL, PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency },
757 { PCI_FIXUP_FINAL, PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency },
758 { PCI_FIXUP_FINAL, PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx },
759 { PCI_FIXUP_FINAL, PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf },
760 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id },
761 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi },
762 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi },
763 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi },
764 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi },
765 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi },
766 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_2, quirk_piix3_usb },
767 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_2, quirk_piix3_usb },
768 { PCI_FIXUP_HEADER, PCI_ANY_ID, PCI_ANY_ID, quirk_ide_bases },
769 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_bridge },
770 { PCI_FIXUP_FINAL, PCI_ANY_ID, PCI_ANY_ID, quirk_cardbus_legacy },
772 #ifdef CONFIG_X86_IO_APIC
773 { PCI_FIXUP_FINAL, PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic },
774 #endif
775 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi },
776 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi },
777 { PCI_FIXUP_FINAL, PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_2, quirk_via_irqpic },
778 { PCI_FIXUP_FINAL, PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_5, quirk_via_irqpic },
779 { PCI_FIXUP_FINAL, PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_6, quirk_via_irqpic },
781 { PCI_FIXUP_FINAL, PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic },
782 { PCI_FIXUP_FINAL, PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering },
783 { PCI_FIXUP_FINAL, PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_IGP, quirk_ati_exploding_mce },
784 /*
785 * i82380FB mobile docking controller: its PCI-to-PCI bridge
786 * is subtractive decoding (transparent), and does indicate this
787 * in the ProgIf. Unfortunately, the ProgIf value is wrong - 0x80
788 * instead of 0x01.
789 */
790 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge },
791 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge },
793 { PCI_FIXUP_FINAL, PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master },
795 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide },
797 #ifdef CONFIG_X86_IO_APIC
798 { PCI_FIXUP_FINAL, PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_APIC,
799 quirk_amd_8131_ioapic },
800 #endif
802 /*
803 * on Asus P4B boards, the i801SMBus device is disabled at startup.
804 */
805 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge },
806 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge },
807 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge },
808 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge },
809 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc },
810 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc },
812 { 0 }
813 };
816 static void pci_do_fixups(struct pci_dev *dev, int pass, struct pci_fixup *f)
817 {
818 while (f->pass) {
819 if (f->pass == pass &&
820 (f->vendor == dev->vendor || f->vendor == (u16) PCI_ANY_ID) &&
821 (f->device == dev->device || f->device == (u16) PCI_ANY_ID)) {
822 #ifdef DEBUG
823 printk(KERN_INFO "PCI: Calling quirk %p for %s\n", f->hook, dev->slot_name);
824 #endif
825 f->hook(dev);
826 }
827 f++;
828 }
829 }
831 void pci_fixup_device(int pass, struct pci_dev *dev)
832 {
833 pci_do_fixups(dev, pass, pcibios_fixups);
834 pci_do_fixups(dev, pass, pci_fixups);
835 }