ia64/xen-unstable

view xen/include/asm-x86/hvm/vlapic.h @ 10908:a6cb8ba24a91

[HVM] Place all APIC registers into one page in native format.
With this change we can re-use code at include/asm-x86/apicdef.h,
making the code much cleaner. Also it help for future enhancement.

This patch does not change any logic except the change to
CONTROL_REG_ACCESS_NUM, which should be 0xf for CR8 access.

Signed-off-by: Yunhong Jiang <yunhong.jiang@intel.com
author kfraser@localhost.localdomain
date Wed Aug 02 10:07:03 2006 +0100 (2006-08-02)
parents 30a5eb240a20
children 3e31c5e160cf
line source
1 /*
2 * hvm_vlapic.h: virtualize LAPIC definitions.
3 *
4 * Copyright (c) 2004, Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along with
16 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
17 * Place - Suite 330, Boston, MA 02111-1307 USA.
18 */
20 #ifndef __ASM_X86_HVM_VLAPIC_H__
21 #define __ASM_X86_HVM_VLAPIC_H__
23 #include <asm/msr.h>
24 #include <public/hvm/ioreq.h>
26 static __inline__ int find_highest_bit(unsigned long *data, int nr_bits)
27 {
28 int length = BITS_TO_LONGS(nr_bits);
29 while ( length && !data[--length] )
30 continue;
31 return (fls(data[length]) - 1) + (length * BITS_PER_LONG);
32 }
34 #define VLAPIC(v) (v->arch.hvm_vcpu.vlapic)
36 #define VLAPIC_VERSION 0x00050014
38 #define VLOCAL_APIC_MEM_LENGTH (1 << 12)
40 #define VLAPIC_LVT_NUM 6
42 #define VLAPIC_ID(vlapic) \
43 (GET_APIC_ID(vlapic_get_reg(vlapic, APIC_ID)))
45 /* followed define is not in apicdef.h */
46 #define APIC_SHORT_MASK 0xc0000
47 #define APIC_DEST_NOSHORT 0x0
48 #define APIC_DEST_MASK 0x800
50 #define vlapic_lvt_enabled(vlapic, lvt_type) \
51 (!(vlapic_get_reg(vlapic, lvt_type) & APIC_LVT_MASKED))
53 #define vlapic_lvt_vector(vlapic, lvt_type) \
54 (vlapic_get_reg(vlapic, lvt_type) & APIC_VECTOR_MASK)
56 #define vlapic_lvt_dm(vlapic, lvt_type) \
57 (vlapic_get_reg(vlapic, lvt_type) & APIC_MODE_MASK)
59 #define vlapic_lvtt_period(vlapic) \
60 (vlapic_get_reg(vlapic, APIC_LVTT) & APIC_LVT_TIMER_PERIODIC)
62 #define _VLAPIC_GLOB_DISABLE 0x0
63 #define VLAPIC_GLOB_DISABLE_MASK 0x1
64 #define VLAPIC_SOFTWARE_DISABLE_MASK 0x2
65 #define _VLAPIC_BSP_ACCEPT_PIC 0x3
67 #define vlapic_enabled(vlapic) \
68 (!((vlapic)->status & \
69 (VLAPIC_GLOB_DISABLE_MASK | VLAPIC_SOFTWARE_DISABLE_MASK)))
71 #define vlapic_global_enabled(vlapic) \
72 (!(test_bit(_VLAPIC_GLOB_DISABLE, &(vlapic)->status)))
74 #define LVT_MASK \
75 APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK
77 #define LINT_MASK \
78 LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY |\
79 APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER
81 typedef struct direct_intr_info {
82 int deliver_mode;
83 int source[6];
84 } direct_intr_info_t;
86 #define MAX_VECTOR 256
88 struct vlapic {
89 uint32_t status;
90 uint32_t vcpu_id;
91 uint64_t apic_base_msr;
92 unsigned long base_address;
93 uint32_t timer_divide_count;
94 struct timer vlapic_timer;
95 int intr_pending_count[MAX_VECTOR];
96 s_time_t timer_last_update;
97 direct_intr_info_t direct_intr;
98 uint32_t err_status;
99 uint32_t err_write_count;
100 struct vcpu *vcpu;
101 struct domain *domain;
102 struct page_info *regs_page;
103 void *regs;
104 };
106 static inline int vlapic_set_irq(struct vlapic *vlapic,
107 uint8_t vec, uint8_t trig)
108 {
109 int ret;
111 ret = test_and_set_bit(vec, vlapic->regs + APIC_IRR);
112 if ( trig )
113 set_bit(vec, vlapic->regs + APIC_TMR);
115 /* We may need to wake up target vcpu, besides set pending bit here */
116 return ret;
117 }
119 static inline uint32_t vlapic_get_reg(struct vlapic *vlapic, uint32_t reg)
120 {
121 return *( (uint32_t *)(vlapic->regs + reg));
122 }
124 static inline void vlapic_set_reg(struct vlapic *vlapic,
125 uint32_t reg, uint32_t val)
126 {
127 *((uint32_t *)(vlapic->regs + reg)) = val;
128 }
131 void vlapic_post_injection(struct vcpu* v, int vector, int deliver_mode);
133 int cpu_has_apic_interrupt(struct vcpu* v);
134 int cpu_get_apic_interrupt(struct vcpu* v, int *mode);
136 extern int vlapic_init(struct vcpu *vc);
138 extern void vlapic_msr_set(struct vlapic *vlapic, uint64_t value);
140 int vlapic_accept_pic_intr(struct vcpu *v);
142 struct vlapic* apic_round_robin(struct domain *d,
143 uint8_t dest_mode,
144 uint8_t vector,
145 uint32_t bitmap);
147 s_time_t get_apictime_scheduled(struct vcpu *v);
149 int hvm_apic_support(struct domain *d);
151 #endif /* __ASM_X86_HVM_VLAPIC_H__ */