ia64/xen-unstable

view xen/arch/x86/hvm/vmx/vmx.c @ 10908:a6cb8ba24a91

[HVM] Place all APIC registers into one page in native format.
With this change we can re-use code at include/asm-x86/apicdef.h,
making the code much cleaner. Also it help for future enhancement.

This patch does not change any logic except the change to
CONTROL_REG_ACCESS_NUM, which should be 0xf for CR8 access.

Signed-off-by: Yunhong Jiang <yunhong.jiang@intel.com
author kfraser@localhost.localdomain
date Wed Aug 02 10:07:03 2006 +0100 (2006-08-02)
parents 822c39808e62
children 7e7552112954
line source
1 /*
2 * vmx.c: handling VMX architecture-related VM exits
3 * Copyright (c) 2004, Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
16 * Place - Suite 330, Boston, MA 02111-1307 USA.
17 *
18 */
20 #include <xen/config.h>
21 #include <xen/init.h>
22 #include <xen/lib.h>
23 #include <xen/trace.h>
24 #include <xen/sched.h>
25 #include <xen/irq.h>
26 #include <xen/softirq.h>
27 #include <xen/domain_page.h>
28 #include <asm/current.h>
29 #include <asm/io.h>
30 #include <asm/shadow.h>
31 #include <asm/regs.h>
32 #include <asm/cpufeature.h>
33 #include <asm/processor.h>
34 #include <asm/types.h>
35 #include <asm/msr.h>
36 #include <asm/spinlock.h>
37 #include <asm/hvm/hvm.h>
38 #include <asm/hvm/support.h>
39 #include <asm/hvm/vmx/vmx.h>
40 #include <asm/hvm/vmx/vmcs.h>
41 #include <asm/hvm/vmx/cpu.h>
42 #include <asm/shadow.h>
43 #if CONFIG_PAGING_LEVELS >= 3
44 #include <asm/shadow_64.h>
45 #endif
46 #include <public/sched.h>
47 #include <public/hvm/ioreq.h>
48 #include <asm/hvm/vpic.h>
49 #include <asm/hvm/vlapic.h>
51 static unsigned long trace_values[NR_CPUS][5];
52 #define TRACE_VMEXIT(index,value) trace_values[smp_processor_id()][index]=value
54 static void vmx_ctxt_switch_from(struct vcpu *v);
55 static void vmx_ctxt_switch_to(struct vcpu *v);
57 static int vmx_initialize_guest_resources(struct vcpu *v)
58 {
59 struct domain *d = v->domain;
60 struct vcpu *vc;
61 void *io_bitmap_a, *io_bitmap_b;
62 int rc;
64 v->arch.schedule_tail = arch_vmx_do_launch;
65 v->arch.ctxt_switch_from = vmx_ctxt_switch_from;
66 v->arch.ctxt_switch_to = vmx_ctxt_switch_to;
68 if ( v->vcpu_id != 0 )
69 return 1;
71 for_each_vcpu ( d, vc )
72 {
73 /* Initialize monitor page table */
74 vc->arch.monitor_table = pagetable_null();
76 memset(&vc->arch.hvm_vmx, 0, sizeof(struct arch_vmx_struct));
78 if ( (rc = vmx_create_vmcs(vc)) != 0 )
79 {
80 DPRINTK("Failed to create VMCS for vcpu %d: err=%d.\n",
81 vc->vcpu_id, rc);
82 return 0;
83 }
85 spin_lock_init(&vc->arch.hvm_vmx.vmcs_lock);
87 if ( (io_bitmap_a = alloc_xenheap_pages(IO_BITMAP_ORDER)) == NULL )
88 {
89 DPRINTK("Failed to allocate io bitmap b for vcpu %d.\n",
90 vc->vcpu_id);
91 return 0;
92 }
94 if ( (io_bitmap_b = alloc_xenheap_pages(IO_BITMAP_ORDER)) == NULL )
95 {
96 DPRINTK("Failed to allocate io bitmap b for vcpu %d.\n",
97 vc->vcpu_id);
98 return 0;
99 }
101 memset(io_bitmap_a, 0xff, 0x1000);
102 memset(io_bitmap_b, 0xff, 0x1000);
104 /* don't bother debug port access */
105 clear_bit(PC_DEBUG_PORT, io_bitmap_a);
107 vc->arch.hvm_vmx.io_bitmap_a = io_bitmap_a;
108 vc->arch.hvm_vmx.io_bitmap_b = io_bitmap_b;
109 }
111 /*
112 * Required to do this once per domain XXX todo: add a seperate function
113 * to do these.
114 */
115 memset(&d->shared_info->evtchn_mask[0], 0xff,
116 sizeof(d->shared_info->evtchn_mask));
118 /* Put the domain in shadow mode even though we're going to be using
119 * the shared 1:1 page table initially. It shouldn't hurt */
120 shadow_mode_enable(
121 d, SHM_enable|SHM_refcounts|SHM_translate|SHM_external|SHM_wr_pt_pte);
123 return 1;
124 }
126 static void vmx_relinquish_guest_resources(struct domain *d)
127 {
128 struct vcpu *v;
130 for_each_vcpu ( d, v )
131 {
132 vmx_destroy_vmcs(v);
133 if ( !test_bit(_VCPUF_initialised, &v->vcpu_flags) )
134 continue;
135 free_monitor_pagetable(v);
136 kill_timer(&v->arch.hvm_vmx.hlt_timer);
137 if ( hvm_apic_support(v->domain) && (VLAPIC(v) != NULL) )
138 {
139 kill_timer(&VLAPIC(v)->vlapic_timer);
140 unmap_domain_page_global(VLAPIC(v)->regs);
141 free_domheap_page(VLAPIC(v)->regs_page);
142 xfree(VLAPIC(v));
143 }
144 }
146 kill_timer(&d->arch.hvm_domain.pl_time.periodic_tm.timer);
148 if ( d->arch.hvm_domain.shared_page_va )
149 unmap_domain_page_global(
150 (void *)d->arch.hvm_domain.shared_page_va);
152 shadow_direct_map_clean(d);
153 }
155 #ifdef __x86_64__
157 static struct vmx_msr_state percpu_msr[NR_CPUS];
159 static u32 msr_data_index[VMX_MSR_COUNT] =
160 {
161 MSR_LSTAR, MSR_STAR, MSR_CSTAR,
162 MSR_SYSCALL_MASK, MSR_EFER,
163 };
165 static void vmx_save_segments(struct vcpu *v)
166 {
167 rdmsrl(MSR_SHADOW_GS_BASE, v->arch.hvm_vmx.msr_content.shadow_gs);
168 }
170 /*
171 * To avoid MSR save/restore at every VM exit/entry time, we restore
172 * the x86_64 specific MSRs at domain switch time. Since those MSRs are
173 * are not modified once set for generic domains, we don't save them,
174 * but simply reset them to the values set at percpu_traps_init().
175 */
176 static void vmx_load_msrs(void)
177 {
178 struct vmx_msr_state *host_state = &percpu_msr[smp_processor_id()];
179 int i;
181 while ( host_state->flags )
182 {
183 i = find_first_set_bit(host_state->flags);
184 wrmsrl(msr_data_index[i], host_state->msr_items[i]);
185 clear_bit(i, &host_state->flags);
186 }
187 }
189 static void vmx_save_init_msrs(void)
190 {
191 struct vmx_msr_state *host_state = &percpu_msr[smp_processor_id()];
192 int i;
194 for ( i = 0; i < VMX_MSR_COUNT; i++ )
195 rdmsrl(msr_data_index[i], host_state->msr_items[i]);
196 }
198 #define CASE_READ_MSR(address) \
199 case MSR_ ## address: \
200 msr_content = msr->msr_items[VMX_INDEX_MSR_ ## address]; \
201 break
203 #define CASE_WRITE_MSR(address) \
204 case MSR_ ## address: \
205 { \
206 msr->msr_items[VMX_INDEX_MSR_ ## address] = msr_content; \
207 if (!test_bit(VMX_INDEX_MSR_ ## address, &msr->flags)) { \
208 set_bit(VMX_INDEX_MSR_ ## address, &msr->flags); \
209 } \
210 wrmsrl(MSR_ ## address, msr_content); \
211 set_bit(VMX_INDEX_MSR_ ## address, &host_state->flags); \
212 } \
213 break
215 #define IS_CANO_ADDRESS(add) 1
216 static inline int long_mode_do_msr_read(struct cpu_user_regs *regs)
217 {
218 u64 msr_content = 0;
219 struct vcpu *v = current;
220 struct vmx_msr_state *msr = &v->arch.hvm_vmx.msr_content;
222 switch ( regs->ecx ) {
223 case MSR_EFER:
224 HVM_DBG_LOG(DBG_LEVEL_2, "EFER msr_content 0x%"PRIx64, msr_content);
225 msr_content = msr->msr_items[VMX_INDEX_MSR_EFER];
227 /* the following code may be not needed */
228 if ( test_bit(VMX_CPU_STATE_LME_ENABLED, &v->arch.hvm_vmx.cpu_state) )
229 msr_content |= EFER_LME;
230 else
231 msr_content &= ~EFER_LME;
233 if ( VMX_LONG_GUEST(v) )
234 msr_content |= EFER_LMA;
235 else
236 msr_content &= ~EFER_LMA;
237 break;
239 case MSR_FS_BASE:
240 if ( !(VMX_LONG_GUEST(v)) )
241 /* XXX should it be GP fault */
242 domain_crash_synchronous();
244 __vmread(GUEST_FS_BASE, &msr_content);
245 break;
247 case MSR_GS_BASE:
248 if ( !(VMX_LONG_GUEST(v)) )
249 domain_crash_synchronous();
251 __vmread(GUEST_GS_BASE, &msr_content);
252 break;
254 case MSR_SHADOW_GS_BASE:
255 msr_content = msr->shadow_gs;
256 break;
258 CASE_READ_MSR(STAR);
259 CASE_READ_MSR(LSTAR);
260 CASE_READ_MSR(CSTAR);
261 CASE_READ_MSR(SYSCALL_MASK);
263 default:
264 return 0;
265 }
267 HVM_DBG_LOG(DBG_LEVEL_2, "msr_content: 0x%"PRIx64, msr_content);
269 regs->eax = msr_content & 0xffffffff;
270 regs->edx = msr_content >> 32;
272 return 1;
273 }
275 static inline int long_mode_do_msr_write(struct cpu_user_regs *regs)
276 {
277 u64 msr_content = regs->eax | ((u64)regs->edx << 32);
278 struct vcpu *v = current;
279 struct vmx_msr_state *msr = &v->arch.hvm_vmx.msr_content;
280 struct vmx_msr_state *host_state = &percpu_msr[smp_processor_id()];
282 HVM_DBG_LOG(DBG_LEVEL_1, "msr 0x%lx msr_content 0x%"PRIx64"\n",
283 (unsigned long)regs->ecx, msr_content);
285 switch ( regs->ecx ) {
286 case MSR_EFER:
287 /* offending reserved bit will cause #GP */
288 if ( msr_content & ~(EFER_LME | EFER_LMA | EFER_NX | EFER_SCE) )
289 {
290 printk("trying to set reserved bit in EFER\n");
291 vmx_inject_hw_exception(v, TRAP_gp_fault, 0);
292 return 0;
293 }
295 /* LME: 0 -> 1 */
296 if ( msr_content & EFER_LME &&
297 !test_bit(VMX_CPU_STATE_LME_ENABLED, &v->arch.hvm_vmx.cpu_state) )
298 {
299 if ( vmx_paging_enabled(v) ||
300 !test_bit(VMX_CPU_STATE_PAE_ENABLED,
301 &v->arch.hvm_vmx.cpu_state) )
302 {
303 printk("trying to set LME bit when "
304 "in paging mode or PAE bit is not set\n");
305 vmx_inject_hw_exception(v, TRAP_gp_fault, 0);
306 return 0;
307 }
309 set_bit(VMX_CPU_STATE_LME_ENABLED, &v->arch.hvm_vmx.cpu_state);
310 }
312 msr->msr_items[VMX_INDEX_MSR_EFER] = msr_content;
313 break;
315 case MSR_FS_BASE:
316 case MSR_GS_BASE:
317 if ( !(VMX_LONG_GUEST(v)) )
318 domain_crash_synchronous();
320 if ( !IS_CANO_ADDRESS(msr_content) )
321 {
322 HVM_DBG_LOG(DBG_LEVEL_1, "Not cano address of msr write\n");
323 vmx_inject_hw_exception(v, TRAP_gp_fault, 0);
324 return 0;
325 }
327 if ( regs->ecx == MSR_FS_BASE )
328 __vmwrite(GUEST_FS_BASE, msr_content);
329 else
330 __vmwrite(GUEST_GS_BASE, msr_content);
332 break;
334 case MSR_SHADOW_GS_BASE:
335 if ( !(VMX_LONG_GUEST(v)) )
336 domain_crash_synchronous();
338 v->arch.hvm_vmx.msr_content.shadow_gs = msr_content;
339 wrmsrl(MSR_SHADOW_GS_BASE, msr_content);
340 break;
342 CASE_WRITE_MSR(STAR);
343 CASE_WRITE_MSR(LSTAR);
344 CASE_WRITE_MSR(CSTAR);
345 CASE_WRITE_MSR(SYSCALL_MASK);
347 default:
348 return 0;
349 }
351 return 1;
352 }
354 static void vmx_restore_msrs(struct vcpu *v)
355 {
356 int i = 0;
357 struct vmx_msr_state *guest_state;
358 struct vmx_msr_state *host_state;
359 unsigned long guest_flags ;
361 guest_state = &v->arch.hvm_vmx.msr_content;;
362 host_state = &percpu_msr[smp_processor_id()];
364 wrmsrl(MSR_SHADOW_GS_BASE, guest_state->shadow_gs);
365 guest_flags = guest_state->flags;
366 if (!guest_flags)
367 return;
369 while (guest_flags){
370 i = find_first_set_bit(guest_flags);
372 HVM_DBG_LOG(DBG_LEVEL_2,
373 "restore guest's index %d msr %lx with %lx\n",
374 i, (unsigned long)msr_data_index[i],
375 (unsigned long)guest_state->msr_items[i]);
376 set_bit(i, &host_state->flags);
377 wrmsrl(msr_data_index[i], guest_state->msr_items[i]);
378 clear_bit(i, &guest_flags);
379 }
380 }
382 #else /* __i386__ */
384 #define vmx_save_segments(v) ((void)0)
385 #define vmx_load_msrs() ((void)0)
386 #define vmx_restore_msrs(v) ((void)0)
387 #define vmx_save_init_msrs() ((void)0)
389 static inline int long_mode_do_msr_read(struct cpu_user_regs *regs)
390 {
391 return 0;
392 }
394 static inline int long_mode_do_msr_write(struct cpu_user_regs *regs)
395 {
396 return 0;
397 }
399 #endif /* __i386__ */
401 #define loaddebug(_v,_reg) \
402 __asm__ __volatile__ ("mov %0,%%db" #_reg : : "r" ((_v)->debugreg[_reg]))
403 #define savedebug(_v,_reg) \
404 __asm__ __volatile__ ("mov %%db" #_reg ",%0" : : "r" ((_v)->debugreg[_reg]))
406 static inline void vmx_save_dr(struct vcpu *v)
407 {
408 if ( v->arch.hvm_vcpu.flag_dr_dirty )
409 {
410 savedebug(&v->arch.guest_context, 0);
411 savedebug(&v->arch.guest_context, 1);
412 savedebug(&v->arch.guest_context, 2);
413 savedebug(&v->arch.guest_context, 3);
414 savedebug(&v->arch.guest_context, 6);
416 v->arch.hvm_vcpu.flag_dr_dirty = 0;
418 v->arch.hvm_vcpu.u.vmx.exec_control |= CPU_BASED_MOV_DR_EXITING;
419 __vmwrite(CPU_BASED_VM_EXEC_CONTROL,
420 v->arch.hvm_vcpu.u.vmx.exec_control);
421 }
422 }
424 static inline void __restore_debug_registers(struct vcpu *v)
425 {
426 loaddebug(&v->arch.guest_context, 0);
427 loaddebug(&v->arch.guest_context, 1);
428 loaddebug(&v->arch.guest_context, 2);
429 loaddebug(&v->arch.guest_context, 3);
430 /* No 4 and 5 */
431 loaddebug(&v->arch.guest_context, 6);
432 /* DR7 is loaded from the vmcs. */
433 }
435 /*
436 * DR7 is saved and restored on every vmexit. Other debug registers only
437 * need to be restored if their value is going to affect execution -- i.e.,
438 * if one of the breakpoints is enabled. So mask out all bits that don't
439 * enable some breakpoint functionality.
440 *
441 * This is in part necessary because bit 10 of DR7 is hardwired to 1, so a
442 * simple if( guest_dr7 ) will always return true. As long as we're masking,
443 * we might as well do it right.
444 */
445 #define DR7_ACTIVE_MASK 0xff
447 static inline void vmx_restore_dr(struct vcpu *v)
448 {
449 unsigned long guest_dr7;
451 __vmread(GUEST_DR7, &guest_dr7);
453 /* Assumes guest does not have DR access at time of context switch. */
454 if ( unlikely(guest_dr7 & DR7_ACTIVE_MASK) )
455 __restore_debug_registers(v);
456 }
458 static void vmx_freeze_time(struct vcpu *v)
459 {
460 struct periodic_time *pt=&v->domain->arch.hvm_domain.pl_time.periodic_tm;
462 if ( pt->enabled && pt->first_injected && !v->arch.hvm_vcpu.guest_time ) {
463 v->arch.hvm_vcpu.guest_time = hvm_get_guest_time(v);
464 stop_timer(&(pt->timer));
465 }
466 }
468 static void vmx_ctxt_switch_from(struct vcpu *v)
469 {
470 vmx_freeze_time(v);
471 vmx_save_segments(v);
472 vmx_load_msrs();
473 vmx_save_dr(v);
474 }
476 static void vmx_ctxt_switch_to(struct vcpu *v)
477 {
478 vmx_restore_msrs(v);
479 vmx_restore_dr(v);
480 }
482 static void stop_vmx(void)
483 {
484 if (read_cr4() & X86_CR4_VMXE)
485 __vmxoff();
486 }
488 void vmx_migrate_timers(struct vcpu *v)
489 {
490 struct periodic_time *pt = &(v->domain->arch.hvm_domain.pl_time.periodic_tm);
492 if ( pt->enabled ) {
493 migrate_timer(&pt->timer, v->processor);
494 migrate_timer(&v->arch.hvm_vmx.hlt_timer, v->processor);
495 }
496 if ( hvm_apic_support(v->domain) && VLAPIC(v))
497 migrate_timer(&(VLAPIC(v)->vlapic_timer), v->processor);
498 }
500 static void vmx_store_cpu_guest_regs(
501 struct vcpu *v, struct cpu_user_regs *regs, unsigned long *crs)
502 {
503 vmx_vmcs_enter(v);
505 if ( regs != NULL )
506 {
507 __vmread(GUEST_RFLAGS, &regs->eflags);
508 __vmread(GUEST_SS_SELECTOR, &regs->ss);
509 __vmread(GUEST_CS_SELECTOR, &regs->cs);
510 __vmread(GUEST_DS_SELECTOR, &regs->ds);
511 __vmread(GUEST_ES_SELECTOR, &regs->es);
512 __vmread(GUEST_GS_SELECTOR, &regs->gs);
513 __vmread(GUEST_FS_SELECTOR, &regs->fs);
514 __vmread(GUEST_RIP, &regs->eip);
515 __vmread(GUEST_RSP, &regs->esp);
516 }
518 if ( crs != NULL )
519 {
520 __vmread(CR0_READ_SHADOW, &crs[0]);
521 __vmread(GUEST_CR3, &crs[3]);
522 __vmread(CR4_READ_SHADOW, &crs[4]);
523 }
525 vmx_vmcs_exit(v);
526 }
528 /*
529 * The VMX spec (section 4.3.1.2, Checks on Guest Segment
530 * Registers) says that virtual-8086 mode guests' segment
531 * base-address fields in the VMCS must be equal to their
532 * corresponding segment selector field shifted right by
533 * four bits upon vmentry.
534 *
535 * This function (called only for VM86-mode guests) fixes
536 * the bases to be consistent with the selectors in regs
537 * if they're not already. Without this, we can fail the
538 * vmentry check mentioned above.
539 */
540 static void fixup_vm86_seg_bases(struct cpu_user_regs *regs)
541 {
542 int err = 0;
543 unsigned long base;
545 err |= __vmread(GUEST_ES_BASE, &base);
546 if (regs->es << 4 != base)
547 err |= __vmwrite(GUEST_ES_BASE, regs->es << 4);
548 err |= __vmread(GUEST_CS_BASE, &base);
549 if (regs->cs << 4 != base)
550 err |= __vmwrite(GUEST_CS_BASE, regs->cs << 4);
551 err |= __vmread(GUEST_SS_BASE, &base);
552 if (regs->ss << 4 != base)
553 err |= __vmwrite(GUEST_SS_BASE, regs->ss << 4);
554 err |= __vmread(GUEST_DS_BASE, &base);
555 if (regs->ds << 4 != base)
556 err |= __vmwrite(GUEST_DS_BASE, regs->ds << 4);
557 err |= __vmread(GUEST_FS_BASE, &base);
558 if (regs->fs << 4 != base)
559 err |= __vmwrite(GUEST_FS_BASE, regs->fs << 4);
560 err |= __vmread(GUEST_GS_BASE, &base);
561 if (regs->gs << 4 != base)
562 err |= __vmwrite(GUEST_GS_BASE, regs->gs << 4);
564 BUG_ON(err);
565 }
567 static void vmx_load_cpu_guest_regs(struct vcpu *v, struct cpu_user_regs *regs)
568 {
569 vmx_vmcs_enter(v);
571 __vmwrite(GUEST_SS_SELECTOR, regs->ss);
572 __vmwrite(GUEST_DS_SELECTOR, regs->ds);
573 __vmwrite(GUEST_ES_SELECTOR, regs->es);
574 __vmwrite(GUEST_GS_SELECTOR, regs->gs);
575 __vmwrite(GUEST_FS_SELECTOR, regs->fs);
577 __vmwrite(GUEST_RSP, regs->esp);
579 __vmwrite(GUEST_RFLAGS, regs->eflags);
580 if (regs->eflags & EF_TF)
581 __vm_set_bit(EXCEPTION_BITMAP, EXCEPTION_BITMAP_DB);
582 else
583 __vm_clear_bit(EXCEPTION_BITMAP, EXCEPTION_BITMAP_DB);
584 if (regs->eflags & EF_VM)
585 fixup_vm86_seg_bases(regs);
587 __vmwrite(GUEST_CS_SELECTOR, regs->cs);
588 __vmwrite(GUEST_RIP, regs->eip);
590 vmx_vmcs_exit(v);
591 }
593 static int vmx_realmode(struct vcpu *v)
594 {
595 unsigned long rflags;
597 __vmread(GUEST_RFLAGS, &rflags);
598 return rflags & X86_EFLAGS_VM;
599 }
601 static int vmx_instruction_length(struct vcpu *v)
602 {
603 unsigned long inst_len;
605 if (__vmread(VM_EXIT_INSTRUCTION_LEN, &inst_len))
606 return 0;
607 return inst_len;
608 }
610 static unsigned long vmx_get_ctrl_reg(struct vcpu *v, unsigned int num)
611 {
612 switch ( num )
613 {
614 case 0:
615 return v->arch.hvm_vmx.cpu_cr0;
616 case 2:
617 return v->arch.hvm_vmx.cpu_cr2;
618 case 3:
619 return v->arch.hvm_vmx.cpu_cr3;
620 default:
621 BUG();
622 }
623 return 0; /* dummy */
624 }
626 /* SMP VMX guest support */
627 static void vmx_init_ap_context(struct vcpu_guest_context *ctxt,
628 int vcpuid, int trampoline_vector)
629 {
630 int i;
632 memset(ctxt, 0, sizeof(*ctxt));
634 /*
635 * Initial register values:
636 */
637 ctxt->user_regs.eip = VMXASSIST_BASE;
638 ctxt->user_regs.edx = vcpuid;
639 ctxt->user_regs.ebx = trampoline_vector;
641 ctxt->flags = VGCF_HVM_GUEST;
643 /* Virtual IDT is empty at start-of-day. */
644 for ( i = 0; i < 256; i++ )
645 {
646 ctxt->trap_ctxt[i].vector = i;
647 ctxt->trap_ctxt[i].cs = FLAT_KERNEL_CS;
648 }
650 /* No callback handlers. */
651 #if defined(__i386__)
652 ctxt->event_callback_cs = FLAT_KERNEL_CS;
653 ctxt->failsafe_callback_cs = FLAT_KERNEL_CS;
654 #endif
655 }
657 void do_nmi(struct cpu_user_regs *);
659 static int check_vmx_controls(u32 ctrls, u32 msr)
660 {
661 u32 vmx_msr_low, vmx_msr_high;
663 rdmsr(msr, vmx_msr_low, vmx_msr_high);
664 if ( (ctrls < vmx_msr_low) || (ctrls > vmx_msr_high) )
665 {
666 printk("Insufficient VMX capability 0x%x, "
667 "msr=0x%x,low=0x%8x,high=0x%x\n",
668 ctrls, msr, vmx_msr_low, vmx_msr_high);
669 return 0;
670 }
671 return 1;
672 }
674 /* Setup HVM interfaces */
675 static void vmx_setup_hvm_funcs(void)
676 {
677 if ( hvm_enabled )
678 return;
680 hvm_funcs.disable = stop_vmx;
682 hvm_funcs.initialize_guest_resources = vmx_initialize_guest_resources;
683 hvm_funcs.relinquish_guest_resources = vmx_relinquish_guest_resources;
685 hvm_funcs.store_cpu_guest_regs = vmx_store_cpu_guest_regs;
686 hvm_funcs.load_cpu_guest_regs = vmx_load_cpu_guest_regs;
688 hvm_funcs.realmode = vmx_realmode;
689 hvm_funcs.paging_enabled = vmx_paging_enabled;
690 hvm_funcs.instruction_length = vmx_instruction_length;
691 hvm_funcs.get_guest_ctrl_reg = vmx_get_ctrl_reg;
693 hvm_funcs.init_ap_context = vmx_init_ap_context;
694 }
696 static void vmx_init_hypercall_page(struct domain *d, void *hypercall_page)
697 {
698 char *p;
699 int i;
701 memset(hypercall_page, 0, PAGE_SIZE);
703 for ( i = 0; i < (PAGE_SIZE / 32); i++ )
704 {
705 p = (char *)(hypercall_page + (i * 32));
706 *(u8 *)(p + 0) = 0xb8; /* mov imm32, %eax */
707 *(u32 *)(p + 1) = i;
708 *(u8 *)(p + 5) = 0x0f; /* vmcall */
709 *(u8 *)(p + 6) = 0x01;
710 *(u8 *)(p + 7) = 0xc1;
711 *(u8 *)(p + 8) = 0xc3; /* ret */
712 }
714 /* Don't support HYPERVISOR_iret at the moment */
715 *(u16 *)(hypercall_page + (__HYPERVISOR_iret * 32)) = 0x0b0f; /* ud2 */
716 }
718 int start_vmx(void)
719 {
720 u32 eax, edx;
721 struct vmcs_struct *vmcs;
723 /*
724 * Xen does not fill x86_capability words except 0.
725 */
726 boot_cpu_data.x86_capability[4] = cpuid_ecx(1);
728 if (!(test_bit(X86_FEATURE_VMXE, &boot_cpu_data.x86_capability)))
729 return 0;
731 rdmsr(IA32_FEATURE_CONTROL_MSR, eax, edx);
733 if ( eax & IA32_FEATURE_CONTROL_MSR_LOCK )
734 {
735 if ( (eax & IA32_FEATURE_CONTROL_MSR_ENABLE_VMXON) == 0x0 )
736 {
737 printk("VMX disabled by Feature Control MSR.\n");
738 return 0;
739 }
740 }
741 else
742 {
743 wrmsr(IA32_FEATURE_CONTROL_MSR,
744 IA32_FEATURE_CONTROL_MSR_LOCK |
745 IA32_FEATURE_CONTROL_MSR_ENABLE_VMXON, 0);
746 }
748 if ( !check_vmx_controls(MONITOR_PIN_BASED_EXEC_CONTROLS,
749 MSR_IA32_VMX_PINBASED_CTLS_MSR) )
750 return 0;
751 if ( !check_vmx_controls(MONITOR_CPU_BASED_EXEC_CONTROLS,
752 MSR_IA32_VMX_PROCBASED_CTLS_MSR) )
753 return 0;
754 if ( !check_vmx_controls(MONITOR_VM_EXIT_CONTROLS,
755 MSR_IA32_VMX_EXIT_CTLS_MSR) )
756 return 0;
757 if ( !check_vmx_controls(MONITOR_VM_ENTRY_CONTROLS,
758 MSR_IA32_VMX_ENTRY_CTLS_MSR) )
759 return 0;
761 set_in_cr4(X86_CR4_VMXE);
763 vmx_init_vmcs_config();
765 if ( (vmcs = vmx_alloc_host_vmcs()) == NULL )
766 {
767 printk("Failed to allocate host VMCS\n");
768 return 0;
769 }
771 if ( __vmxon(virt_to_maddr(vmcs)) )
772 {
773 printk("VMXON failed\n");
774 vmx_free_host_vmcs(vmcs);
775 return 0;
776 }
778 printk("VMXON is done\n");
780 vmx_save_init_msrs();
782 vmx_setup_hvm_funcs();
784 hvm_funcs.init_hypercall_page = vmx_init_hypercall_page;
786 hvm_enabled = 1;
788 return 1;
789 }
791 /*
792 * Not all cases receive valid value in the VM-exit instruction length field.
793 */
794 #define __get_instruction_length(len) \
795 __vmread(VM_EXIT_INSTRUCTION_LEN, &(len)); \
796 if ((len) < 1 || (len) > 15) \
797 __hvm_bug(&regs);
799 static void inline __update_guest_eip(unsigned long inst_len)
800 {
801 unsigned long current_eip;
803 __vmread(GUEST_RIP, &current_eip);
804 __vmwrite(GUEST_RIP, current_eip + inst_len);
805 __vmwrite(GUEST_INTERRUPTIBILITY_INFO, 0);
806 }
809 static int vmx_do_page_fault(unsigned long va, struct cpu_user_regs *regs)
810 {
811 unsigned long gpa; /* FIXME: PAE */
812 int result;
814 #if 0 /* keep for debugging */
815 {
816 unsigned long eip;
818 __vmread(GUEST_RIP, &eip);
819 HVM_DBG_LOG(DBG_LEVEL_VMMU,
820 "vmx_do_page_fault = 0x%lx, eip = %lx, error_code = %lx",
821 va, eip, (unsigned long)regs->error_code);
822 }
823 #endif
825 if ( !vmx_paging_enabled(current) )
826 {
827 /* construct 1-to-1 direct mapping */
828 if ( shadow_direct_map_fault(va, regs) )
829 return 1;
831 handle_mmio(va, va);
832 TRACE_VMEXIT (2,2);
833 return 1;
834 }
835 gpa = gva_to_gpa(va);
837 /* Use 1:1 page table to identify MMIO address space */
838 if ( mmio_space(gpa) ){
839 struct vcpu *v = current;
840 /* No support for APIC */
841 if (!hvm_apic_support(v->domain) && gpa >= 0xFEC00000) {
842 u32 inst_len;
843 __vmread(VM_EXIT_INSTRUCTION_LEN, &(inst_len));
844 __update_guest_eip(inst_len);
845 return 1;
846 }
847 TRACE_VMEXIT (2,2);
848 /* in the case of MMIO, we are more interested in gpa than in va */
849 TRACE_VMEXIT (4,gpa);
850 handle_mmio(va, gpa);
851 return 1;
852 }
854 result = shadow_fault(va, regs);
855 TRACE_VMEXIT (2,result);
856 #if 0
857 if ( !result )
858 {
859 __vmread(GUEST_RIP, &eip);
860 printk("vmx pgfault to guest va=%lx eip=%lx\n", va, eip);
861 }
862 #endif
864 return result;
865 }
867 static void vmx_do_no_device_fault(void)
868 {
869 unsigned long cr0;
870 struct vcpu *v = current;
872 setup_fpu(current);
873 __vm_clear_bit(EXCEPTION_BITMAP, EXCEPTION_BITMAP_NM);
875 /* Disable TS in guest CR0 unless the guest wants the exception too. */
876 __vmread_vcpu(v, CR0_READ_SHADOW, &cr0);
877 if ( !(cr0 & X86_CR0_TS) )
878 {
879 __vmread_vcpu(v, GUEST_CR0, &cr0);
880 cr0 &= ~X86_CR0_TS;
881 __vmwrite(GUEST_CR0, cr0);
882 }
883 }
885 #define bitmaskof(idx) (1U << ((idx)&31))
886 static void vmx_vmexit_do_cpuid(struct cpu_user_regs *regs)
887 {
888 unsigned int input = (unsigned int)regs->eax;
889 unsigned int count = (unsigned int)regs->ecx;
890 unsigned int eax, ebx, ecx, edx;
891 unsigned long eip;
892 struct vcpu *v = current;
894 __vmread(GUEST_RIP, &eip);
896 HVM_DBG_LOG(DBG_LEVEL_3, "(eax) 0x%08lx, (ebx) 0x%08lx, "
897 "(ecx) 0x%08lx, (edx) 0x%08lx, (esi) 0x%08lx, (edi) 0x%08lx",
898 (unsigned long)regs->eax, (unsigned long)regs->ebx,
899 (unsigned long)regs->ecx, (unsigned long)regs->edx,
900 (unsigned long)regs->esi, (unsigned long)regs->edi);
902 if ( input == CPUID_LEAF_0x4 )
903 {
904 cpuid_count(input, count, &eax, &ebx, &ecx, &edx);
905 eax &= NUM_CORES_RESET_MASK;
906 }
907 else if ( !cpuid_hypervisor_leaves(input, &eax, &ebx, &ecx, &edx) )
908 {
909 cpuid(input, &eax, &ebx, &ecx, &edx);
911 if ( input == CPUID_LEAF_0x1 )
912 {
913 /* mask off reserved bits */
914 ecx &= ~VMX_VCPU_CPUID_L1_ECX_RESERVED;
916 if ( !hvm_apic_support(v->domain) ||
917 !vlapic_global_enabled((VLAPIC(v))) )
918 {
919 /* Since the apic is disabled, avoid any
920 confusion about SMP cpus being available */
922 clear_bit(X86_FEATURE_APIC, &edx);
923 }
925 #if CONFIG_PAGING_LEVELS < 3
926 edx &= ~(bitmaskof(X86_FEATURE_PAE) |
927 bitmaskof(X86_FEATURE_PSE) |
928 bitmaskof(X86_FEATURE_PSE36));
929 #else
930 if ( v->domain->arch.ops->guest_paging_levels == PAGING_L2 )
931 {
932 if ( v->domain->arch.hvm_domain.pae_enabled )
933 clear_bit(X86_FEATURE_PSE36, &edx);
934 else
935 {
936 clear_bit(X86_FEATURE_PAE, &edx);
937 clear_bit(X86_FEATURE_PSE, &edx);
938 clear_bit(X86_FEATURE_PSE36, &edx);
939 }
940 }
941 #endif
943 ebx &= NUM_THREADS_RESET_MASK;
945 /* Unsupportable for virtualised CPUs. */
946 ecx &= ~(bitmaskof(X86_FEATURE_VMXE) |
947 bitmaskof(X86_FEATURE_EST) |
948 bitmaskof(X86_FEATURE_TM2) |
949 bitmaskof(X86_FEATURE_CID) |
950 bitmaskof(X86_FEATURE_MWAIT) );
952 edx &= ~( bitmaskof(X86_FEATURE_HT) |
953 bitmaskof(X86_FEATURE_MCA) |
954 bitmaskof(X86_FEATURE_MCE) |
955 bitmaskof(X86_FEATURE_ACPI) |
956 bitmaskof(X86_FEATURE_ACC) );
957 }
958 else if ( ( input == CPUID_LEAF_0x6 )
959 || ( input == CPUID_LEAF_0x9 )
960 || ( input == CPUID_LEAF_0xA ))
961 {
962 eax = ebx = ecx = edx = 0x0;
963 }
964 #ifdef __i386__
965 else if ( input == CPUID_LEAF_0x80000001 )
966 {
967 clear_bit(X86_FEATURE_LAHF_LM & 31, &ecx);
969 clear_bit(X86_FEATURE_LM & 31, &edx);
970 clear_bit(X86_FEATURE_SYSCALL & 31, &edx);
971 }
972 #endif
973 }
975 regs->eax = (unsigned long) eax;
976 regs->ebx = (unsigned long) ebx;
977 regs->ecx = (unsigned long) ecx;
978 regs->edx = (unsigned long) edx;
980 HVM_DBG_LOG(DBG_LEVEL_3, "eip@%lx, input: 0x%lx, "
981 "output: eax = 0x%08lx, ebx = 0x%08lx, "
982 "ecx = 0x%08lx, edx = 0x%08lx",
983 (unsigned long)eip, (unsigned long)input,
984 (unsigned long)eax, (unsigned long)ebx,
985 (unsigned long)ecx, (unsigned long)edx);
986 }
988 #define CASE_GET_REG_P(REG, reg) \
989 case REG_ ## REG: reg_p = (unsigned long *)&(regs->reg); break
991 #ifdef __i386__
992 #define CASE_EXTEND_GET_REG_P
993 #else
994 #define CASE_EXTEND_GET_REG_P \
995 CASE_GET_REG_P(R8, r8); \
996 CASE_GET_REG_P(R9, r9); \
997 CASE_GET_REG_P(R10, r10); \
998 CASE_GET_REG_P(R11, r11); \
999 CASE_GET_REG_P(R12, r12); \
1000 CASE_GET_REG_P(R13, r13); \
1001 CASE_GET_REG_P(R14, r14); \
1002 CASE_GET_REG_P(R15, r15)
1003 #endif
1005 static void vmx_dr_access(unsigned long exit_qualification,
1006 struct cpu_user_regs *regs)
1008 struct vcpu *v = current;
1010 v->arch.hvm_vcpu.flag_dr_dirty = 1;
1012 /* We could probably be smarter about this */
1013 __restore_debug_registers(v);
1015 /* Allow guest direct access to DR registers */
1016 v->arch.hvm_vcpu.u.vmx.exec_control &= ~CPU_BASED_MOV_DR_EXITING;
1017 __vmwrite(CPU_BASED_VM_EXEC_CONTROL,
1018 v->arch.hvm_vcpu.u.vmx.exec_control);
1021 /*
1022 * Invalidate the TLB for va. Invalidate the shadow page corresponding
1023 * the address va.
1024 */
1025 static void vmx_vmexit_do_invlpg(unsigned long va)
1027 unsigned long eip;
1028 struct vcpu *v = current;
1030 __vmread(GUEST_RIP, &eip);
1032 HVM_DBG_LOG(DBG_LEVEL_VMMU, "vmx_vmexit_do_invlpg: eip=%lx, va=%lx",
1033 eip, va);
1035 /*
1036 * We do the safest things first, then try to update the shadow
1037 * copying from guest
1038 */
1039 shadow_invlpg(v, va);
1042 static int check_for_null_selector(unsigned long eip)
1044 unsigned char inst[MAX_INST_LEN];
1045 unsigned long sel;
1046 int i, inst_len;
1047 int inst_copy_from_guest(unsigned char *, unsigned long, int);
1049 __vmread(VM_EXIT_INSTRUCTION_LEN, &inst_len);
1050 memset(inst, 0, MAX_INST_LEN);
1051 if (inst_copy_from_guest(inst, eip, inst_len) != inst_len) {
1052 printf("check_for_null_selector: get guest instruction failed\n");
1053 domain_crash_synchronous();
1056 for (i = 0; i < inst_len; i++) {
1057 switch (inst[i]) {
1058 case 0xf3: /* REPZ */
1059 case 0xf2: /* REPNZ */
1060 case 0xf0: /* LOCK */
1061 case 0x66: /* data32 */
1062 case 0x67: /* addr32 */
1063 continue;
1064 case 0x2e: /* CS */
1065 __vmread(GUEST_CS_SELECTOR, &sel);
1066 break;
1067 case 0x36: /* SS */
1068 __vmread(GUEST_SS_SELECTOR, &sel);
1069 break;
1070 case 0x26: /* ES */
1071 __vmread(GUEST_ES_SELECTOR, &sel);
1072 break;
1073 case 0x64: /* FS */
1074 __vmread(GUEST_FS_SELECTOR, &sel);
1075 break;
1076 case 0x65: /* GS */
1077 __vmread(GUEST_GS_SELECTOR, &sel);
1078 break;
1079 case 0x3e: /* DS */
1080 /* FALLTHROUGH */
1081 default:
1082 /* DS is the default */
1083 __vmread(GUEST_DS_SELECTOR, &sel);
1085 return sel == 0 ? 1 : 0;
1088 return 0;
1091 extern void send_pio_req(struct cpu_user_regs *regs, unsigned long port,
1092 unsigned long count, int size, long value,
1093 int dir, int pvalid);
1095 static void vmx_io_instruction(unsigned long exit_qualification,
1096 unsigned long inst_len)
1098 struct cpu_user_regs *regs;
1099 struct hvm_io_op *pio_opp;
1100 unsigned long eip, cs, eflags;
1101 unsigned long port, size, dir;
1102 int vm86;
1104 pio_opp = &current->arch.hvm_vcpu.io_op;
1105 pio_opp->instr = INSTR_PIO;
1106 pio_opp->flags = 0;
1108 regs = &pio_opp->io_context;
1110 /* Copy current guest state into io instruction state structure. */
1111 memcpy(regs, guest_cpu_user_regs(), HVM_CONTEXT_STACK_BYTES);
1112 hvm_store_cpu_guest_regs(current, regs, NULL);
1114 __vmread(GUEST_RIP, &eip);
1115 __vmread(GUEST_CS_SELECTOR, &cs);
1116 __vmread(GUEST_RFLAGS, &eflags);
1117 vm86 = eflags & X86_EFLAGS_VM ? 1 : 0;
1119 HVM_DBG_LOG(DBG_LEVEL_IO,
1120 "vmx_io_instruction: vm86 %d, eip=%lx:%lx, "
1121 "exit_qualification = %lx",
1122 vm86, cs, eip, exit_qualification);
1124 if (test_bit(6, &exit_qualification))
1125 port = (exit_qualification >> 16) & 0xFFFF;
1126 else
1127 port = regs->edx & 0xffff;
1128 TRACE_VMEXIT(1, port);
1129 size = (exit_qualification & 7) + 1;
1130 dir = test_bit(3, &exit_qualification); /* direction */
1132 if (test_bit(4, &exit_qualification)) { /* string instruction */
1133 unsigned long addr, count = 1;
1134 int sign = regs->eflags & EF_DF ? -1 : 1;
1136 __vmread(GUEST_LINEAR_ADDRESS, &addr);
1138 /*
1139 * In protected mode, guest linear address is invalid if the
1140 * selector is null.
1141 */
1142 if (!vm86 && check_for_null_selector(eip))
1143 addr = dir == IOREQ_WRITE ? regs->esi : regs->edi;
1145 if (test_bit(5, &exit_qualification)) { /* "rep" prefix */
1146 pio_opp->flags |= REPZ;
1147 count = vm86 ? regs->ecx & 0xFFFF : regs->ecx;
1150 /*
1151 * Handle string pio instructions that cross pages or that
1152 * are unaligned. See the comments in hvm_domain.c/handle_mmio()
1153 */
1154 if ((addr & PAGE_MASK) != ((addr + size - 1) & PAGE_MASK)) {
1155 unsigned long value = 0;
1157 pio_opp->flags |= OVERLAP;
1158 if (dir == IOREQ_WRITE)
1159 hvm_copy(&value, addr, size, HVM_COPY_IN);
1160 send_pio_req(regs, port, 1, size, value, dir, 0);
1161 } else {
1162 if ((addr & PAGE_MASK) != ((addr + count * size - 1) & PAGE_MASK)) {
1163 if (sign > 0)
1164 count = (PAGE_SIZE - (addr & ~PAGE_MASK)) / size;
1165 else
1166 count = (addr & ~PAGE_MASK) / size;
1167 } else
1168 __update_guest_eip(inst_len);
1170 send_pio_req(regs, port, count, size, addr, dir, 1);
1172 } else {
1173 if (port == 0xe9 && dir == IOREQ_WRITE && size == 1)
1174 hvm_print_line(current, regs->eax); /* guest debug output */
1176 __update_guest_eip(inst_len);
1177 send_pio_req(regs, port, 1, size, regs->eax, dir, 0);
1181 int
1182 vmx_world_save(struct vcpu *v, struct vmx_assist_context *c)
1184 unsigned long inst_len;
1185 int error = 0;
1187 error |= __vmread(VM_EXIT_INSTRUCTION_LEN, &inst_len);
1188 error |= __vmread(GUEST_RIP, &c->eip);
1189 c->eip += inst_len; /* skip transition instruction */
1190 error |= __vmread(GUEST_RSP, &c->esp);
1191 error |= __vmread(GUEST_RFLAGS, &c->eflags);
1193 error |= __vmread(CR0_READ_SHADOW, &c->cr0);
1194 c->cr3 = v->arch.hvm_vmx.cpu_cr3;
1195 error |= __vmread(CR4_READ_SHADOW, &c->cr4);
1197 error |= __vmread(GUEST_IDTR_LIMIT, &c->idtr_limit);
1198 error |= __vmread(GUEST_IDTR_BASE, &c->idtr_base);
1200 error |= __vmread(GUEST_GDTR_LIMIT, &c->gdtr_limit);
1201 error |= __vmread(GUEST_GDTR_BASE, &c->gdtr_base);
1203 error |= __vmread(GUEST_CS_SELECTOR, &c->cs_sel);
1204 error |= __vmread(GUEST_CS_LIMIT, &c->cs_limit);
1205 error |= __vmread(GUEST_CS_BASE, &c->cs_base);
1206 error |= __vmread(GUEST_CS_AR_BYTES, &c->cs_arbytes.bytes);
1208 error |= __vmread(GUEST_DS_SELECTOR, &c->ds_sel);
1209 error |= __vmread(GUEST_DS_LIMIT, &c->ds_limit);
1210 error |= __vmread(GUEST_DS_BASE, &c->ds_base);
1211 error |= __vmread(GUEST_DS_AR_BYTES, &c->ds_arbytes.bytes);
1213 error |= __vmread(GUEST_ES_SELECTOR, &c->es_sel);
1214 error |= __vmread(GUEST_ES_LIMIT, &c->es_limit);
1215 error |= __vmread(GUEST_ES_BASE, &c->es_base);
1216 error |= __vmread(GUEST_ES_AR_BYTES, &c->es_arbytes.bytes);
1218 error |= __vmread(GUEST_SS_SELECTOR, &c->ss_sel);
1219 error |= __vmread(GUEST_SS_LIMIT, &c->ss_limit);
1220 error |= __vmread(GUEST_SS_BASE, &c->ss_base);
1221 error |= __vmread(GUEST_SS_AR_BYTES, &c->ss_arbytes.bytes);
1223 error |= __vmread(GUEST_FS_SELECTOR, &c->fs_sel);
1224 error |= __vmread(GUEST_FS_LIMIT, &c->fs_limit);
1225 error |= __vmread(GUEST_FS_BASE, &c->fs_base);
1226 error |= __vmread(GUEST_FS_AR_BYTES, &c->fs_arbytes.bytes);
1228 error |= __vmread(GUEST_GS_SELECTOR, &c->gs_sel);
1229 error |= __vmread(GUEST_GS_LIMIT, &c->gs_limit);
1230 error |= __vmread(GUEST_GS_BASE, &c->gs_base);
1231 error |= __vmread(GUEST_GS_AR_BYTES, &c->gs_arbytes.bytes);
1233 error |= __vmread(GUEST_TR_SELECTOR, &c->tr_sel);
1234 error |= __vmread(GUEST_TR_LIMIT, &c->tr_limit);
1235 error |= __vmread(GUEST_TR_BASE, &c->tr_base);
1236 error |= __vmread(GUEST_TR_AR_BYTES, &c->tr_arbytes.bytes);
1238 error |= __vmread(GUEST_LDTR_SELECTOR, &c->ldtr_sel);
1239 error |= __vmread(GUEST_LDTR_LIMIT, &c->ldtr_limit);
1240 error |= __vmread(GUEST_LDTR_BASE, &c->ldtr_base);
1241 error |= __vmread(GUEST_LDTR_AR_BYTES, &c->ldtr_arbytes.bytes);
1243 return !error;
1246 int
1247 vmx_world_restore(struct vcpu *v, struct vmx_assist_context *c)
1249 unsigned long mfn, old_cr4, old_base_mfn;
1250 int error = 0;
1252 error |= __vmwrite(GUEST_RIP, c->eip);
1253 error |= __vmwrite(GUEST_RSP, c->esp);
1254 error |= __vmwrite(GUEST_RFLAGS, c->eflags);
1256 error |= __vmwrite(CR0_READ_SHADOW, c->cr0);
1258 if (!vmx_paging_enabled(v)) {
1259 HVM_DBG_LOG(DBG_LEVEL_VMMU, "switching to vmxassist. use phys table");
1260 __vmwrite(GUEST_CR3, pagetable_get_paddr(v->domain->arch.phys_table));
1261 goto skip_cr3;
1264 if (c->cr3 == v->arch.hvm_vmx.cpu_cr3) {
1265 /*
1266 * This is simple TLB flush, implying the guest has
1267 * removed some translation or changed page attributes.
1268 * We simply invalidate the shadow.
1269 */
1270 mfn = get_mfn_from_gpfn(c->cr3 >> PAGE_SHIFT);
1271 if (mfn != pagetable_get_pfn(v->arch.guest_table)) {
1272 printk("Invalid CR3 value=%x", c->cr3);
1273 domain_crash_synchronous();
1274 return 0;
1276 shadow_sync_all(v->domain);
1277 } else {
1278 /*
1279 * If different, make a shadow. Check if the PDBR is valid
1280 * first.
1281 */
1282 HVM_DBG_LOG(DBG_LEVEL_VMMU, "CR3 c->cr3 = %x", c->cr3);
1283 if ((c->cr3 >> PAGE_SHIFT) > v->domain->max_pages) {
1284 printk("Invalid CR3 value=%x", c->cr3);
1285 domain_crash_synchronous();
1286 return 0;
1288 mfn = get_mfn_from_gpfn(c->cr3 >> PAGE_SHIFT);
1289 if(!get_page(mfn_to_page(mfn), v->domain))
1290 return 0;
1291 old_base_mfn = pagetable_get_pfn(v->arch.guest_table);
1292 v->arch.guest_table = pagetable_from_pfn(mfn);
1293 if (old_base_mfn)
1294 put_page(mfn_to_page(old_base_mfn));
1295 /*
1296 * arch.shadow_table should now hold the next CR3 for shadow
1297 */
1298 v->arch.hvm_vmx.cpu_cr3 = c->cr3;
1299 update_pagetables(v);
1300 HVM_DBG_LOG(DBG_LEVEL_VMMU, "Update CR3 value = %x", c->cr3);
1301 __vmwrite(GUEST_CR3, pagetable_get_paddr(v->arch.shadow_table));
1304 skip_cr3:
1306 error |= __vmread(CR4_READ_SHADOW, &old_cr4);
1307 error |= __vmwrite(GUEST_CR4, (c->cr4 | VMX_CR4_HOST_MASK));
1308 error |= __vmwrite(CR4_READ_SHADOW, c->cr4);
1310 error |= __vmwrite(GUEST_IDTR_LIMIT, c->idtr_limit);
1311 error |= __vmwrite(GUEST_IDTR_BASE, c->idtr_base);
1313 error |= __vmwrite(GUEST_GDTR_LIMIT, c->gdtr_limit);
1314 error |= __vmwrite(GUEST_GDTR_BASE, c->gdtr_base);
1316 error |= __vmwrite(GUEST_CS_SELECTOR, c->cs_sel);
1317 error |= __vmwrite(GUEST_CS_LIMIT, c->cs_limit);
1318 error |= __vmwrite(GUEST_CS_BASE, c->cs_base);
1319 error |= __vmwrite(GUEST_CS_AR_BYTES, c->cs_arbytes.bytes);
1321 error |= __vmwrite(GUEST_DS_SELECTOR, c->ds_sel);
1322 error |= __vmwrite(GUEST_DS_LIMIT, c->ds_limit);
1323 error |= __vmwrite(GUEST_DS_BASE, c->ds_base);
1324 error |= __vmwrite(GUEST_DS_AR_BYTES, c->ds_arbytes.bytes);
1326 error |= __vmwrite(GUEST_ES_SELECTOR, c->es_sel);
1327 error |= __vmwrite(GUEST_ES_LIMIT, c->es_limit);
1328 error |= __vmwrite(GUEST_ES_BASE, c->es_base);
1329 error |= __vmwrite(GUEST_ES_AR_BYTES, c->es_arbytes.bytes);
1331 error |= __vmwrite(GUEST_SS_SELECTOR, c->ss_sel);
1332 error |= __vmwrite(GUEST_SS_LIMIT, c->ss_limit);
1333 error |= __vmwrite(GUEST_SS_BASE, c->ss_base);
1334 error |= __vmwrite(GUEST_SS_AR_BYTES, c->ss_arbytes.bytes);
1336 error |= __vmwrite(GUEST_FS_SELECTOR, c->fs_sel);
1337 error |= __vmwrite(GUEST_FS_LIMIT, c->fs_limit);
1338 error |= __vmwrite(GUEST_FS_BASE, c->fs_base);
1339 error |= __vmwrite(GUEST_FS_AR_BYTES, c->fs_arbytes.bytes);
1341 error |= __vmwrite(GUEST_GS_SELECTOR, c->gs_sel);
1342 error |= __vmwrite(GUEST_GS_LIMIT, c->gs_limit);
1343 error |= __vmwrite(GUEST_GS_BASE, c->gs_base);
1344 error |= __vmwrite(GUEST_GS_AR_BYTES, c->gs_arbytes.bytes);
1346 error |= __vmwrite(GUEST_TR_SELECTOR, c->tr_sel);
1347 error |= __vmwrite(GUEST_TR_LIMIT, c->tr_limit);
1348 error |= __vmwrite(GUEST_TR_BASE, c->tr_base);
1349 error |= __vmwrite(GUEST_TR_AR_BYTES, c->tr_arbytes.bytes);
1351 error |= __vmwrite(GUEST_LDTR_SELECTOR, c->ldtr_sel);
1352 error |= __vmwrite(GUEST_LDTR_LIMIT, c->ldtr_limit);
1353 error |= __vmwrite(GUEST_LDTR_BASE, c->ldtr_base);
1354 error |= __vmwrite(GUEST_LDTR_AR_BYTES, c->ldtr_arbytes.bytes);
1356 return !error;
1359 enum { VMX_ASSIST_INVOKE = 0, VMX_ASSIST_RESTORE };
1361 int
1362 vmx_assist(struct vcpu *v, int mode)
1364 struct vmx_assist_context c;
1365 u32 magic;
1366 u32 cp;
1368 /* make sure vmxassist exists (this is not an error) */
1369 if (!hvm_copy(&magic, VMXASSIST_MAGIC_OFFSET, sizeof(magic), HVM_COPY_IN))
1370 return 0;
1371 if (magic != VMXASSIST_MAGIC)
1372 return 0;
1374 switch (mode) {
1375 /*
1376 * Transfer control to vmxassist.
1377 * Store the current context in VMXASSIST_OLD_CONTEXT and load
1378 * the new VMXASSIST_NEW_CONTEXT context. This context was created
1379 * by vmxassist and will transfer control to it.
1380 */
1381 case VMX_ASSIST_INVOKE:
1382 /* save the old context */
1383 if (!hvm_copy(&cp, VMXASSIST_OLD_CONTEXT, sizeof(cp), HVM_COPY_IN))
1384 goto error;
1385 if (cp != 0) {
1386 if (!vmx_world_save(v, &c))
1387 goto error;
1388 if (!hvm_copy(&c, cp, sizeof(c), HVM_COPY_OUT))
1389 goto error;
1392 /* restore the new context, this should activate vmxassist */
1393 if (!hvm_copy(&cp, VMXASSIST_NEW_CONTEXT, sizeof(cp), HVM_COPY_IN))
1394 goto error;
1395 if (cp != 0) {
1396 if (!hvm_copy(&c, cp, sizeof(c), HVM_COPY_IN))
1397 goto error;
1398 if (!vmx_world_restore(v, &c))
1399 goto error;
1400 return 1;
1402 break;
1404 /*
1405 * Restore the VMXASSIST_OLD_CONTEXT that was saved by VMX_ASSIST_INVOKE
1406 * above.
1407 */
1408 case VMX_ASSIST_RESTORE:
1409 /* save the old context */
1410 if (!hvm_copy(&cp, VMXASSIST_OLD_CONTEXT, sizeof(cp), HVM_COPY_IN))
1411 goto error;
1412 if (cp != 0) {
1413 if (!hvm_copy(&c, cp, sizeof(c), HVM_COPY_IN))
1414 goto error;
1415 if (!vmx_world_restore(v, &c))
1416 goto error;
1417 return 1;
1419 break;
1422 error:
1423 printf("Failed to transfer to vmxassist\n");
1424 domain_crash_synchronous();
1425 return 0;
1428 static int vmx_set_cr0(unsigned long value)
1430 struct vcpu *v = current;
1431 unsigned long mfn;
1432 unsigned long eip;
1433 int paging_enabled;
1434 unsigned long vm_entry_value;
1435 unsigned long old_cr0;
1437 /*
1438 * CR0: We don't want to lose PE and PG.
1439 */
1440 __vmread_vcpu(v, CR0_READ_SHADOW, &old_cr0);
1441 paging_enabled = (old_cr0 & X86_CR0_PE) && (old_cr0 & X86_CR0_PG);
1443 /* TS cleared? Then initialise FPU now. */
1444 if ( !(value & X86_CR0_TS) )
1446 setup_fpu(v);
1447 __vm_clear_bit(EXCEPTION_BITMAP, EXCEPTION_BITMAP_NM);
1450 __vmwrite(GUEST_CR0, value | X86_CR0_PE | X86_CR0_PG | X86_CR0_NE);
1451 __vmwrite(CR0_READ_SHADOW, value);
1453 HVM_DBG_LOG(DBG_LEVEL_VMMU, "Update CR0 value = %lx\n", value);
1455 if ( (value & X86_CR0_PE) && (value & X86_CR0_PG) && !paging_enabled )
1457 /*
1458 * Trying to enable guest paging.
1459 * The guest CR3 must be pointing to the guest physical.
1460 */
1461 if ( !VALID_MFN(mfn = get_mfn_from_gpfn(
1462 v->arch.hvm_vmx.cpu_cr3 >> PAGE_SHIFT)) ||
1463 !get_page(mfn_to_page(mfn), v->domain) )
1465 printk("Invalid CR3 value = %lx", v->arch.hvm_vmx.cpu_cr3);
1466 domain_crash_synchronous(); /* need to take a clean path */
1469 #if defined(__x86_64__)
1470 if ( test_bit(VMX_CPU_STATE_LME_ENABLED,
1471 &v->arch.hvm_vmx.cpu_state) &&
1472 !test_bit(VMX_CPU_STATE_PAE_ENABLED,
1473 &v->arch.hvm_vmx.cpu_state) )
1475 HVM_DBG_LOG(DBG_LEVEL_1, "Enable paging before PAE enabled\n");
1476 vmx_inject_hw_exception(v, TRAP_gp_fault, 0);
1479 if ( test_bit(VMX_CPU_STATE_LME_ENABLED,
1480 &v->arch.hvm_vmx.cpu_state) )
1482 /* Here the PAE is should be opened */
1483 HVM_DBG_LOG(DBG_LEVEL_1, "Enable long mode\n");
1484 set_bit(VMX_CPU_STATE_LMA_ENABLED,
1485 &v->arch.hvm_vmx.cpu_state);
1487 __vmread(VM_ENTRY_CONTROLS, &vm_entry_value);
1488 vm_entry_value |= VM_ENTRY_CONTROLS_IA32E_MODE;
1489 __vmwrite(VM_ENTRY_CONTROLS, vm_entry_value);
1491 if ( !shadow_set_guest_paging_levels(v->domain, PAGING_L4) )
1493 printk("Unsupported guest paging levels\n");
1494 domain_crash_synchronous(); /* need to take a clean path */
1497 else
1498 #endif /* __x86_64__ */
1500 #if CONFIG_PAGING_LEVELS >= 3
1501 /* seems it's a 32-bit or 32-bit PAE guest */
1503 if ( test_bit(VMX_CPU_STATE_PAE_ENABLED,
1504 &v->arch.hvm_vmx.cpu_state) )
1506 /* The guest enables PAE first and then it enables PG, it is
1507 * really a PAE guest */
1508 if ( !shadow_set_guest_paging_levels(v->domain, PAGING_L3) )
1510 printk("Unsupported guest paging levels\n");
1511 domain_crash_synchronous();
1514 else
1516 if ( !shadow_set_guest_paging_levels(v->domain, PAGING_L2) )
1518 printk("Unsupported guest paging levels\n");
1519 domain_crash_synchronous(); /* need to take a clean path */
1522 #endif
1525 /*
1526 * Now arch.guest_table points to machine physical.
1527 */
1528 v->arch.guest_table = pagetable_from_pfn(mfn);
1529 update_pagetables(v);
1531 HVM_DBG_LOG(DBG_LEVEL_VMMU, "New arch.guest_table = %lx",
1532 (unsigned long) (mfn << PAGE_SHIFT));
1534 __vmwrite(GUEST_CR3, pagetable_get_paddr(v->arch.shadow_table));
1535 /*
1536 * arch->shadow_table should hold the next CR3 for shadow
1537 */
1538 HVM_DBG_LOG(DBG_LEVEL_VMMU, "Update CR3 value = %lx, mfn = %lx",
1539 v->arch.hvm_vmx.cpu_cr3, mfn);
1542 if ( !((value & X86_CR0_PE) && (value & X86_CR0_PG)) && paging_enabled )
1543 if ( v->arch.hvm_vmx.cpu_cr3 ) {
1544 put_page(mfn_to_page(get_mfn_from_gpfn(
1545 v->arch.hvm_vmx.cpu_cr3 >> PAGE_SHIFT)));
1546 v->arch.guest_table = pagetable_null();
1549 /*
1550 * VMX does not implement real-mode virtualization. We emulate
1551 * real-mode by performing a world switch to VMXAssist whenever
1552 * a partition disables the CR0.PE bit.
1553 */
1554 if ( (value & X86_CR0_PE) == 0 )
1556 if ( value & X86_CR0_PG ) {
1557 /* inject GP here */
1558 vmx_inject_hw_exception(v, TRAP_gp_fault, 0);
1559 return 0;
1560 } else {
1561 /*
1562 * Disable paging here.
1563 * Same to PE == 1 && PG == 0
1564 */
1565 if ( test_bit(VMX_CPU_STATE_LMA_ENABLED,
1566 &v->arch.hvm_vmx.cpu_state) )
1568 clear_bit(VMX_CPU_STATE_LMA_ENABLED,
1569 &v->arch.hvm_vmx.cpu_state);
1570 __vmread(VM_ENTRY_CONTROLS, &vm_entry_value);
1571 vm_entry_value &= ~VM_ENTRY_CONTROLS_IA32E_MODE;
1572 __vmwrite(VM_ENTRY_CONTROLS, vm_entry_value);
1576 clear_all_shadow_status(v->domain);
1577 if ( vmx_assist(v, VMX_ASSIST_INVOKE) ) {
1578 set_bit(VMX_CPU_STATE_ASSIST_ENABLED, &v->arch.hvm_vmx.cpu_state);
1579 __vmread(GUEST_RIP, &eip);
1580 HVM_DBG_LOG(DBG_LEVEL_1,
1581 "Transfering control to vmxassist %%eip 0x%lx\n", eip);
1582 return 0; /* do not update eip! */
1584 } else if ( test_bit(VMX_CPU_STATE_ASSIST_ENABLED,
1585 &v->arch.hvm_vmx.cpu_state) )
1587 __vmread(GUEST_RIP, &eip);
1588 HVM_DBG_LOG(DBG_LEVEL_1,
1589 "Enabling CR0.PE at %%eip 0x%lx\n", eip);
1590 if ( vmx_assist(v, VMX_ASSIST_RESTORE) )
1592 clear_bit(VMX_CPU_STATE_ASSIST_ENABLED,
1593 &v->arch.hvm_vmx.cpu_state);
1594 __vmread(GUEST_RIP, &eip);
1595 HVM_DBG_LOG(DBG_LEVEL_1,
1596 "Restoring to %%eip 0x%lx\n", eip);
1597 return 0; /* do not update eip! */
1600 else if ( (value & (X86_CR0_PE | X86_CR0_PG)) == X86_CR0_PE )
1602 /* we should take care of this kind of situation */
1603 clear_all_shadow_status(v->domain);
1604 __vmwrite(GUEST_CR3, pagetable_get_paddr(v->domain->arch.phys_table));
1607 return 1;
1610 #define CASE_SET_REG(REG, reg) \
1611 case REG_ ## REG: regs->reg = value; break
1612 #define CASE_GET_REG(REG, reg) \
1613 case REG_ ## REG: value = regs->reg; break
1615 #define CASE_EXTEND_SET_REG \
1616 CASE_EXTEND_REG(S)
1617 #define CASE_EXTEND_GET_REG \
1618 CASE_EXTEND_REG(G)
1620 #ifdef __i386__
1621 #define CASE_EXTEND_REG(T)
1622 #else
1623 #define CASE_EXTEND_REG(T) \
1624 CASE_ ## T ## ET_REG(R8, r8); \
1625 CASE_ ## T ## ET_REG(R9, r9); \
1626 CASE_ ## T ## ET_REG(R10, r10); \
1627 CASE_ ## T ## ET_REG(R11, r11); \
1628 CASE_ ## T ## ET_REG(R12, r12); \
1629 CASE_ ## T ## ET_REG(R13, r13); \
1630 CASE_ ## T ## ET_REG(R14, r14); \
1631 CASE_ ## T ## ET_REG(R15, r15)
1632 #endif
1634 /*
1635 * Write to control registers
1636 */
1637 static int mov_to_cr(int gp, int cr, struct cpu_user_regs *regs)
1639 unsigned long value;
1640 unsigned long old_cr;
1641 struct vcpu *v = current;
1643 switch ( gp ) {
1644 CASE_GET_REG(EAX, eax);
1645 CASE_GET_REG(ECX, ecx);
1646 CASE_GET_REG(EDX, edx);
1647 CASE_GET_REG(EBX, ebx);
1648 CASE_GET_REG(EBP, ebp);
1649 CASE_GET_REG(ESI, esi);
1650 CASE_GET_REG(EDI, edi);
1651 CASE_EXTEND_GET_REG;
1652 case REG_ESP:
1653 __vmread(GUEST_RSP, &value);
1654 break;
1655 default:
1656 printk("invalid gp: %d\n", gp);
1657 __hvm_bug(regs);
1660 HVM_DBG_LOG(DBG_LEVEL_1, "CR%d, value = %lx", cr, value);
1662 switch ( cr ) {
1663 case 0:
1664 return vmx_set_cr0(value);
1665 case 3:
1667 unsigned long old_base_mfn, mfn;
1669 /*
1670 * If paging is not enabled yet, simply copy the value to CR3.
1671 */
1672 if (!vmx_paging_enabled(v)) {
1673 v->arch.hvm_vmx.cpu_cr3 = value;
1674 break;
1677 /*
1678 * We make a new one if the shadow does not exist.
1679 */
1680 if (value == v->arch.hvm_vmx.cpu_cr3) {
1681 /*
1682 * This is simple TLB flush, implying the guest has
1683 * removed some translation or changed page attributes.
1684 * We simply invalidate the shadow.
1685 */
1686 mfn = get_mfn_from_gpfn(value >> PAGE_SHIFT);
1687 if (mfn != pagetable_get_pfn(v->arch.guest_table))
1688 __hvm_bug(regs);
1689 shadow_sync_all(v->domain);
1690 } else {
1691 /*
1692 * If different, make a shadow. Check if the PDBR is valid
1693 * first.
1694 */
1695 HVM_DBG_LOG(DBG_LEVEL_VMMU, "CR3 value = %lx", value);
1696 if ( ((value >> PAGE_SHIFT) > v->domain->max_pages ) ||
1697 !VALID_MFN(mfn = get_mfn_from_gpfn(value >> PAGE_SHIFT)) ||
1698 !get_page(mfn_to_page(mfn), v->domain) )
1700 printk("Invalid CR3 value=%lx", value);
1701 domain_crash_synchronous(); /* need to take a clean path */
1703 old_base_mfn = pagetable_get_pfn(v->arch.guest_table);
1704 v->arch.guest_table = pagetable_from_pfn(mfn);
1705 if (old_base_mfn)
1706 put_page(mfn_to_page(old_base_mfn));
1707 /*
1708 * arch.shadow_table should now hold the next CR3 for shadow
1709 */
1710 #if CONFIG_PAGING_LEVELS >= 3
1711 if ( v->domain->arch.ops->guest_paging_levels == PAGING_L3 )
1712 shadow_sync_all(v->domain);
1713 #endif
1715 v->arch.hvm_vmx.cpu_cr3 = value;
1716 update_pagetables(v);
1717 HVM_DBG_LOG(DBG_LEVEL_VMMU, "Update CR3 value = %lx",
1718 value);
1719 __vmwrite(GUEST_CR3, pagetable_get_paddr(v->arch.shadow_table));
1721 break;
1723 case 4: /* CR4 */
1725 __vmread(CR4_READ_SHADOW, &old_cr);
1727 if ( value & X86_CR4_PAE && !(old_cr & X86_CR4_PAE) )
1729 set_bit(VMX_CPU_STATE_PAE_ENABLED, &v->arch.hvm_vmx.cpu_state);
1731 if ( vmx_pgbit_test(v) )
1733 /* The guest is a 32-bit PAE guest. */
1734 #if CONFIG_PAGING_LEVELS >= 3
1735 unsigned long mfn, old_base_mfn;
1737 if( !shadow_set_guest_paging_levels(v->domain, PAGING_L3) )
1739 printk("Unsupported guest paging levels\n");
1740 domain_crash_synchronous(); /* need to take a clean path */
1743 if ( !VALID_MFN(mfn = get_mfn_from_gpfn(
1744 v->arch.hvm_vmx.cpu_cr3 >> PAGE_SHIFT)) ||
1745 !get_page(mfn_to_page(mfn), v->domain) )
1747 printk("Invalid CR3 value = %lx", v->arch.hvm_vmx.cpu_cr3);
1748 domain_crash_synchronous(); /* need to take a clean path */
1751 old_base_mfn = pagetable_get_pfn(v->arch.guest_table);
1752 if ( old_base_mfn )
1753 put_page(mfn_to_page(old_base_mfn));
1755 /*
1756 * Now arch.guest_table points to machine physical.
1757 */
1759 v->arch.guest_table = pagetable_from_pfn(mfn);
1760 update_pagetables(v);
1762 HVM_DBG_LOG(DBG_LEVEL_VMMU, "New arch.guest_table = %lx",
1763 (unsigned long) (mfn << PAGE_SHIFT));
1765 __vmwrite(GUEST_CR3, pagetable_get_paddr(v->arch.shadow_table));
1767 /*
1768 * arch->shadow_table should hold the next CR3 for shadow
1769 */
1771 HVM_DBG_LOG(DBG_LEVEL_VMMU, "Update CR3 value = %lx, mfn = %lx",
1772 v->arch.hvm_vmx.cpu_cr3, mfn);
1773 #endif
1775 else
1777 /* The guest is a 64 bit or 32-bit PAE guest. */
1778 #if CONFIG_PAGING_LEVELS >= 3
1779 if ( (v->domain->arch.ops != NULL) &&
1780 v->domain->arch.ops->guest_paging_levels == PAGING_L2)
1782 /* Seems the guest first enables PAE without enabling PG,
1783 * it must enable PG after that, and it is a 32-bit PAE
1784 * guest */
1786 if ( !shadow_set_guest_paging_levels(v->domain,
1787 PAGING_L3) )
1789 printk("Unsupported guest paging levels\n");
1790 /* need to take a clean path */
1791 domain_crash_synchronous();
1794 #endif
1797 else if ( value & X86_CR4_PAE )
1798 set_bit(VMX_CPU_STATE_PAE_ENABLED, &v->arch.hvm_vmx.cpu_state);
1799 else
1801 if ( test_bit(VMX_CPU_STATE_LMA_ENABLED, &v->arch.hvm_vmx.cpu_state) )
1802 vmx_inject_hw_exception(v, TRAP_gp_fault, 0);
1804 clear_bit(VMX_CPU_STATE_PAE_ENABLED, &v->arch.hvm_vmx.cpu_state);
1807 __vmwrite(GUEST_CR4, value| VMX_CR4_HOST_MASK);
1808 __vmwrite(CR4_READ_SHADOW, value);
1810 /*
1811 * Writing to CR4 to modify the PSE, PGE, or PAE flag invalidates
1812 * all TLB entries except global entries.
1813 */
1814 if ( (old_cr ^ value) & (X86_CR4_PSE | X86_CR4_PGE | X86_CR4_PAE) )
1815 shadow_sync_all(v->domain);
1817 break;
1819 default:
1820 printk("invalid cr: %d\n", gp);
1821 __hvm_bug(regs);
1824 return 1;
1827 /*
1828 * Read from control registers. CR0 and CR4 are read from the shadow.
1829 */
1830 static void mov_from_cr(int cr, int gp, struct cpu_user_regs *regs)
1832 unsigned long value;
1833 struct vcpu *v = current;
1835 if ( cr != 3 )
1836 __hvm_bug(regs);
1838 value = (unsigned long) v->arch.hvm_vmx.cpu_cr3;
1840 switch ( gp ) {
1841 CASE_SET_REG(EAX, eax);
1842 CASE_SET_REG(ECX, ecx);
1843 CASE_SET_REG(EDX, edx);
1844 CASE_SET_REG(EBX, ebx);
1845 CASE_SET_REG(EBP, ebp);
1846 CASE_SET_REG(ESI, esi);
1847 CASE_SET_REG(EDI, edi);
1848 CASE_EXTEND_SET_REG;
1849 case REG_ESP:
1850 __vmwrite(GUEST_RSP, value);
1851 regs->esp = value;
1852 break;
1853 default:
1854 printk("invalid gp: %d\n", gp);
1855 __hvm_bug(regs);
1858 HVM_DBG_LOG(DBG_LEVEL_VMMU, "CR%d, value = %lx", cr, value);
1861 static int vmx_cr_access(unsigned long exit_qualification, struct cpu_user_regs *regs)
1863 unsigned int gp, cr;
1864 unsigned long value;
1865 struct vcpu *v = current;
1867 switch (exit_qualification & CONTROL_REG_ACCESS_TYPE) {
1868 case TYPE_MOV_TO_CR:
1869 gp = exit_qualification & CONTROL_REG_ACCESS_REG;
1870 cr = exit_qualification & CONTROL_REG_ACCESS_NUM;
1871 TRACE_VMEXIT(1,TYPE_MOV_TO_CR);
1872 TRACE_VMEXIT(2,cr);
1873 TRACE_VMEXIT(3,gp);
1874 return mov_to_cr(gp, cr, regs);
1875 case TYPE_MOV_FROM_CR:
1876 gp = exit_qualification & CONTROL_REG_ACCESS_REG;
1877 cr = exit_qualification & CONTROL_REG_ACCESS_NUM;
1878 TRACE_VMEXIT(1,TYPE_MOV_FROM_CR);
1879 TRACE_VMEXIT(2,cr);
1880 TRACE_VMEXIT(3,gp);
1881 mov_from_cr(cr, gp, regs);
1882 break;
1883 case TYPE_CLTS:
1884 TRACE_VMEXIT(1,TYPE_CLTS);
1886 /* We initialise the FPU now, to avoid needing another vmexit. */
1887 setup_fpu(v);
1888 __vm_clear_bit(EXCEPTION_BITMAP, EXCEPTION_BITMAP_NM);
1890 __vmread_vcpu(v, GUEST_CR0, &value);
1891 value &= ~X86_CR0_TS; /* clear TS */
1892 __vmwrite(GUEST_CR0, value);
1894 __vmread_vcpu(v, CR0_READ_SHADOW, &value);
1895 value &= ~X86_CR0_TS; /* clear TS */
1896 __vmwrite(CR0_READ_SHADOW, value);
1897 break;
1898 case TYPE_LMSW:
1899 TRACE_VMEXIT(1,TYPE_LMSW);
1900 __vmread_vcpu(v, CR0_READ_SHADOW, &value);
1901 value = (value & ~0xF) |
1902 (((exit_qualification & LMSW_SOURCE_DATA) >> 16) & 0xF);
1903 return vmx_set_cr0(value);
1904 break;
1905 default:
1906 __hvm_bug(regs);
1907 break;
1909 return 1;
1912 static inline void vmx_do_msr_read(struct cpu_user_regs *regs)
1914 u64 msr_content = 0;
1915 u32 eax, edx;
1916 struct vcpu *v = current;
1918 HVM_DBG_LOG(DBG_LEVEL_1, "vmx_do_msr_read: ecx=%lx, eax=%lx, edx=%lx",
1919 (unsigned long)regs->ecx, (unsigned long)regs->eax,
1920 (unsigned long)regs->edx);
1921 switch (regs->ecx) {
1922 case MSR_IA32_TIME_STAMP_COUNTER:
1923 msr_content = hvm_get_guest_time(v);
1924 break;
1925 case MSR_IA32_SYSENTER_CS:
1926 __vmread(GUEST_SYSENTER_CS, (u32 *)&msr_content);
1927 break;
1928 case MSR_IA32_SYSENTER_ESP:
1929 __vmread(GUEST_SYSENTER_ESP, &msr_content);
1930 break;
1931 case MSR_IA32_SYSENTER_EIP:
1932 __vmread(GUEST_SYSENTER_EIP, &msr_content);
1933 break;
1934 case MSR_IA32_APICBASE:
1935 msr_content = VLAPIC(v) ? VLAPIC(v)->apic_base_msr : 0;
1936 break;
1937 default:
1938 if (long_mode_do_msr_read(regs))
1939 return;
1941 if ( rdmsr_hypervisor_regs(regs->ecx, &eax, &edx) )
1943 regs->eax = eax;
1944 regs->edx = edx;
1945 return;
1948 rdmsr_safe(regs->ecx, regs->eax, regs->edx);
1949 break;
1952 regs->eax = msr_content & 0xFFFFFFFF;
1953 regs->edx = msr_content >> 32;
1955 HVM_DBG_LOG(DBG_LEVEL_1, "vmx_do_msr_read returns: "
1956 "ecx=%lx, eax=%lx, edx=%lx",
1957 (unsigned long)regs->ecx, (unsigned long)regs->eax,
1958 (unsigned long)regs->edx);
1961 static inline void vmx_do_msr_write(struct cpu_user_regs *regs)
1963 u64 msr_content;
1964 struct vcpu *v = current;
1966 HVM_DBG_LOG(DBG_LEVEL_1, "vmx_do_msr_write: ecx=%lx, eax=%lx, edx=%lx",
1967 (unsigned long)regs->ecx, (unsigned long)regs->eax,
1968 (unsigned long)regs->edx);
1970 msr_content = (regs->eax & 0xFFFFFFFF) | ((u64)regs->edx << 32);
1972 switch (regs->ecx) {
1973 case MSR_IA32_TIME_STAMP_COUNTER:
1974 set_guest_time(v, msr_content);
1975 break;
1976 case MSR_IA32_SYSENTER_CS:
1977 __vmwrite(GUEST_SYSENTER_CS, msr_content);
1978 break;
1979 case MSR_IA32_SYSENTER_ESP:
1980 __vmwrite(GUEST_SYSENTER_ESP, msr_content);
1981 break;
1982 case MSR_IA32_SYSENTER_EIP:
1983 __vmwrite(GUEST_SYSENTER_EIP, msr_content);
1984 break;
1985 case MSR_IA32_APICBASE:
1986 vlapic_msr_set(VLAPIC(v), msr_content);
1987 break;
1988 default:
1989 if ( !long_mode_do_msr_write(regs) )
1990 wrmsr_hypervisor_regs(regs->ecx, regs->eax, regs->edx);
1991 break;
1994 HVM_DBG_LOG(DBG_LEVEL_1, "vmx_do_msr_write returns: "
1995 "ecx=%lx, eax=%lx, edx=%lx",
1996 (unsigned long)regs->ecx, (unsigned long)regs->eax,
1997 (unsigned long)regs->edx);
2000 /*
2001 * Need to use this exit to reschedule
2002 */
2003 void vmx_vmexit_do_hlt(void)
2005 struct vcpu *v=current;
2006 struct periodic_time *pt = &(v->domain->arch.hvm_domain.pl_time.periodic_tm);
2007 s_time_t next_pit=-1,next_wakeup;
2009 if ( !v->vcpu_id )
2010 next_pit = get_scheduled(v, pt->irq, pt);
2011 next_wakeup = get_apictime_scheduled(v);
2012 if ( (next_pit != -1 && next_pit < next_wakeup) || next_wakeup == -1 )
2013 next_wakeup = next_pit;
2014 if ( next_wakeup != - 1 )
2015 set_timer(&current->arch.hvm_vmx.hlt_timer, next_wakeup);
2016 hvm_safe_block();
2019 static inline void vmx_vmexit_do_extint(struct cpu_user_regs *regs)
2021 unsigned int vector;
2022 int error;
2024 asmlinkage void do_IRQ(struct cpu_user_regs *);
2025 fastcall void smp_apic_timer_interrupt(struct cpu_user_regs *);
2026 fastcall void smp_event_check_interrupt(void);
2027 fastcall void smp_invalidate_interrupt(void);
2028 fastcall void smp_call_function_interrupt(void);
2029 fastcall void smp_spurious_interrupt(struct cpu_user_regs *regs);
2030 fastcall void smp_error_interrupt(struct cpu_user_regs *regs);
2031 #ifdef CONFIG_X86_MCE_P4THERMAL
2032 fastcall void smp_thermal_interrupt(struct cpu_user_regs *regs);
2033 #endif
2035 if ((error = __vmread(VM_EXIT_INTR_INFO, &vector))
2036 && !(vector & INTR_INFO_VALID_MASK))
2037 __hvm_bug(regs);
2039 vector &= INTR_INFO_VECTOR_MASK;
2040 TRACE_VMEXIT(1,vector);
2042 switch(vector) {
2043 case LOCAL_TIMER_VECTOR:
2044 smp_apic_timer_interrupt(regs);
2045 break;
2046 case EVENT_CHECK_VECTOR:
2047 smp_event_check_interrupt();
2048 break;
2049 case INVALIDATE_TLB_VECTOR:
2050 smp_invalidate_interrupt();
2051 break;
2052 case CALL_FUNCTION_VECTOR:
2053 smp_call_function_interrupt();
2054 break;
2055 case SPURIOUS_APIC_VECTOR:
2056 smp_spurious_interrupt(regs);
2057 break;
2058 case ERROR_APIC_VECTOR:
2059 smp_error_interrupt(regs);
2060 break;
2061 #ifdef CONFIG_X86_MCE_P4THERMAL
2062 case THERMAL_APIC_VECTOR:
2063 smp_thermal_interrupt(regs);
2064 break;
2065 #endif
2066 default:
2067 regs->entry_vector = vector;
2068 do_IRQ(regs);
2069 break;
2073 #if defined (__x86_64__)
2074 void store_cpu_user_regs(struct cpu_user_regs *regs)
2076 __vmread(GUEST_SS_SELECTOR, &regs->ss);
2077 __vmread(GUEST_RSP, &regs->rsp);
2078 __vmread(GUEST_RFLAGS, &regs->rflags);
2079 __vmread(GUEST_CS_SELECTOR, &regs->cs);
2080 __vmread(GUEST_DS_SELECTOR, &regs->ds);
2081 __vmread(GUEST_ES_SELECTOR, &regs->es);
2082 __vmread(GUEST_RIP, &regs->rip);
2084 #elif defined (__i386__)
2085 void store_cpu_user_regs(struct cpu_user_regs *regs)
2087 __vmread(GUEST_SS_SELECTOR, &regs->ss);
2088 __vmread(GUEST_RSP, &regs->esp);
2089 __vmread(GUEST_RFLAGS, &regs->eflags);
2090 __vmread(GUEST_CS_SELECTOR, &regs->cs);
2091 __vmread(GUEST_DS_SELECTOR, &regs->ds);
2092 __vmread(GUEST_ES_SELECTOR, &regs->es);
2093 __vmread(GUEST_RIP, &regs->eip);
2095 #endif
2097 #ifdef XEN_DEBUGGER
2098 void save_cpu_user_regs(struct cpu_user_regs *regs)
2100 __vmread(GUEST_SS_SELECTOR, &regs->xss);
2101 __vmread(GUEST_RSP, &regs->esp);
2102 __vmread(GUEST_RFLAGS, &regs->eflags);
2103 __vmread(GUEST_CS_SELECTOR, &regs->xcs);
2104 __vmread(GUEST_RIP, &regs->eip);
2106 __vmread(GUEST_GS_SELECTOR, &regs->xgs);
2107 __vmread(GUEST_FS_SELECTOR, &regs->xfs);
2108 __vmread(GUEST_ES_SELECTOR, &regs->xes);
2109 __vmread(GUEST_DS_SELECTOR, &regs->xds);
2112 void restore_cpu_user_regs(struct cpu_user_regs *regs)
2114 __vmwrite(GUEST_SS_SELECTOR, regs->xss);
2115 __vmwrite(GUEST_RSP, regs->esp);
2116 __vmwrite(GUEST_RFLAGS, regs->eflags);
2117 __vmwrite(GUEST_CS_SELECTOR, regs->xcs);
2118 __vmwrite(GUEST_RIP, regs->eip);
2120 __vmwrite(GUEST_GS_SELECTOR, regs->xgs);
2121 __vmwrite(GUEST_FS_SELECTOR, regs->xfs);
2122 __vmwrite(GUEST_ES_SELECTOR, regs->xes);
2123 __vmwrite(GUEST_DS_SELECTOR, regs->xds);
2125 #endif
2127 asmlinkage void vmx_vmexit_handler(struct cpu_user_regs regs)
2129 unsigned int exit_reason;
2130 unsigned long exit_qualification, eip, inst_len = 0;
2131 struct vcpu *v = current;
2132 int error;
2134 error = __vmread(VM_EXIT_REASON, &exit_reason);
2135 BUG_ON(error);
2137 perfc_incra(vmexits, exit_reason);
2139 if ( (exit_reason != EXIT_REASON_EXTERNAL_INTERRUPT) &&
2140 (exit_reason != EXIT_REASON_VMCALL) &&
2141 (exit_reason != EXIT_REASON_IO_INSTRUCTION) )
2142 HVM_DBG_LOG(DBG_LEVEL_0, "exit reason = %x", exit_reason);
2144 if ( exit_reason != EXIT_REASON_EXTERNAL_INTERRUPT )
2145 local_irq_enable();
2147 if ( unlikely(exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) )
2149 unsigned int failed_vmentry_reason = exit_reason & 0xFFFF;
2151 __vmread(EXIT_QUALIFICATION, &exit_qualification);
2152 printk("Failed vm entry (exit reason 0x%x) ", exit_reason);
2153 switch ( failed_vmentry_reason ) {
2154 case EXIT_REASON_INVALID_GUEST_STATE:
2155 printk("caused by invalid guest state (%ld).\n", exit_qualification);
2156 break;
2157 case EXIT_REASON_MSR_LOADING:
2158 printk("caused by MSR entry %ld loading.\n", exit_qualification);
2159 break;
2160 case EXIT_REASON_MACHINE_CHECK:
2161 printk("caused by machine check.\n");
2162 break;
2163 default:
2164 printk("reason not known yet!");
2165 break;
2168 printk("************* VMCS Area **************\n");
2169 vmcs_dump_vcpu();
2170 printk("**************************************\n");
2171 domain_crash_synchronous();
2174 __vmread(GUEST_RIP, &eip);
2175 TRACE_VMEXIT(0,exit_reason);
2177 switch ( exit_reason )
2179 case EXIT_REASON_EXCEPTION_NMI:
2181 /*
2182 * We don't set the software-interrupt exiting (INT n).
2183 * (1) We can get an exception (e.g. #PG) in the guest, or
2184 * (2) NMI
2185 */
2186 int error;
2187 unsigned int vector;
2188 unsigned long va;
2190 if ((error = __vmread(VM_EXIT_INTR_INFO, &vector))
2191 || !(vector & INTR_INFO_VALID_MASK))
2192 __hvm_bug(&regs);
2193 vector &= INTR_INFO_VECTOR_MASK;
2195 TRACE_VMEXIT(1,vector);
2196 perfc_incra(cause_vector, vector);
2198 switch (vector) {
2199 #ifdef XEN_DEBUGGER
2200 case TRAP_debug:
2202 save_cpu_user_regs(&regs);
2203 pdb_handle_exception(1, &regs, 1);
2204 restore_cpu_user_regs(&regs);
2205 break;
2207 case TRAP_int3:
2209 save_cpu_user_regs(&regs);
2210 pdb_handle_exception(3, &regs, 1);
2211 restore_cpu_user_regs(&regs);
2212 break;
2214 #else
2215 case TRAP_debug:
2217 void store_cpu_user_regs(struct cpu_user_regs *regs);
2219 if ( test_bit(_DOMF_debugging, &v->domain->domain_flags) )
2221 store_cpu_user_regs(&regs);
2222 domain_pause_for_debugger();
2223 __vm_clear_bit(GUEST_PENDING_DBG_EXCEPTIONS,
2224 PENDING_DEBUG_EXC_BS);
2226 else
2228 vmx_reflect_exception(v);
2229 __vm_clear_bit(GUEST_PENDING_DBG_EXCEPTIONS,
2230 PENDING_DEBUG_EXC_BS);
2233 break;
2235 case TRAP_int3:
2237 if ( test_bit(_DOMF_debugging, &v->domain->domain_flags) )
2238 domain_pause_for_debugger();
2239 else
2240 vmx_reflect_exception(v);
2241 break;
2243 #endif
2244 case TRAP_no_device:
2246 vmx_do_no_device_fault();
2247 break;
2249 case TRAP_page_fault:
2251 __vmread(EXIT_QUALIFICATION, &va);
2252 __vmread(VM_EXIT_INTR_ERROR_CODE, &regs.error_code);
2254 TRACE_VMEXIT(3,regs.error_code);
2255 TRACE_VMEXIT(4,va);
2257 HVM_DBG_LOG(DBG_LEVEL_VMMU,
2258 "eax=%lx, ebx=%lx, ecx=%lx, edx=%lx, esi=%lx, edi=%lx",
2259 (unsigned long)regs.eax, (unsigned long)regs.ebx,
2260 (unsigned long)regs.ecx, (unsigned long)regs.edx,
2261 (unsigned long)regs.esi, (unsigned long)regs.edi);
2263 if (!(error = vmx_do_page_fault(va, &regs))) {
2264 /*
2265 * Inject #PG using Interruption-Information Fields
2266 */
2267 vmx_inject_hw_exception(v, TRAP_page_fault, regs.error_code);
2268 v->arch.hvm_vmx.cpu_cr2 = va;
2269 TRACE_3D(TRC_VMX_INT, v->domain->domain_id, TRAP_page_fault, va);
2271 break;
2273 case TRAP_nmi:
2274 do_nmi(&regs);
2275 break;
2276 default:
2277 vmx_reflect_exception(v);
2278 break;
2280 break;
2282 case EXIT_REASON_EXTERNAL_INTERRUPT:
2283 vmx_vmexit_do_extint(&regs);
2284 break;
2285 case EXIT_REASON_PENDING_INTERRUPT:
2286 /*
2287 * Not sure exactly what the purpose of this is. The only bits set
2288 * and cleared at this point are CPU_BASED_VIRTUAL_INTR_PENDING.
2289 * (in io.c:{enable,disable}_irq_window(). So presumably we want to
2290 * set it to the original value...
2291 */
2292 v->arch.hvm_vcpu.u.vmx.exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
2293 v->arch.hvm_vcpu.u.vmx.exec_control |=
2294 (MONITOR_CPU_BASED_EXEC_CONTROLS & CPU_BASED_VIRTUAL_INTR_PENDING);
2295 __vmwrite(CPU_BASED_VM_EXEC_CONTROL,
2296 v->arch.hvm_vcpu.u.vmx.exec_control);
2297 break;
2298 case EXIT_REASON_TASK_SWITCH:
2299 __hvm_bug(&regs);
2300 break;
2301 case EXIT_REASON_CPUID:
2302 vmx_vmexit_do_cpuid(&regs);
2303 __get_instruction_length(inst_len);
2304 __update_guest_eip(inst_len);
2305 break;
2306 case EXIT_REASON_HLT:
2307 __get_instruction_length(inst_len);
2308 __update_guest_eip(inst_len);
2309 vmx_vmexit_do_hlt();
2310 break;
2311 case EXIT_REASON_INVLPG:
2313 unsigned long va;
2315 __vmread(EXIT_QUALIFICATION, &va);
2316 vmx_vmexit_do_invlpg(va);
2317 __get_instruction_length(inst_len);
2318 __update_guest_eip(inst_len);
2319 break;
2321 case EXIT_REASON_VMCALL:
2323 __get_instruction_length(inst_len);
2324 __vmread(GUEST_RIP, &eip);
2325 __vmread(EXIT_QUALIFICATION, &exit_qualification);
2327 hvm_do_hypercall(&regs);
2328 __update_guest_eip(inst_len);
2329 break;
2331 case EXIT_REASON_CR_ACCESS:
2333 __vmread(GUEST_RIP, &eip);
2334 __get_instruction_length(inst_len);
2335 __vmread(EXIT_QUALIFICATION, &exit_qualification);
2337 HVM_DBG_LOG(DBG_LEVEL_1, "eip = %lx, inst_len =%lx, exit_qualification = %lx",
2338 eip, inst_len, exit_qualification);
2339 if (vmx_cr_access(exit_qualification, &regs))
2340 __update_guest_eip(inst_len);
2341 TRACE_VMEXIT(3,regs.error_code);
2342 TRACE_VMEXIT(4,exit_qualification);
2343 break;
2345 case EXIT_REASON_DR_ACCESS:
2346 __vmread(EXIT_QUALIFICATION, &exit_qualification);
2347 vmx_dr_access(exit_qualification, &regs);
2348 __get_instruction_length(inst_len);
2349 __update_guest_eip(inst_len);
2350 break;
2351 case EXIT_REASON_IO_INSTRUCTION:
2352 __vmread(EXIT_QUALIFICATION, &exit_qualification);
2353 __get_instruction_length(inst_len);
2354 vmx_io_instruction(exit_qualification, inst_len);
2355 TRACE_VMEXIT(4,exit_qualification);
2356 break;
2357 case EXIT_REASON_MSR_READ:
2358 __get_instruction_length(inst_len);
2359 vmx_do_msr_read(&regs);
2360 __update_guest_eip(inst_len);
2361 break;
2362 case EXIT_REASON_MSR_WRITE:
2363 __vmread(GUEST_RIP, &eip);
2364 vmx_do_msr_write(&regs);
2365 __get_instruction_length(inst_len);
2366 __update_guest_eip(inst_len);
2367 break;
2368 case EXIT_REASON_MWAIT_INSTRUCTION:
2369 __hvm_bug(&regs);
2370 break;
2371 case EXIT_REASON_VMCLEAR:
2372 case EXIT_REASON_VMLAUNCH:
2373 case EXIT_REASON_VMPTRLD:
2374 case EXIT_REASON_VMPTRST:
2375 case EXIT_REASON_VMREAD:
2376 case EXIT_REASON_VMRESUME:
2377 case EXIT_REASON_VMWRITE:
2378 case EXIT_REASON_VMOFF:
2379 case EXIT_REASON_VMON:
2380 /* Report invalid opcode exception when a VMX guest tries to execute
2381 any of the VMX instructions */
2382 vmx_inject_hw_exception(v, TRAP_invalid_op, VMX_DELIVER_NO_ERROR_CODE);
2383 break;
2385 default:
2386 __hvm_bug(&regs); /* should not happen */
2390 asmlinkage void vmx_load_cr2(void)
2392 struct vcpu *v = current;
2394 local_irq_disable();
2395 asm volatile("mov %0,%%cr2": :"r" (v->arch.hvm_vmx.cpu_cr2));
2398 asmlinkage void vmx_trace_vmentry (void)
2400 TRACE_5D(TRC_VMX_VMENTRY,
2401 trace_values[smp_processor_id()][0],
2402 trace_values[smp_processor_id()][1],
2403 trace_values[smp_processor_id()][2],
2404 trace_values[smp_processor_id()][3],
2405 trace_values[smp_processor_id()][4]);
2406 TRACE_VMEXIT(0,9);
2407 TRACE_VMEXIT(1,9);
2408 TRACE_VMEXIT(2,9);
2409 TRACE_VMEXIT(3,9);
2410 TRACE_VMEXIT(4,9);
2411 return;
2414 asmlinkage void vmx_trace_vmexit (void)
2416 TRACE_3D(TRC_VMX_VMEXIT,0,0,0);
2417 return;
2420 /*
2421 * Local variables:
2422 * mode: C
2423 * c-set-style: "BSD"
2424 * c-basic-offset: 4
2425 * tab-width: 4
2426 * indent-tabs-mode: nil
2427 * End:
2428 */