ia64/xen-unstable

view tools/ioemu/hw/pass-through.h @ 18438:a5bf2535e7bb

ioemu: support PCI Express Capability Structure version 1.
Signed-off-by: Yuji Shimada <shimada-yxb@necst.nec.co.jp>
author Keir Fraser <keir.fraser@citrix.com>
date Thu Sep 04 11:28:17 2008 +0100 (2008-09-04)
parents 0638a5c2cc9f
children
line source
1 /*
2 * Copyright (c) 2007, Neocleus Corporation.
3 * Copyright (c) 2007, Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
16 * Place - Suite 330, Boston, MA 02111-1307 USA.
17 */
18 #ifndef __PASSTHROUGH_H__
19 #define __PASSTHROUGH_H__
21 #include "vl.h"
22 #include "pci/header.h"
23 #include "pci/pci.h"
24 #include "audio/sys-queue.h"
26 /* Log acesss */
27 #define PT_LOGGING_ENABLED
29 #ifdef PT_LOGGING_ENABLED
30 #define PT_LOG(_f, _a...) fprintf(logfile, "%s: " _f, __func__, ##_a)
31 #else
32 #define PT_LOG(_f, _a...)
33 #endif
35 /* Some compilation flags */
36 // #define PT_DEBUG_PCI_CONFIG_ACCESS
38 #define PT_MACHINE_IRQ_AUTO (0xFFFFFFFF)
39 #define PT_VIRT_DEVFN_AUTO (-1)
41 /* Misc PCI constants that should be moved to a separate library :) */
42 #define PCI_CONFIG_SIZE (256)
43 #define PCI_EXP_DEVCAP_FLR (1 << 28)
44 #define PCI_EXP_DEVCTL_FLR (1 << 15)
45 #define PCI_BAR_ENTRIES (6)
47 /* because the current version of libpci (2.2.0) doesn't define these ID,
48 * so we define Capability ID here.
49 */
50 #ifndef PCI_CAP_ID_HOTPLUG
51 /* SHPC Capability List Item reg group */
52 #define PCI_CAP_ID_HOTPLUG 0x0C
53 #endif
55 #ifndef PCI_CAP_ID_SSVID
56 /* Subsystem ID and Subsystem Vendor ID Capability List Item reg group */
57 #define PCI_CAP_ID_SSVID 0x0D
58 #endif
60 #ifndef PCI_MSI_FLAGS_MASK_BIT
61 /* interrupt masking & reporting supported */
62 #define PCI_MSI_FLAGS_MASK_BIT 0x0100
63 #endif
65 #ifndef PCI_EXP_TYPE_PCIE_BRIDGE
66 /* PCI/PCI-X to PCIE Bridge */
67 #define PCI_EXP_TYPE_PCIE_BRIDGE 0x8
68 #endif
70 #ifndef PCI_EXP_TYPE_ROOT_INT_EP
71 /* Root Complex Integrated Endpoint */
72 #define PCI_EXP_TYPE_ROOT_INT_EP 0x9
73 #endif
75 #ifndef PCI_EXP_TYPE_ROOT_EC
76 /* Root Complex Event Collector */
77 #define PCI_EXP_TYPE_ROOT_EC 0xa
78 #endif
80 #define PT_INVALID_REG 0xFFFFFFFF /* invalid register value */
81 #define PT_BAR_ALLF 0xFFFFFFFF /* BAR ALLF value */
82 #define PT_BAR_MEM_RO_MASK 0x0000000F /* BAR ReadOnly mask(Memory) */
83 #define PT_BAR_MEM_EMU_MASK 0xFFFFFFF0 /* BAR emul mask(Memory) */
84 #define PT_BAR_IO_RO_MASK 0x00000003 /* BAR ReadOnly mask(I/O) */
85 #define PT_BAR_IO_EMU_MASK 0xFFFFFFFC /* BAR emul mask(I/O) */
86 enum {
87 PT_BAR_FLAG_MEM = 0, /* Memory type BAR */
88 PT_BAR_FLAG_IO, /* I/O type BAR */
89 PT_BAR_FLAG_UPPER, /* upper 64bit BAR */
90 PT_BAR_FLAG_UNUSED, /* unused BAR */
91 };
92 enum {
93 GRP_TYPE_HARDWIRED = 0, /* 0 Hardwired reg group */
94 GRP_TYPE_EMU, /* emul reg group */
95 };
97 #define PT_GET_EMUL_SIZE(flag, r_size) do { \
98 if (flag == PT_BAR_FLAG_MEM) {\
99 r_size = (((r_size) + XC_PAGE_SIZE - 1) & ~(XC_PAGE_SIZE - 1)); \
100 }\
101 } while(0)
104 struct pt_region {
105 /* Virtual phys base & size */
106 uint32_t e_physbase;
107 uint32_t e_size;
108 /* Index of region in qemu */
109 uint32_t memory_index;
110 /* BAR flag */
111 uint32_t bar_flag;
112 /* Translation of the emulated address */
113 union {
114 uint64_t maddr;
115 uint64_t pio_base;
116 uint64_t u;
117 } access;
118 };
120 struct pt_msi_info {
121 uint32_t flags;
122 int pirq; /* guest pirq corresponding */
123 uint32_t addr_lo; /* guest message address */
124 uint32_t addr_hi; /* guest message upper address */
125 uint16_t data; /* guest message data */
126 };
128 struct msix_entry_info {
129 int pirq; /* -1 means unmapped */
130 int flags; /* flags indicting whether MSI ADDR or DATA is updated */
131 uint32_t io_mem[4];
132 };
134 struct pt_msix_info {
135 int enabled;
136 int total_entries;
137 int bar_index;
138 uint64_t table_base;
139 uint32_t table_off;
140 uint64_t mmio_base_addr;
141 int mmio_index;
142 int fd;
143 void *phys_iomem_base;
144 struct msix_entry_info msix_entry[0];
145 };
147 /*
148 This structure holds the context of the mapping functions
149 and data that is relevant for qemu device management.
150 */
151 struct pt_dev {
152 PCIDevice dev;
153 struct pci_dev *pci_dev; /* libpci struct */
154 struct pt_region bases[PCI_NUM_REGIONS]; /* Access regions */
155 LIST_HEAD (reg_grp_tbl_listhead, pt_reg_grp_tbl) reg_grp_tbl_head;
156 /* emul reg group list */
157 struct pt_msi_info *msi; /* MSI virtualization */
158 struct pt_msix_info *msix; /* MSI-X virtualization */
159 };
161 /* Used for formatting PCI BDF into cf8 format */
162 struct pci_config_cf8 {
163 union {
164 unsigned int value;
165 struct {
166 unsigned int reserved1:2;
167 unsigned int reg:6;
168 unsigned int func:3;
169 unsigned int dev:5;
170 unsigned int bus:8;
171 unsigned int reserved2:7;
172 unsigned int enable:1;
173 };
174 };
175 };
177 int pt_init(PCIBus * e_bus, char * direct_pci);
179 /* emul reg group management table */
180 struct pt_reg_grp_tbl {
181 /* emul reg group list */
182 LIST_ENTRY (pt_reg_grp_tbl) entries;
183 /* emul reg group info table */
184 struct pt_reg_grp_info_tbl *reg_grp;
185 /* emul reg group base offset */
186 uint32_t base_offset;
187 /* emul reg group size */
188 uint8_t size;
189 /* emul reg management table list */
190 LIST_HEAD (reg_tbl_listhead, pt_reg_tbl) reg_tbl_head;
191 };
193 /* emul reg group size initialize method */
194 typedef uint8_t (*pt_reg_size_init) (struct pt_dev *ptdev,
195 struct pt_reg_grp_info_tbl *grp_reg,
196 uint32_t base_offset);
197 /* emul reg group infomation table */
198 struct pt_reg_grp_info_tbl {
199 /* emul reg group ID */
200 uint8_t grp_id;
201 /* emul reg group type */
202 uint8_t grp_type;
203 /* emul reg group size */
204 uint8_t grp_size;
205 /* emul reg get size method */
206 pt_reg_size_init size_init;
207 /* emul reg info table */
208 struct pt_reg_info_tbl *emu_reg_tbl;
209 };
211 /* emul reg management table */
212 struct pt_reg_tbl {
213 /* emul reg table list */
214 LIST_ENTRY (pt_reg_tbl) entries;
215 /* emul reg info table */
216 struct pt_reg_info_tbl *reg;
217 /* emul reg value */
218 uint32_t data;
219 };
221 /* emul reg initialize method */
222 typedef uint32_t (*conf_reg_init) (struct pt_dev *ptdev,
223 struct pt_reg_info_tbl *reg,
224 uint32_t real_offset);
225 /* emul reg long write method */
226 typedef int (*conf_dword_write) (struct pt_dev *ptdev,
227 struct pt_reg_tbl *cfg_entry,
228 uint32_t *value,
229 uint32_t dev_value,
230 uint32_t valid_mask);
231 /* emul reg word write method */
232 typedef int (*conf_word_write) (struct pt_dev *ptdev,
233 struct pt_reg_tbl *cfg_entry,
234 uint16_t *value,
235 uint16_t dev_value,
236 uint16_t valid_mask);
237 /* emul reg byte write method */
238 typedef int (*conf_byte_write) (struct pt_dev *ptdev,
239 struct pt_reg_tbl *cfg_entry,
240 uint8_t *value,
241 uint8_t dev_value,
242 uint8_t valid_mask);
243 /* emul reg long read methods */
244 typedef int (*conf_dword_read) (struct pt_dev *ptdev,
245 struct pt_reg_tbl *cfg_entry,
246 uint32_t *value,
247 uint32_t valid_mask);
248 /* emul reg word read method */
249 typedef int (*conf_word_read) (struct pt_dev *ptdev,
250 struct pt_reg_tbl *cfg_entry,
251 uint16_t *value,
252 uint16_t valid_mask);
253 /* emul reg byte read method */
254 typedef int (*conf_byte_read) (struct pt_dev *ptdev,
255 struct pt_reg_tbl *cfg_entry,
256 uint8_t *value,
257 uint8_t valid_mask);
259 /* emul reg infomation table */
260 struct pt_reg_info_tbl {
261 /* reg relative offset */
262 uint32_t offset;
263 /* reg size */
264 uint32_t size;
265 /* reg initial value */
266 uint32_t init_val;
267 /* reg read only field mask (ON:RO/ROS, OFF:other) */
268 uint32_t ro_mask;
269 /* reg emulate field mask (ON:emu, OFF:passthrough) */
270 uint32_t emu_mask;
271 /* emul reg initialize method */
272 conf_reg_init init;
273 union {
274 struct {
275 /* emul reg long write method */
276 conf_dword_write write;
277 /* emul reg long read method */
278 conf_dword_read read;
279 } dw;
280 struct {
281 /* emul reg word write method */
282 conf_word_write write;
283 /* emul reg word read method */
284 conf_word_read read;
285 } w;
286 struct {
287 /* emul reg byte write method */
288 conf_byte_write write;
289 /* emul reg byte read method */
290 conf_byte_read read;
291 } b;
292 } u;
293 };
295 #endif /* __PASSTHROUGH_H__ */