ia64/xen-unstable

view tools/ioemu/hw/pass-through.c @ 18438:a5bf2535e7bb

ioemu: support PCI Express Capability Structure version 1.
Signed-off-by: Yuji Shimada <shimada-yxb@necst.nec.co.jp>
author Keir Fraser <keir.fraser@citrix.com>
date Thu Sep 04 11:28:17 2008 +0100 (2008-09-04)
parents 5d30ca2b2efd
children
line source
1 /*
2 * Copyright (c) 2007, Neocleus Corporation.
3 * Copyright (c) 2007, Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
16 * Place - Suite 330, Boston, MA 02111-1307 USA.
17 *
18 * Alex Novik <alex@neocleus.com>
19 * Allen Kay <allen.m.kay@intel.com>
20 * Guy Zana <guy@neocleus.com>
21 *
22 * This file implements direct PCI assignment to a HVM guest
23 */
25 #include "vl.h"
26 #include "pass-through.h"
27 #include "pci/header.h"
28 #include "pci/pci.h"
29 #include "pt-msi.h"
31 extern FILE *logfile;
33 struct php_dev {
34 struct pt_dev *pt_dev;
35 uint8_t valid;
36 uint8_t r_bus;
37 uint8_t r_dev;
38 uint8_t r_func;
39 };
40 struct dpci_infos {
42 struct php_dev php_devs[PHP_SLOT_LEN];
44 PCIBus *e_bus;
45 struct pci_access *pci_access;
47 } dpci_infos;
49 /* prototype */
50 static uint32_t pt_common_reg_init(struct pt_dev *ptdev,
51 struct pt_reg_info_tbl *reg, uint32_t real_offset);
52 static uint32_t pt_ptr_reg_init(struct pt_dev *ptdev,
53 struct pt_reg_info_tbl *reg, uint32_t real_offset);
54 static uint32_t pt_status_reg_init(struct pt_dev *ptdev,
55 struct pt_reg_info_tbl *reg, uint32_t real_offset);
56 static uint32_t pt_irqpin_reg_init(struct pt_dev *ptdev,
57 struct pt_reg_info_tbl *reg, uint32_t real_offset);
58 static uint32_t pt_bar_reg_init(struct pt_dev *ptdev,
59 struct pt_reg_info_tbl *reg, uint32_t real_offset);
60 static uint32_t pt_linkctrl_reg_init(struct pt_dev *ptdev,
61 struct pt_reg_info_tbl *reg, uint32_t real_offset);
62 static uint32_t pt_devctrl2_reg_init(struct pt_dev *ptdev,
63 struct pt_reg_info_tbl *reg, uint32_t real_offset);
64 static uint32_t pt_linkctrl2_reg_init(struct pt_dev *ptdev,
65 struct pt_reg_info_tbl *reg, uint32_t real_offset);
66 static uint32_t pt_msgctrl_reg_init(struct pt_dev *ptdev,
67 struct pt_reg_info_tbl *reg, uint32_t real_offset);
68 static uint32_t pt_msgaddr32_reg_init(struct pt_dev *ptdev,
69 struct pt_reg_info_tbl *reg, uint32_t real_offset);
70 static uint32_t pt_msgaddr64_reg_init(struct pt_dev *ptdev,
71 struct pt_reg_info_tbl *reg, uint32_t real_offset);
72 static uint32_t pt_msgdata_reg_init(struct pt_dev *ptdev,
73 struct pt_reg_info_tbl *reg, uint32_t real_offset);
74 static uint32_t pt_msixctrl_reg_init(struct pt_dev *ptdev,
75 struct pt_reg_info_tbl *reg, uint32_t real_offset);
76 static uint8_t pt_reg_grp_size_init(struct pt_dev *ptdev,
77 struct pt_reg_grp_info_tbl *grp_reg, uint32_t base_offset);
78 static uint8_t pt_msi_size_init(struct pt_dev *ptdev,
79 struct pt_reg_grp_info_tbl *grp_reg, uint32_t base_offset);
80 static uint8_t pt_msix_size_init(struct pt_dev *ptdev,
81 struct pt_reg_grp_info_tbl *grp_reg, uint32_t base_offset);
82 static uint8_t pt_vendor_size_init(struct pt_dev *ptdev,
83 struct pt_reg_grp_info_tbl *grp_reg, uint32_t base_offset);
84 static uint8_t pt_pcie_size_init(struct pt_dev *ptdev,
85 struct pt_reg_grp_info_tbl *grp_reg, uint32_t base_offset);
86 static int pt_byte_reg_read(struct pt_dev *ptdev,
87 struct pt_reg_tbl *cfg_entry,
88 uint8_t *valueu, uint8_t valid_mask);
89 static int pt_word_reg_read(struct pt_dev *ptdev,
90 struct pt_reg_tbl *cfg_entry,
91 uint16_t *value, uint16_t valid_mask);
92 static int pt_long_reg_read(struct pt_dev *ptdev,
93 struct pt_reg_tbl *cfg_entry,
94 uint32_t *value, uint32_t valid_mask);
95 static int pt_bar_reg_read(struct pt_dev *ptdev,
96 struct pt_reg_tbl *cfg_entry,
97 uint32_t *value, uint32_t valid_mask);
98 static int pt_byte_reg_write(struct pt_dev *ptdev,
99 struct pt_reg_tbl *cfg_entry,
100 uint8_t *value, uint8_t dev_value, uint8_t valid_mask);
101 static int pt_word_reg_write(struct pt_dev *ptdev,
102 struct pt_reg_tbl *cfg_entry,
103 uint16_t *value, uint16_t dev_value, uint16_t valid_mask);
104 static int pt_long_reg_write(struct pt_dev *ptdev,
105 struct pt_reg_tbl *cfg_entry,
106 uint32_t *value, uint32_t dev_value, uint32_t valid_mask);
107 static int pt_cmd_reg_write(struct pt_dev *ptdev,
108 struct pt_reg_tbl *cfg_entry,
109 uint16_t *value, uint16_t dev_value, uint16_t valid_mask);
110 static int pt_bar_reg_write(struct pt_dev *ptdev,
111 struct pt_reg_tbl *cfg_entry,
112 uint32_t *value, uint32_t dev_value, uint32_t valid_mask);
113 static int pt_exp_rom_bar_reg_write(struct pt_dev *ptdev,
114 struct pt_reg_tbl *cfg_entry,
115 uint32_t *value, uint32_t dev_value, uint32_t valid_mask);
116 static int pt_pmcsr_reg_write(struct pt_dev *ptdev,
117 struct pt_reg_tbl *cfg_entry,
118 uint16_t *value, uint16_t dev_value, uint16_t valid_mask);
119 static int pt_devctrl_reg_write(struct pt_dev *ptdev,
120 struct pt_reg_tbl *cfg_entry,
121 uint16_t *value, uint16_t dev_value, uint16_t valid_mask);
122 static int pt_linkctrl_reg_write(struct pt_dev *ptdev,
123 struct pt_reg_tbl *cfg_entry,
124 uint16_t *value, uint16_t dev_value, uint16_t valid_mask);
125 static int pt_devctrl2_reg_write(struct pt_dev *ptdev,
126 struct pt_reg_tbl *cfg_entry,
127 uint16_t *value, uint16_t dev_value, uint16_t valid_mask);
128 static int pt_linkctrl2_reg_write(struct pt_dev *ptdev,
129 struct pt_reg_tbl *cfg_entry,
130 uint16_t *value, uint16_t dev_value, uint16_t valid_mask);
131 static int pt_msgctrl_reg_write(struct pt_dev *ptdev,
132 struct pt_reg_tbl *cfg_entry,
133 uint16_t *value, uint16_t dev_value, uint16_t valid_mask);
134 static int pt_msgaddr32_reg_write(struct pt_dev *ptdev,
135 struct pt_reg_tbl *cfg_entry,
136 uint32_t *value, uint32_t dev_value, uint32_t valid_mask);
137 static int pt_msgaddr64_reg_write(struct pt_dev *ptdev,
138 struct pt_reg_tbl *cfg_entry,
139 uint32_t *value, uint32_t dev_value, uint32_t valid_mask);
140 static int pt_msgdata_reg_write(struct pt_dev *ptdev,
141 struct pt_reg_tbl *cfg_entry,
142 uint16_t *value, uint16_t dev_value, uint16_t valid_mask);
143 static int pt_msixctrl_reg_write(struct pt_dev *ptdev,
144 struct pt_reg_tbl *cfg_entry,
145 uint16_t *value, uint16_t dev_value, uint16_t valid_mask);
147 /* pt_reg_info_tbl declaration
148 * - only for emulated register (either a part or whole bit).
149 * - for passthrough register that need special behavior (like interacting with
150 * other component), set emu_mask to all 0 and specify r/w func properly.
151 * - do NOT use ALL F for init_val, otherwise the tbl will not be registered.
152 */
154 /* Header Type0 reg static infomation table */
155 static struct pt_reg_info_tbl pt_emu_reg_header0_tbl[] = {
156 /* Command reg */
157 {
158 .offset = PCI_COMMAND,
159 .size = 2,
160 .init_val = 0x0000,
161 .ro_mask = 0xF880,
162 .emu_mask = 0x0340,
163 .init = pt_common_reg_init,
164 .u.w.read = pt_word_reg_read,
165 .u.w.write = pt_cmd_reg_write,
166 },
167 /* Capabilities Pointer reg */
168 {
169 .offset = PCI_CAPABILITY_LIST,
170 .size = 1,
171 .init_val = 0x00,
172 .ro_mask = 0xFF,
173 .emu_mask = 0xFF,
174 .init = pt_ptr_reg_init,
175 .u.b.read = pt_byte_reg_read,
176 .u.b.write = pt_byte_reg_write,
177 },
178 /* Status reg */
179 /* use emulated Cap Ptr value to initialize,
180 * so need to be declared after Cap Ptr reg
181 */
182 {
183 .offset = PCI_STATUS,
184 .size = 2,
185 .init_val = 0x0000,
186 .ro_mask = 0x06FF,
187 .emu_mask = 0x0010,
188 .init = pt_status_reg_init,
189 .u.w.read = pt_word_reg_read,
190 .u.w.write = pt_word_reg_write,
191 },
192 /* Cache Line Size reg */
193 {
194 .offset = PCI_CACHE_LINE_SIZE,
195 .size = 1,
196 .init_val = 0x00,
197 .ro_mask = 0x00,
198 .emu_mask = 0xFF,
199 .init = pt_common_reg_init,
200 .u.b.read = pt_byte_reg_read,
201 .u.b.write = pt_byte_reg_write,
202 },
203 /* Latency Timer reg */
204 {
205 .offset = PCI_LATENCY_TIMER,
206 .size = 1,
207 .init_val = 0x00,
208 .ro_mask = 0x00,
209 .emu_mask = 0xFF,
210 .init = pt_common_reg_init,
211 .u.b.read = pt_byte_reg_read,
212 .u.b.write = pt_byte_reg_write,
213 },
214 /* Header Type reg */
215 {
216 .offset = PCI_HEADER_TYPE,
217 .size = 1,
218 .init_val = 0x00,
219 .ro_mask = 0xFF,
220 .emu_mask = 0x80,
221 .init = pt_common_reg_init,
222 .u.b.read = pt_byte_reg_read,
223 .u.b.write = pt_byte_reg_write,
224 },
225 /* Interrupt Line reg */
226 {
227 .offset = PCI_INTERRUPT_LINE,
228 .size = 1,
229 .init_val = 0x00,
230 .ro_mask = 0x00,
231 .emu_mask = 0xFF,
232 .init = pt_common_reg_init,
233 .u.b.read = pt_byte_reg_read,
234 .u.b.write = pt_byte_reg_write,
235 },
236 /* Interrupt Pin reg */
237 {
238 .offset = PCI_INTERRUPT_PIN,
239 .size = 1,
240 .init_val = 0x00,
241 .ro_mask = 0xFF,
242 .emu_mask = 0xFF,
243 .init = pt_irqpin_reg_init,
244 .u.b.read = pt_byte_reg_read,
245 .u.b.write = pt_byte_reg_write,
246 },
247 /* BAR 0 reg */
248 /* mask of BAR need to be decided later, depends on IO/MEM type */
249 {
250 .offset = PCI_BASE_ADDRESS_0,
251 .size = 4,
252 .init_val = 0x00000000,
253 .init = pt_bar_reg_init,
254 .u.dw.read = pt_bar_reg_read,
255 .u.dw.write = pt_bar_reg_write,
256 },
257 /* BAR 1 reg */
258 {
259 .offset = PCI_BASE_ADDRESS_1,
260 .size = 4,
261 .init_val = 0x00000000,
262 .init = pt_bar_reg_init,
263 .u.dw.read = pt_bar_reg_read,
264 .u.dw.write = pt_bar_reg_write,
265 },
266 /* BAR 2 reg */
267 {
268 .offset = PCI_BASE_ADDRESS_2,
269 .size = 4,
270 .init_val = 0x00000000,
271 .init = pt_bar_reg_init,
272 .u.dw.read = pt_bar_reg_read,
273 .u.dw.write = pt_bar_reg_write,
274 },
275 /* BAR 3 reg */
276 {
277 .offset = PCI_BASE_ADDRESS_3,
278 .size = 4,
279 .init_val = 0x00000000,
280 .init = pt_bar_reg_init,
281 .u.dw.read = pt_bar_reg_read,
282 .u.dw.write = pt_bar_reg_write,
283 },
284 /* BAR 4 reg */
285 {
286 .offset = PCI_BASE_ADDRESS_4,
287 .size = 4,
288 .init_val = 0x00000000,
289 .init = pt_bar_reg_init,
290 .u.dw.read = pt_bar_reg_read,
291 .u.dw.write = pt_bar_reg_write,
292 },
293 /* BAR 5 reg */
294 {
295 .offset = PCI_BASE_ADDRESS_5,
296 .size = 4,
297 .init_val = 0x00000000,
298 .init = pt_bar_reg_init,
299 .u.dw.read = pt_bar_reg_read,
300 .u.dw.write = pt_bar_reg_write,
301 },
302 /* Expansion ROM BAR reg */
303 {
304 .offset = PCI_ROM_ADDRESS,
305 .size = 4,
306 .init_val = 0x00000000,
307 .ro_mask = 0x000007FE,
308 .emu_mask = 0xFFFFF800,
309 .init = pt_bar_reg_init,
310 .u.dw.read = pt_long_reg_read,
311 .u.dw.write = pt_exp_rom_bar_reg_write,
312 },
313 {
314 .size = 0,
315 },
316 };
318 /* Power Management Capability reg static infomation table */
319 static struct pt_reg_info_tbl pt_emu_reg_pm_tbl[] = {
320 /* Next Pointer reg */
321 {
322 .offset = PCI_CAP_LIST_NEXT,
323 .size = 1,
324 .init_val = 0x00,
325 .ro_mask = 0xFF,
326 .emu_mask = 0xFF,
327 .init = pt_ptr_reg_init,
328 .u.b.read = pt_byte_reg_read,
329 .u.b.write = pt_byte_reg_write,
330 },
331 /* Power Management Capabilities reg */
332 {
333 .offset = PCI_CAP_FLAGS,
334 .size = 2,
335 .init_val = 0x0000,
336 .ro_mask = 0xFFFF,
337 .emu_mask = 0xFFE8,
338 .init = pt_common_reg_init,
339 .u.w.read = pt_word_reg_read,
340 .u.w.write = pt_word_reg_write,
341 },
342 /* PCI Power Management Control/Status reg */
343 {
344 .offset = PCI_PM_CTRL,
345 .size = 2,
346 .init_val = 0x0008,
347 .ro_mask = 0x60FC,
348 .emu_mask = 0xFF0B,
349 .init = pt_common_reg_init,
350 .u.w.read = pt_word_reg_read,
351 .u.w.write = pt_pmcsr_reg_write,
352 },
353 /* Data reg */
354 {
355 .offset = PCI_PM_DATA_REGISTER,
356 .size = 1,
357 .init_val = 0x00,
358 .ro_mask = 0xFF,
359 .emu_mask = 0xFF,
360 .init = pt_common_reg_init,
361 .u.b.read = pt_byte_reg_read,
362 .u.b.write = pt_byte_reg_write,
363 },
364 {
365 .size = 0,
366 },
367 };
369 /* Vital Product Data Capability Structure reg static infomation table */
370 static struct pt_reg_info_tbl pt_emu_reg_vpd_tbl[] = {
371 /* Next Pointer reg */
372 {
373 .offset = PCI_CAP_LIST_NEXT,
374 .size = 1,
375 .init_val = 0x00,
376 .ro_mask = 0xFF,
377 .emu_mask = 0xFF,
378 .init = pt_ptr_reg_init,
379 .u.b.read = pt_byte_reg_read,
380 .u.b.write = pt_byte_reg_write,
381 },
382 {
383 .size = 0,
384 },
385 };
387 /* Vendor Specific Capability Structure reg static infomation table */
388 static struct pt_reg_info_tbl pt_emu_reg_vendor_tbl[] = {
389 /* Next Pointer reg */
390 {
391 .offset = PCI_CAP_LIST_NEXT,
392 .size = 1,
393 .init_val = 0x00,
394 .ro_mask = 0xFF,
395 .emu_mask = 0xFF,
396 .init = pt_ptr_reg_init,
397 .u.b.read = pt_byte_reg_read,
398 .u.b.write = pt_byte_reg_write,
399 },
400 {
401 .size = 0,
402 },
403 };
405 /* PCI Express Capability Structure reg static infomation table */
406 static struct pt_reg_info_tbl pt_emu_reg_pcie_tbl[] = {
407 /* Next Pointer reg */
408 {
409 .offset = PCI_CAP_LIST_NEXT,
410 .size = 1,
411 .init_val = 0x00,
412 .ro_mask = 0xFF,
413 .emu_mask = 0xFF,
414 .init = pt_ptr_reg_init,
415 .u.b.read = pt_byte_reg_read,
416 .u.b.write = pt_byte_reg_write,
417 },
418 /* Device Capabilities reg */
419 {
420 .offset = PCI_EXP_DEVCAP,
421 .size = 4,
422 .init_val = 0x00000000,
423 .ro_mask = 0x1FFCFFFF,
424 .emu_mask = 0x10000000,
425 .init = pt_common_reg_init,
426 .u.dw.read = pt_long_reg_read,
427 .u.dw.write = pt_long_reg_write,
428 },
429 /* Device Control reg */
430 {
431 .offset = PCI_EXP_DEVCTL,
432 .size = 2,
433 .init_val = 0x2810,
434 .ro_mask = 0x0000,
435 .emu_mask = 0xFFFF,
436 .init = pt_common_reg_init,
437 .u.w.read = pt_word_reg_read,
438 .u.w.write = pt_devctrl_reg_write,
439 },
440 /* Link Control reg */
441 {
442 .offset = PCI_EXP_LNKCTL,
443 .size = 2,
444 .init_val = 0x0000,
445 .ro_mask = 0x0000,
446 .emu_mask = 0xFFFF,
447 .init = pt_linkctrl_reg_init,
448 .u.w.read = pt_word_reg_read,
449 .u.w.write = pt_linkctrl_reg_write,
450 },
451 /* Device Control 2 reg */
452 {
453 .offset = 0x28,
454 .size = 2,
455 .init_val = 0x0000,
456 .ro_mask = 0x0000,
457 .emu_mask = 0xFFFF,
458 .init = pt_devctrl2_reg_init,
459 .u.w.read = pt_word_reg_read,
460 .u.w.write = pt_devctrl2_reg_write,
461 },
462 /* Link Control 2 reg */
463 {
464 .offset = 0x30,
465 .size = 2,
466 .init_val = 0x0000,
467 .ro_mask = 0x0000,
468 .emu_mask = 0xFFFF,
469 .init = pt_linkctrl2_reg_init,
470 .u.w.read = pt_word_reg_read,
471 .u.w.write = pt_linkctrl2_reg_write,
472 },
473 {
474 .size = 0,
475 },
476 };
478 /* MSI Capability Structure reg static infomation table */
479 static struct pt_reg_info_tbl pt_emu_reg_msi_tbl[] = {
480 /* Next Pointer reg */
481 {
482 .offset = PCI_CAP_LIST_NEXT,
483 .size = 1,
484 .init_val = 0x00,
485 .ro_mask = 0xFF,
486 .emu_mask = 0xFF,
487 .init = pt_ptr_reg_init,
488 .u.b.read = pt_byte_reg_read,
489 .u.b.write = pt_byte_reg_write,
490 },
491 /* Message Control reg */
492 {
493 .offset = PCI_MSI_FLAGS, // 2
494 .size = 2,
495 .init_val = 0x0000,
496 .ro_mask = 0x018E,
497 .emu_mask = 0xFFFE,
498 .init = pt_msgctrl_reg_init,
499 .u.w.read = pt_word_reg_read,
500 .u.w.write = pt_msgctrl_reg_write,
501 },
502 /* Message Address reg */
503 {
504 .offset = PCI_MSI_ADDRESS_LO, // 4
505 .size = 4,
506 .init_val = 0x00000000,
507 .ro_mask = 0x00000FF0, /* bit 4~11 is reserved for MSI in x86 */
508 .emu_mask = 0xFFFFFFFF,
509 .init = pt_msgaddr32_reg_init,
510 .u.dw.read = pt_long_reg_read,
511 .u.dw.write = pt_msgaddr32_reg_write,
512 },
513 /* Message Upper Address reg (if PCI_MSI_FLAGS_64BIT set) */
514 {
515 .offset = PCI_MSI_ADDRESS_HI, // 8
516 .size = 4,
517 .init_val = 0x00000000,
518 .ro_mask = 0x00000000,
519 .emu_mask = 0xFFFFFFFF,
520 .init = pt_msgaddr64_reg_init,
521 .u.dw.read = pt_long_reg_read,
522 .u.dw.write = pt_msgaddr64_reg_write,
523 },
524 /* Message Data reg (16 bits of data for 32-bit devices) */
525 {
526 .offset = PCI_MSI_DATA_32, // 8
527 .size = 2,
528 .init_val = 0x0000,
529 .ro_mask = 0x3800,
530 .emu_mask = 0xFFFF,
531 .init = pt_msgdata_reg_init,
532 .u.w.read = pt_word_reg_read,
533 .u.w.write = pt_msgdata_reg_write,
534 },
535 /* Message Data reg (16 bits of data for 64-bit devices) */
536 {
537 .offset = PCI_MSI_DATA_64, // 12
538 .size = 2,
539 .init_val = 0x0000,
540 .ro_mask = 0x3800,
541 .emu_mask = 0xFFFF,
542 .init = pt_msgdata_reg_init,
543 .u.w.read = pt_word_reg_read,
544 .u.w.write = pt_msgdata_reg_write,
545 },
546 {
547 .size = 0,
548 },
549 };
551 /* MSI-X Capability Structure reg static infomation table */
552 static struct pt_reg_info_tbl pt_emu_reg_msix_tbl[] = {
553 /* Next Pointer reg */
554 {
555 .offset = PCI_CAP_LIST_NEXT,
556 .size = 1,
557 .init_val = 0x00,
558 .ro_mask = 0xFF,
559 .emu_mask = 0xFF,
560 .init = pt_ptr_reg_init,
561 .u.b.read = pt_byte_reg_read,
562 .u.b.write = pt_byte_reg_write,
563 },
564 /* Message Control reg */
565 {
566 .offset = PCI_MSI_FLAGS, // 2
567 .size = 2,
568 .init_val = 0x0000,
569 .ro_mask = 0x3FFF,
570 .emu_mask = 0x0000,
571 .init = pt_msixctrl_reg_init,
572 .u.w.read = pt_word_reg_read,
573 .u.w.write = pt_msixctrl_reg_write,
574 },
575 {
576 .size = 0,
577 },
578 };
580 /* pt_reg_grp_info_tbl declaration
581 * - only for emulated or zero-hardwired register group.
582 * - for register group with dynamic size, just set grp_size to 0xFF and
583 * specify size_init func properly.
584 * - no need to specify emu_reg_tbl for zero-hardwired type.
585 */
587 /* emul reg group static infomation table */
588 static const struct pt_reg_grp_info_tbl pt_emu_reg_grp_tbl[] = {
589 /* Header Type0 reg group */
590 {
591 .grp_id = 0xFF,
592 .grp_type = GRP_TYPE_EMU,
593 .grp_size = 0x40,
594 .size_init = pt_reg_grp_size_init,
595 .emu_reg_tbl= pt_emu_reg_header0_tbl,
596 },
597 /* PCI PowerManagement Capability reg group */
598 {
599 .grp_id = PCI_CAP_ID_PM,
600 .grp_type = GRP_TYPE_EMU,
601 .grp_size = PCI_PM_SIZEOF,
602 .size_init = pt_reg_grp_size_init,
603 .emu_reg_tbl= pt_emu_reg_pm_tbl,
604 },
605 /* AGP Capability Structure reg group */
606 {
607 .grp_id = PCI_CAP_ID_AGP,
608 .grp_type = GRP_TYPE_HARDWIRED,
609 .grp_size = 0x30,
610 .size_init = pt_reg_grp_size_init,
611 },
612 /* Vital Product Data Capability Structure reg group */
613 {
614 .grp_id = PCI_CAP_ID_VPD,
615 .grp_type = GRP_TYPE_EMU,
616 .grp_size = 0x08,
617 .size_init = pt_reg_grp_size_init,
618 .emu_reg_tbl= pt_emu_reg_vpd_tbl,
619 },
620 /* Slot Identification reg group */
621 {
622 .grp_id = PCI_CAP_ID_SLOTID,
623 .grp_type = GRP_TYPE_HARDWIRED,
624 .grp_size = 0x04,
625 .size_init = pt_reg_grp_size_init,
626 },
627 /* MSI Capability Structure reg group */
628 {
629 .grp_id = PCI_CAP_ID_MSI,
630 .grp_type = GRP_TYPE_EMU,
631 .grp_size = 0xFF,
632 .size_init = pt_msi_size_init,
633 .emu_reg_tbl= pt_emu_reg_msi_tbl,
634 },
635 /* PCI-X Capabilities List Item reg group */
636 {
637 .grp_id = PCI_CAP_ID_PCIX,
638 .grp_type = GRP_TYPE_HARDWIRED,
639 .grp_size = 0x18,
640 .size_init = pt_reg_grp_size_init,
641 },
642 /* Vendor Specific Capability Structure reg group */
643 {
644 .grp_id = PCI_CAP_ID_VNDR,
645 .grp_type = GRP_TYPE_EMU,
646 .grp_size = 0xFF,
647 .size_init = pt_vendor_size_init,
648 .emu_reg_tbl= pt_emu_reg_vendor_tbl,
649 },
650 /* SHPC Capability List Item reg group */
651 {
652 .grp_id = PCI_CAP_ID_HOTPLUG,
653 .grp_type = GRP_TYPE_HARDWIRED,
654 .grp_size = 0x08,
655 .size_init = pt_reg_grp_size_init,
656 },
657 /* Subsystem ID and Subsystem Vendor ID Capability List Item reg group */
658 {
659 .grp_id = PCI_CAP_ID_SSVID,
660 .grp_type = GRP_TYPE_HARDWIRED,
661 .grp_size = 0x08,
662 .size_init = pt_reg_grp_size_init,
663 },
664 /* AGP 8x Capability Structure reg group */
665 {
666 .grp_id = PCI_CAP_ID_AGP3,
667 .grp_type = GRP_TYPE_HARDWIRED,
668 .grp_size = 0x30,
669 .size_init = pt_reg_grp_size_init,
670 },
671 /* PCI Express Capability Structure reg group */
672 {
673 .grp_id = PCI_CAP_ID_EXP,
674 .grp_type = GRP_TYPE_EMU,
675 .grp_size = 0xFF,
676 .size_init = pt_pcie_size_init,
677 .emu_reg_tbl= pt_emu_reg_pcie_tbl,
678 },
679 /* MSI-X Capability Structure reg group */
680 {
681 .grp_id = PCI_CAP_ID_MSIX,
682 .grp_type = GRP_TYPE_EMU,
683 .grp_size = 0x0C,
684 .size_init = pt_msix_size_init,
685 .emu_reg_tbl= pt_emu_reg_msix_tbl,
686 },
687 {
688 .grp_size = 0,
689 },
690 };
692 static int token_value(char *token)
693 {
694 return strtol(token, NULL, 16);
695 }
697 static int next_bdf(char **str, int *seg, int *bus, int *dev, int *func)
698 {
699 char *token, *delim = ":.-";
701 if ( !(*str) ||
702 ( !strchr(*str, ':') && !strchr(*str, '.')) )
703 return 0;
705 token = strsep(str, delim);
706 *seg = token_value(token);
708 token = strsep(str, delim);
709 *bus = token_value(token);
711 token = strsep(str, delim);
712 *dev = token_value(token);
714 token = strsep(str, delim);
715 *func = token_value(token);
717 return 1;
718 }
720 /* Insert a new pass-through device into a specific pci slot.
721 * input dom:bus:dev.func@slot, chose free one if slot == 0
722 * return -1: required slot not available
723 * 0: no free hotplug slots, but normal slot should okay
724 * >0: the new hotplug slot
725 */
726 static int __insert_to_pci_slot(int bus, int dev, int func, int slot)
727 {
728 int i, php_slot;
730 /* preferred virt pci slot */
731 if ( slot >= PHP_SLOT_START && slot < PHP_SLOT_END )
732 {
733 php_slot = PCI_TO_PHP_SLOT(slot);
734 if ( !dpci_infos.php_devs[php_slot].valid )
735 {
736 goto found;
737 }
738 else
739 return -1;
740 }
742 if ( slot != 0 )
743 return -1;
745 /* slot == 0, pick up a free one */
746 for ( i = 0; i < PHP_SLOT_LEN; i++ )
747 {
748 if ( !dpci_infos.php_devs[i].valid )
749 {
750 php_slot = i;
751 goto found;
752 }
753 }
755 /* not found */
756 return 0;
758 found:
759 dpci_infos.php_devs[php_slot].valid = 1;
760 dpci_infos.php_devs[php_slot].r_bus = bus;
761 dpci_infos.php_devs[php_slot].r_dev = dev;
762 dpci_infos.php_devs[php_slot].r_func = func;
763 return PHP_TO_PCI_SLOT(php_slot);
764 }
766 /* Insert a new pass-through device into a specific pci slot.
767 * input dom:bus:dev.func@slot
768 */
769 int insert_to_pci_slot(char *bdf_slt)
770 {
771 int seg, bus, dev, func, slot;
772 char *bdf_str, *slt_str, *delim="@";
774 bdf_str = strsep(&bdf_slt, delim);
775 slt_str = bdf_slt;
776 slot = token_value(slt_str);
778 if ( !next_bdf(&bdf_str, &seg, &bus, &dev, &func))
779 {
780 return -1;
781 }
783 return __insert_to_pci_slot(bus, dev, func, slot);
785 }
787 /* Test if a pci slot has a device
788 * 1: present
789 * 0: not present
790 * -1: invalide pci slot input
791 */
792 int test_pci_slot(int slot)
793 {
794 int php_slot;
796 if ( slot < PHP_SLOT_START || slot >= PHP_SLOT_END )
797 return -1;
799 php_slot = PCI_TO_PHP_SLOT(slot);
800 if ( dpci_infos.php_devs[php_slot].valid )
801 return 1;
802 else
803 return 0;
804 }
806 /* find the pci slot for pass-through dev with specified BDF */
807 int bdf_to_slot(char *bdf_str)
808 {
809 int seg, bus, dev, func, i;
811 if ( !next_bdf(&bdf_str, &seg, &bus, &dev, &func))
812 {
813 return -1;
814 }
816 /* locate the virtual pci slot for this VTd device */
817 for ( i = 0; i < PHP_SLOT_LEN; i++ )
818 {
819 if ( dpci_infos.php_devs[i].valid &&
820 dpci_infos.php_devs[i].r_bus == bus &&
821 dpci_infos.php_devs[i].r_dev == dev &&
822 dpci_infos.php_devs[i].r_func == func )
823 {
824 return PHP_TO_PCI_SLOT(i);
825 }
826 }
828 return -1;
829 }
831 /* Being called each time a mmio region has been updated */
832 void pt_iomem_map(PCIDevice *d, int i, uint32_t e_phys, uint32_t e_size,
833 int type)
834 {
835 struct pt_dev *assigned_device = (struct pt_dev *)d;
836 uint32_t old_ebase = assigned_device->bases[i].e_physbase;
837 int first_map = ( assigned_device->bases[i].e_size == 0 );
838 int ret = 0;
840 assigned_device->bases[i].e_physbase = e_phys;
841 assigned_device->bases[i].e_size= e_size;
843 PT_LOG("e_phys=%08x maddr=%lx type=%d len=%d index=%d first_map=%d\n",
844 e_phys, (unsigned long)assigned_device->bases[i].access.maddr,
845 type, e_size, i, first_map);
847 if ( e_size == 0 )
848 return;
850 if ( !first_map && old_ebase != -1 )
851 {
852 add_msix_mapping(assigned_device, i);
853 /* Remove old mapping */
854 ret = xc_domain_memory_mapping(xc_handle, domid,
855 old_ebase >> XC_PAGE_SHIFT,
856 assigned_device->bases[i].access.maddr >> XC_PAGE_SHIFT,
857 (e_size+XC_PAGE_SIZE-1) >> XC_PAGE_SHIFT,
858 DPCI_REMOVE_MAPPING);
859 if ( ret != 0 )
860 {
861 PT_LOG("Error: remove old mapping failed!\n");
862 return;
863 }
864 }
866 /* map only valid guest address */
867 if (e_phys != -1)
868 {
869 /* Create new mapping */
870 ret = xc_domain_memory_mapping(xc_handle, domid,
871 assigned_device->bases[i].e_physbase >> XC_PAGE_SHIFT,
872 assigned_device->bases[i].access.maddr >> XC_PAGE_SHIFT,
873 (e_size+XC_PAGE_SIZE-1) >> XC_PAGE_SHIFT,
874 DPCI_ADD_MAPPING);
876 if ( ret != 0 )
877 {
878 PT_LOG("Error: create new mapping failed!\n");
879 }
881 ret = remove_msix_mapping(assigned_device, i);
882 if ( ret != 0 )
883 PT_LOG("Error: remove MSI-X mmio mapping failed!\n");
884 }
885 }
887 /* Being called each time a pio region has been updated */
888 void pt_ioport_map(PCIDevice *d, int i,
889 uint32_t e_phys, uint32_t e_size, int type)
890 {
891 struct pt_dev *assigned_device = (struct pt_dev *)d;
892 uint32_t old_ebase = assigned_device->bases[i].e_physbase;
893 int first_map = ( assigned_device->bases[i].e_size == 0 );
894 int ret = 0;
896 assigned_device->bases[i].e_physbase = e_phys;
897 assigned_device->bases[i].e_size= e_size;
899 PT_LOG("e_phys=%04x pio_base=%04x len=%d index=%d first_map=%d\n",
900 (uint16_t)e_phys, (uint16_t)assigned_device->bases[i].access.pio_base,
901 (uint16_t)e_size, i, first_map);
903 if ( e_size == 0 )
904 return;
906 if ( !first_map && old_ebase != -1 )
907 {
908 /* Remove old mapping */
909 ret = xc_domain_ioport_mapping(xc_handle, domid, old_ebase,
910 assigned_device->bases[i].access.pio_base, e_size,
911 DPCI_REMOVE_MAPPING);
912 if ( ret != 0 )
913 {
914 PT_LOG("Error: remove old mapping failed!\n");
915 return;
916 }
917 }
919 /* map only valid guest address (include 0) */
920 if (e_phys != -1)
921 {
922 /* Create new mapping */
923 ret = xc_domain_ioport_mapping(xc_handle, domid, e_phys,
924 assigned_device->bases[i].access.pio_base, e_size,
925 DPCI_ADD_MAPPING);
926 if ( ret != 0 )
927 {
928 PT_LOG("Error: create new mapping failed!\n");
929 }
930 }
931 }
933 /* find emulate register group entry */
934 struct pt_reg_grp_tbl* pt_find_reg_grp(
935 struct pt_dev *ptdev, uint32_t address)
936 {
937 struct pt_reg_grp_tbl* reg_grp_entry = NULL;
939 /* find register group entry */
940 for (reg_grp_entry = ptdev->reg_grp_tbl_head.lh_first; reg_grp_entry;
941 reg_grp_entry = reg_grp_entry->entries.le_next)
942 {
943 /* check address */
944 if ((reg_grp_entry->base_offset <= address) &&
945 ((reg_grp_entry->base_offset + reg_grp_entry->size) > address))
946 goto out;
947 }
948 /* group entry not found */
949 reg_grp_entry = NULL;
951 out:
952 return reg_grp_entry;
953 }
955 /* find emulate register entry */
956 struct pt_reg_tbl* pt_find_reg(
957 struct pt_reg_grp_tbl* reg_grp, uint32_t address)
958 {
959 struct pt_reg_tbl* reg_entry = NULL;
960 struct pt_reg_info_tbl* reg = NULL;
961 uint32_t real_offset = 0;
963 /* find register entry */
964 for (reg_entry = reg_grp->reg_tbl_head.lh_first; reg_entry;
965 reg_entry = reg_entry->entries.le_next)
966 {
967 reg = reg_entry->reg;
968 real_offset = (reg_grp->base_offset + reg->offset);
969 /* check address */
970 if ((real_offset <= address) && ((real_offset + reg->size) > address))
971 goto out;
972 }
973 /* register entry not found */
974 reg_entry = NULL;
976 out:
977 return reg_entry;
978 }
980 /* get BAR index */
981 static int pt_bar_offset_to_index(uint32_t offset)
982 {
983 int index = 0;
985 /* check Exp ROM BAR */
986 if (offset == PCI_ROM_ADDRESS)
987 {
988 index = PCI_ROM_SLOT;
989 goto out;
990 }
992 /* calculate BAR index */
993 index = ((offset - PCI_BASE_ADDRESS_0) >> 2);
994 if (index >= PCI_NUM_REGIONS)
995 index = -1;
997 out:
998 return index;
999 }
1001 static void pt_pci_write_config(PCIDevice *d, uint32_t address, uint32_t val,
1002 int len)
1004 struct pt_dev *assigned_device = (struct pt_dev *)d;
1005 struct pci_dev *pci_dev = assigned_device->pci_dev;
1006 struct pt_reg_grp_tbl *reg_grp_entry = NULL;
1007 struct pt_reg_grp_info_tbl *reg_grp = NULL;
1008 struct pt_reg_tbl *reg_entry = NULL;
1009 struct pt_reg_info_tbl *reg = NULL;
1010 uint32_t find_addr = address;
1011 uint32_t real_offset = 0;
1012 uint32_t valid_mask = 0xFFFFFFFF;
1013 uint32_t read_val = 0;
1014 uint8_t *ptr_val = NULL;
1015 int emul_len = 0;
1016 int index = 0;
1017 int ret = 0;
1019 #ifdef PT_DEBUG_PCI_CONFIG_ACCESS
1020 PT_LOG("[%02x:%02x.%x]: address=%04x val=0x%08x len=%d\n",
1021 pci_bus_num(d->bus), (d->devfn >> 3) & 0x1F, (d->devfn & 0x7),
1022 address, val, len);
1023 #endif
1025 /* check offset range */
1026 if (address >= 0xFF)
1028 PT_LOG("Failed to write register with offset exceeding FFh. "
1029 "[%02x:%02x.%x][Offset:%02xh][Length:%d]\n",
1030 pci_bus_num(d->bus), ((d->devfn >> 3) & 0x1F), (d->devfn & 0x7),
1031 address, len);
1032 goto exit;
1035 /* check write size */
1036 if ((len != 1) && (len != 2) && (len != 4))
1038 PT_LOG("Failed to write register with invalid access length. "
1039 "[%02x:%02x.%x][Offset:%02xh][Length:%d]\n",
1040 pci_bus_num(d->bus), ((d->devfn >> 3) & 0x1F), (d->devfn & 0x7),
1041 address, len);
1042 goto exit;
1045 /* check offset alignment */
1046 if (address & (len-1))
1048 PT_LOG("Failed to write register with invalid access size alignment. "
1049 "[%02x:%02x.%x][Offset:%02xh][Length:%d]\n",
1050 pci_bus_num(d->bus), ((d->devfn >> 3) & 0x1F), (d->devfn & 0x7),
1051 address, len);
1052 goto exit;
1055 /* check unused BAR register */
1056 index = pt_bar_offset_to_index(address);
1057 if ((index >= 0) && (val > 0 && val < PT_BAR_ALLF) &&
1058 (assigned_device->bases[index].bar_flag == PT_BAR_FLAG_UNUSED))
1060 PT_LOG("Guest attempt to set address to unused Base Address Register. "
1061 "[%02x:%02x.%x][Offset:%02xh][Length:%d]\n",
1062 pci_bus_num(d->bus), ((d->devfn >> 3) & 0x1F),
1063 (d->devfn & 0x7), address, len);
1066 /* find register group entry */
1067 reg_grp_entry = pt_find_reg_grp(assigned_device, address);
1068 if (reg_grp_entry)
1070 reg_grp = reg_grp_entry->reg_grp;
1071 /* check 0 Hardwired register group */
1072 if (reg_grp->grp_type == GRP_TYPE_HARDWIRED)
1074 /* ignore silently */
1075 PT_LOG("Access to 0 Hardwired register. "
1076 "[%02x:%02x.%x][Offset:%02xh][Length:%d]\n",
1077 pci_bus_num(d->bus), ((d->devfn >> 3) & 0x1F),
1078 (d->devfn & 0x7), address, len);
1079 goto exit;
1083 /* read I/O device register value */
1084 switch (len) {
1085 case 1:
1086 read_val = pci_read_byte(pci_dev, address);
1087 break;
1088 case 2:
1089 read_val = pci_read_word(pci_dev, address);
1090 break;
1091 case 4:
1092 read_val = pci_read_long(pci_dev, address);
1093 break;
1096 /* check libpci result */
1097 valid_mask = (0xFFFFFFFF >> ((4 - len) << 3));
1098 if ((read_val & valid_mask) == valid_mask)
1100 PT_LOG("Warning: Return ALL F from libpci read. "
1101 "[%02x:%02x.%x][Offset:%02xh][Length:%d]\n",
1102 pci_bus_num(d->bus), ((d->devfn >> 3) & 0x1F), (d->devfn & 0x7),
1103 address, len);
1106 /* pass directly to libpci for passthrough type register group */
1107 if (reg_grp_entry == NULL)
1108 goto out;
1110 /* adjust the read and write value to appropriate CFC-CFF window */
1111 read_val <<= ((address & 3) << 3);
1112 val <<= ((address & 3) << 3);
1113 emul_len = len;
1115 /* loop Guest request size */
1116 while (0 < emul_len)
1118 /* find register entry to be emulated */
1119 reg_entry = pt_find_reg(reg_grp_entry, find_addr);
1120 if (reg_entry)
1122 reg = reg_entry->reg;
1123 real_offset = (reg_grp_entry->base_offset + reg->offset);
1124 valid_mask = (0xFFFFFFFF >> ((4 - emul_len) << 3));
1125 valid_mask <<= ((find_addr - real_offset) << 3);
1126 ptr_val = ((uint8_t *)&val + (real_offset & 3));
1128 /* do emulation depend on register size */
1129 switch (reg->size) {
1130 case 1:
1131 /* emulate write to byte register */
1132 if (reg->u.b.write)
1133 ret = reg->u.b.write(assigned_device, reg_entry,
1134 (uint8_t *)ptr_val,
1135 (uint8_t)(read_val >> ((real_offset & 3) << 3)),
1136 (uint8_t)valid_mask);
1137 break;
1138 case 2:
1139 /* emulate write to word register */
1140 if (reg->u.w.write)
1141 ret = reg->u.w.write(assigned_device, reg_entry,
1142 (uint16_t *)ptr_val,
1143 (uint16_t)(read_val >> ((real_offset & 3) << 3)),
1144 (uint16_t)valid_mask);
1145 break;
1146 case 4:
1147 /* emulate write to double word register */
1148 if (reg->u.dw.write)
1149 ret = reg->u.dw.write(assigned_device, reg_entry,
1150 (uint32_t *)ptr_val,
1151 (uint32_t)(read_val >> ((real_offset & 3) << 3)),
1152 (uint32_t)valid_mask);
1153 break;
1156 /* write emulation error */
1157 if (ret < 0)
1159 /* exit I/O emulator */
1160 PT_LOG("Internal error: Invalid write emulation "
1161 "return value[%d]. I/O emulator exit.\n", ret);
1162 exit(1);
1165 /* calculate next address to find */
1166 emul_len -= reg->size;
1167 if (emul_len > 0)
1168 find_addr = real_offset + reg->size;
1170 else
1172 /* nothing to do with passthrough type register,
1173 * continue to find next byte
1174 */
1175 emul_len--;
1176 find_addr++;
1180 /* need to shift back before passing them to libpci */
1181 val >>= ((address & 3) << 3);
1183 out:
1184 switch (len){
1185 case 1:
1186 pci_write_byte(pci_dev, address, val);
1187 break;
1188 case 2:
1189 pci_write_word(pci_dev, address, val);
1190 break;
1191 case 4:
1192 pci_write_long(pci_dev, address, val);
1193 break;
1196 exit:
1197 return;
1200 static uint32_t pt_pci_read_config(PCIDevice *d, uint32_t address, int len)
1202 struct pt_dev *assigned_device = (struct pt_dev *)d;
1203 struct pci_dev *pci_dev = assigned_device->pci_dev;
1204 uint32_t val = 0xFFFFFFFF;
1205 struct pt_reg_grp_tbl *reg_grp_entry = NULL;
1206 struct pt_reg_grp_info_tbl *reg_grp = NULL;
1207 struct pt_reg_tbl *reg_entry = NULL;
1208 struct pt_reg_info_tbl *reg = NULL;
1209 uint32_t find_addr = address;
1210 uint32_t real_offset = 0;
1211 uint32_t valid_mask = 0xFFFFFFFF;
1212 uint8_t *ptr_val = NULL;
1213 int emul_len = 0;
1214 int ret = 0;
1216 /* check offset range */
1217 if (address >= 0xFF)
1219 PT_LOG("Failed to read register with offset exceeding FFh. "
1220 "[%02x:%02x.%x][Offset:%02xh][Length:%d]\n",
1221 pci_bus_num(d->bus), ((d->devfn >> 3) & 0x1F), (d->devfn & 0x7),
1222 address, len);
1223 goto exit;
1226 /* check read size */
1227 if ((len != 1) && (len != 2) && (len != 4))
1229 PT_LOG("Failed to read register with invalid access length. "
1230 "[%02x:%02x.%x][Offset:%02xh][Length:%d]\n",
1231 pci_bus_num(d->bus), ((d->devfn >> 3) & 0x1F), (d->devfn & 0x7),
1232 address, len);
1233 goto exit;
1236 /* check offset alignment */
1237 if (address & (len-1))
1239 PT_LOG("Failed to read register with invalid access size alignment. "
1240 "[%02x:%02x.%x][Offset:%02xh][Length:%d]\n",
1241 pci_bus_num(d->bus), ((d->devfn >> 3) & 0x1F), (d->devfn & 0x7),
1242 address, len);
1243 goto exit;
1246 /* find register group entry */
1247 reg_grp_entry = pt_find_reg_grp(assigned_device, address);
1248 if (reg_grp_entry)
1250 reg_grp = reg_grp_entry->reg_grp;
1251 /* check 0 Hardwired register group */
1252 if (reg_grp->grp_type == GRP_TYPE_HARDWIRED)
1254 /* no need to emulate, just return 0 */
1255 val = 0;
1256 goto exit;
1260 /* read I/O device register value */
1261 switch (len) {
1262 case 1:
1263 val = pci_read_byte(pci_dev, address);
1264 break;
1265 case 2:
1266 val = pci_read_word(pci_dev, address);
1267 break;
1268 case 4:
1269 val = pci_read_long(pci_dev, address);
1270 break;
1273 /* check libpci result */
1274 valid_mask = (0xFFFFFFFF >> ((4 - len) << 3));
1275 if ((val & valid_mask) == valid_mask)
1277 PT_LOG("Warning: Return ALL F from libpci read. "
1278 "[%02x:%02x.%x][Offset:%02xh][Length:%d]\n",
1279 pci_bus_num(d->bus), ((d->devfn >> 3) & 0x1F), (d->devfn & 0x7),
1280 address, len);
1283 /* just return the I/O device register value for
1284 * passthrough type register group
1285 */
1286 if (reg_grp_entry == NULL)
1287 goto exit;
1289 /* adjust the read value to appropriate CFC-CFF window */
1290 val <<= ((address & 3) << 3);
1291 emul_len = len;
1293 /* loop Guest request size */
1294 while (0 < emul_len)
1296 /* find register entry to be emulated */
1297 reg_entry = pt_find_reg(reg_grp_entry, find_addr);
1298 if (reg_entry)
1300 reg = reg_entry->reg;
1301 real_offset = (reg_grp_entry->base_offset + reg->offset);
1302 valid_mask = (0xFFFFFFFF >> ((4 - emul_len) << 3));
1303 valid_mask <<= ((find_addr - real_offset) << 3);
1304 ptr_val = ((uint8_t *)&val + (real_offset & 3));
1306 /* do emulation depend on register size */
1307 switch (reg->size) {
1308 case 1:
1309 /* emulate read to byte register */
1310 if (reg->u.b.read)
1311 ret = reg->u.b.read(assigned_device, reg_entry,
1312 (uint8_t *)ptr_val,
1313 (uint8_t)valid_mask);
1314 break;
1315 case 2:
1316 /* emulate read to word register */
1317 if (reg->u.w.read)
1318 ret = reg->u.w.read(assigned_device, reg_entry,
1319 (uint16_t *)ptr_val,
1320 (uint16_t)valid_mask);
1321 break;
1322 case 4:
1323 /* emulate read to double word register */
1324 if (reg->u.dw.read)
1325 ret = reg->u.dw.read(assigned_device, reg_entry,
1326 (uint32_t *)ptr_val,
1327 (uint32_t)valid_mask);
1328 break;
1331 /* read emulation error */
1332 if (ret < 0)
1334 /* exit I/O emulator */
1335 PT_LOG("Internal error: Invalid read emulation "
1336 "return value[%d]. I/O emulator exit.\n", ret);
1337 exit(1);
1340 /* calculate next address to find */
1341 emul_len -= reg->size;
1342 if (emul_len > 0)
1343 find_addr = real_offset + reg->size;
1345 else
1347 /* nothing to do with passthrough type register,
1348 * continue to find next byte
1349 */
1350 emul_len--;
1351 find_addr++;
1355 /* need to shift back before returning them to pci bus emulator */
1356 val >>= ((address & 3) << 3);
1358 exit:
1360 #ifdef PT_DEBUG_PCI_CONFIG_ACCESS
1361 PT_LOG("[%02x:%02x.%x]: address=%04x val=0x%08x len=%d\n",
1362 pci_bus_num(d->bus), (d->devfn >> 3) & 0x1F, (d->devfn & 0x7),
1363 address, val, len);
1364 #endif
1366 return val;
1369 static int pt_register_regions(struct pt_dev *assigned_device)
1371 int i = 0;
1372 uint32_t bar_data = 0;
1373 struct pci_dev *pci_dev = assigned_device->pci_dev;
1374 PCIDevice *d = &assigned_device->dev;
1376 /* Register PIO/MMIO BARs */
1377 for ( i = 0; i < PCI_BAR_ENTRIES; i++ )
1379 if ( pci_dev->base_addr[i] )
1381 assigned_device->bases[i].e_physbase = pci_dev->base_addr[i];
1382 assigned_device->bases[i].access.u = pci_dev->base_addr[i];
1384 /* Register current region */
1385 bar_data = *((uint32_t*)(d->config + PCI_BASE_ADDRESS_0) + i);
1386 if ( bar_data & PCI_ADDRESS_SPACE_IO )
1387 pci_register_io_region((PCIDevice *)assigned_device, i,
1388 (uint32_t)pci_dev->size[i], PCI_ADDRESS_SPACE_IO,
1389 pt_ioport_map);
1390 else if ( bar_data & PCI_ADDRESS_SPACE_MEM_PREFETCH )
1391 pci_register_io_region((PCIDevice *)assigned_device, i,
1392 (uint32_t)pci_dev->size[i], PCI_ADDRESS_SPACE_MEM_PREFETCH,
1393 pt_iomem_map);
1394 else
1395 pci_register_io_region((PCIDevice *)assigned_device, i,
1396 (uint32_t)pci_dev->size[i], PCI_ADDRESS_SPACE_MEM,
1397 pt_iomem_map);
1399 PT_LOG("IO region registered (size=0x%08x base_addr=0x%08x)\n",
1400 (uint32_t)(pci_dev->size[i]),
1401 (uint32_t)(pci_dev->base_addr[i]));
1405 /* Register expansion ROM address */
1406 if ( pci_dev->rom_base_addr && pci_dev->rom_size )
1408 assigned_device->bases[PCI_ROM_SLOT].e_physbase =
1409 pci_dev->rom_base_addr;
1410 assigned_device->bases[PCI_ROM_SLOT].access.maddr =
1411 pci_dev->rom_base_addr;
1412 pci_register_io_region((PCIDevice *)assigned_device, PCI_ROM_SLOT,
1413 pci_dev->rom_size, PCI_ADDRESS_SPACE_MEM_PREFETCH,
1414 pt_iomem_map);
1416 PT_LOG("Expansion ROM registered (size=0x%08x base_addr=0x%08x)\n",
1417 (uint32_t)(pci_dev->rom_size), (uint32_t)(pci_dev->rom_base_addr));
1420 return 0;
1423 static void pt_unregister_regions(struct pt_dev *assigned_device)
1425 int i, type, ret;
1426 uint32_t e_size;
1427 PCIDevice *d = (PCIDevice*)assigned_device;
1429 for ( i = 0; i < PCI_NUM_REGIONS; i++ )
1431 e_size = assigned_device->bases[i].e_size;
1432 if ( (e_size == 0) || (assigned_device->bases[i].e_physbase == -1) )
1433 continue;
1435 type = d->io_regions[i].type;
1437 if ( type == PCI_ADDRESS_SPACE_MEM ||
1438 type == PCI_ADDRESS_SPACE_MEM_PREFETCH )
1440 ret = xc_domain_memory_mapping(xc_handle, domid,
1441 assigned_device->bases[i].e_physbase >> XC_PAGE_SHIFT,
1442 assigned_device->bases[i].access.maddr >> XC_PAGE_SHIFT,
1443 (e_size+XC_PAGE_SIZE-1) >> XC_PAGE_SHIFT,
1444 DPCI_REMOVE_MAPPING);
1445 if ( ret != 0 )
1447 PT_LOG("Error: remove old mem mapping failed!\n");
1448 continue;
1452 else if ( type == PCI_ADDRESS_SPACE_IO )
1454 ret = xc_domain_ioport_mapping(xc_handle, domid,
1455 assigned_device->bases[i].e_physbase,
1456 assigned_device->bases[i].access.pio_base,
1457 e_size,
1458 DPCI_REMOVE_MAPPING);
1459 if ( ret != 0 )
1461 PT_LOG("Error: remove old io mapping failed!\n");
1462 continue;
1471 uint8_t find_cap_offset(struct pci_dev *pci_dev, uint8_t cap)
1473 int id;
1474 int max_cap = 48;
1475 int pos = PCI_CAPABILITY_LIST;
1476 int status;
1478 status = pci_read_byte(pci_dev, PCI_STATUS);
1479 if ( (status & PCI_STATUS_CAP_LIST) == 0 )
1480 return 0;
1482 while ( max_cap-- )
1484 pos = pci_read_byte(pci_dev, pos);
1485 if ( pos < 0x40 )
1486 break;
1488 pos &= ~3;
1489 id = pci_read_byte(pci_dev, pos + PCI_CAP_LIST_ID);
1491 if ( id == 0xff )
1492 break;
1493 if ( id == cap )
1494 return pos;
1496 pos += PCI_CAP_LIST_NEXT;
1498 return 0;
1501 /* parse BAR */
1502 static int pt_bar_reg_parse(
1503 struct pt_dev *ptdev, struct pt_reg_info_tbl *reg)
1505 PCIDevice *d = &ptdev->dev;
1506 struct pt_region *region = NULL;
1507 PCIIORegion *r;
1508 uint32_t bar_64 = (reg->offset - 4);
1509 int bar_flag = PT_BAR_FLAG_UNUSED;
1510 int index = 0;
1511 int i;
1513 /* set again the BAR config because it has been overwritten
1514 * by pci_register_io_region()
1515 */
1516 for (i=reg->offset; i<(reg->offset + 4); i++)
1517 d->config[i] = pci_read_byte(ptdev->pci_dev, i);
1519 /* check 64bit BAR */
1520 index = pt_bar_offset_to_index(reg->offset);
1521 if ((index > 0) && (index < PCI_ROM_SLOT) &&
1522 ((d->config[bar_64] & (PCI_BASE_ADDRESS_SPACE |
1523 PCI_BASE_ADDRESS_MEM_TYPE_MASK)) ==
1524 (PCI_BASE_ADDRESS_SPACE_MEMORY | PCI_BASE_ADDRESS_MEM_TYPE_64)))
1526 region = &ptdev->bases[index-1];
1527 if (region->bar_flag != PT_BAR_FLAG_UPPER)
1529 bar_flag = PT_BAR_FLAG_UPPER;
1530 goto out;
1534 /* check unused BAR */
1535 r = &d->io_regions[index];
1536 if (!r->size)
1537 goto out;
1539 /* for ExpROM BAR */
1540 if (index == PCI_ROM_SLOT)
1542 bar_flag = PT_BAR_FLAG_MEM;
1543 goto out;
1546 /* check BAR I/O indicator */
1547 if (d->config[reg->offset] & PCI_BASE_ADDRESS_SPACE_IO)
1548 bar_flag = PT_BAR_FLAG_IO;
1549 else
1550 bar_flag = PT_BAR_FLAG_MEM;
1552 out:
1553 return bar_flag;
1556 /* mapping BAR */
1557 static void pt_bar_mapping(struct pt_dev *ptdev, int io_enable, int mem_enable)
1559 PCIDevice *dev = (PCIDevice *)&ptdev->dev;
1560 PCIIORegion *r;
1561 struct pt_region *base = NULL;
1562 uint32_t r_size = 0, r_addr = -1;
1563 int ret = 0;
1564 int i;
1566 for (i=0; i<PCI_NUM_REGIONS; i++)
1568 r = &dev->io_regions[i];
1570 /* check valid region */
1571 if (!r->size)
1572 continue;
1574 base = &ptdev->bases[i];
1575 /* skip unused BAR or upper 64bit BAR */
1576 if ((base->bar_flag == PT_BAR_FLAG_UNUSED) ||
1577 (base->bar_flag == PT_BAR_FLAG_UPPER))
1578 continue;
1580 /* copy region address to temporary */
1581 r_addr = r->addr;
1583 /* need unmapping in case I/O Space or Memory Space disable */
1584 if (((base->bar_flag == PT_BAR_FLAG_IO) && !io_enable ) ||
1585 ((base->bar_flag == PT_BAR_FLAG_MEM) && !mem_enable ))
1586 r_addr = -1;
1588 /* prevent guest software mapping memory resource to 00000000h */
1589 if ((base->bar_flag == PT_BAR_FLAG_MEM) && (r_addr == 0))
1590 r_addr = -1;
1592 /* align resource size (memory type only) */
1593 r_size = r->size;
1594 PT_GET_EMUL_SIZE(base->bar_flag, r_size);
1596 /* check overlapped address */
1597 ret = pt_chk_bar_overlap(dev->bus, dev->devfn, r_addr, r_size);
1598 if (ret > 0)
1599 PT_LOG("ptdev[%02x:%02x.%x][Region:%d][Address:%08xh][Size:%08xh] "
1600 "is overlapped.\n", pci_bus_num(dev->bus),
1601 (dev->devfn >> 3) & 0x1F, (dev->devfn & 0x7),
1602 i, r_addr, r_size);
1604 /* check whether we need to update the mapping or not */
1605 if (r_addr != ptdev->bases[i].e_physbase)
1607 /* mapping BAR */
1608 r->map_func((PCIDevice *)ptdev, i, r_addr,
1609 r_size, r->type);
1613 return;
1616 /* initialize emulate register */
1617 static int pt_config_reg_init(struct pt_dev *ptdev,
1618 struct pt_reg_grp_tbl *reg_grp,
1619 struct pt_reg_info_tbl *reg)
1621 struct pt_reg_tbl *reg_entry;
1622 uint32_t data = 0;
1623 int err = 0;
1625 /* allocate register entry */
1626 reg_entry = qemu_mallocz(sizeof(struct pt_reg_tbl));
1627 if (reg_entry == NULL)
1629 PT_LOG("Failed to allocate memory.\n");
1630 err = -1;
1631 goto out;
1634 /* initialize register entry */
1635 reg_entry->reg = reg;
1636 reg_entry->data = 0;
1638 if (reg->init)
1640 /* initialize emulate register */
1641 data = reg->init(ptdev, reg_entry->reg,
1642 (reg_grp->base_offset + reg->offset));
1643 if (data == PT_INVALID_REG)
1645 /* free unused BAR register entry */
1646 free(reg_entry);
1647 goto out;
1649 /* set register value */
1650 reg_entry->data = data;
1652 /* list add register entry */
1653 LIST_INSERT_HEAD(&reg_grp->reg_tbl_head, reg_entry, entries);
1655 out:
1656 return err;
1659 /* initialize emulate register group */
1660 static int pt_config_init(struct pt_dev *ptdev)
1662 struct pt_reg_grp_tbl *reg_grp_entry = NULL;
1663 struct pt_reg_info_tbl *reg_tbl = NULL;
1664 uint32_t reg_grp_offset = 0;
1665 int i, j, err = 0;
1667 /* initialize register group list */
1668 LIST_INIT(&ptdev->reg_grp_tbl_head);
1670 /* initialize register group */
1671 for (i=0; pt_emu_reg_grp_tbl[i].grp_size != 0; i++)
1673 if (pt_emu_reg_grp_tbl[i].grp_id != 0xFF)
1675 reg_grp_offset = (uint32_t)find_cap_offset(ptdev->pci_dev,
1676 pt_emu_reg_grp_tbl[i].grp_id);
1677 if (!reg_grp_offset)
1678 continue;
1681 /* allocate register group table */
1682 reg_grp_entry = qemu_mallocz(sizeof(struct pt_reg_grp_tbl));
1683 if (reg_grp_entry == NULL)
1685 PT_LOG("Failed to allocate memory.\n");
1686 err = -1;
1687 goto out;
1690 /* initialize register group entry */
1691 LIST_INIT(&reg_grp_entry->reg_tbl_head);
1693 /* need to declare here, to enable searching Cap Ptr reg
1694 * (which is in the same reg group) when initializing Status reg
1695 */
1696 LIST_INSERT_HEAD(&ptdev->reg_grp_tbl_head, reg_grp_entry, entries);
1698 reg_grp_entry->base_offset = reg_grp_offset;
1699 reg_grp_entry->reg_grp =
1700 (struct pt_reg_grp_info_tbl*)&pt_emu_reg_grp_tbl[i];
1701 if (pt_emu_reg_grp_tbl[i].size_init)
1703 /* get register group size */
1704 reg_grp_entry->size = pt_emu_reg_grp_tbl[i].size_init(ptdev,
1705 reg_grp_entry->reg_grp,
1706 reg_grp_offset);
1709 if (pt_emu_reg_grp_tbl[i].grp_type == GRP_TYPE_EMU)
1711 if (pt_emu_reg_grp_tbl[i].emu_reg_tbl)
1713 reg_tbl = pt_emu_reg_grp_tbl[i].emu_reg_tbl;
1714 /* initialize capability register */
1715 for (j=0; reg_tbl->size != 0; j++, reg_tbl++)
1717 /* initialize capability register */
1718 err = pt_config_reg_init(ptdev, reg_grp_entry, reg_tbl);
1719 if (err < 0)
1720 goto out;
1724 reg_grp_offset = 0;
1727 out:
1728 return err;
1731 /* delete all emulate register */
1732 static void pt_config_delete(struct pt_dev *ptdev)
1734 struct pt_reg_grp_tbl *reg_grp_entry = NULL;
1735 struct pt_reg_tbl *reg_entry = NULL;
1737 /* free MSI/MSI-X info table */
1738 if (ptdev->msix)
1739 pt_msix_delete(ptdev);
1740 if (ptdev->msi)
1741 free(ptdev->msi);
1743 /* free all register group entry */
1744 while ((reg_grp_entry = ptdev->reg_grp_tbl_head.lh_first) != NULL)
1746 /* free all register entry */
1747 while ((reg_entry = reg_grp_entry->reg_tbl_head.lh_first) != NULL)
1749 LIST_REMOVE(reg_entry, entries);
1750 qemu_free(reg_entry);
1753 LIST_REMOVE(reg_grp_entry, entries);
1754 qemu_free(reg_grp_entry);
1758 /* initialize common register value */
1759 static uint32_t pt_common_reg_init(struct pt_dev *ptdev,
1760 struct pt_reg_info_tbl *reg, uint32_t real_offset)
1762 return reg->init_val;
1765 /* initialize Capabilities Pointer or Next Pointer register */
1766 static uint32_t pt_ptr_reg_init(struct pt_dev *ptdev,
1767 struct pt_reg_info_tbl *reg, uint32_t real_offset)
1769 uint32_t reg_field = (uint32_t)ptdev->dev.config[real_offset];
1770 int i;
1772 /* find capability offset */
1773 while (reg_field)
1775 for (i=0; pt_emu_reg_grp_tbl[i].grp_size != 0; i++)
1777 /* check whether the next capability
1778 * should be exported to guest or not
1779 */
1780 if (pt_emu_reg_grp_tbl[i].grp_id == ptdev->dev.config[reg_field])
1782 if (pt_emu_reg_grp_tbl[i].grp_type == GRP_TYPE_EMU)
1783 goto out;
1784 /* ignore the 0 hardwired capability, find next one */
1785 break;
1788 /* next capability */
1789 reg_field = (uint32_t)ptdev->dev.config[reg_field + 1];
1792 out:
1793 return reg_field;
1796 /* initialize Status register */
1797 static uint32_t pt_status_reg_init(struct pt_dev *ptdev,
1798 struct pt_reg_info_tbl *reg, uint32_t real_offset)
1800 struct pt_reg_grp_tbl *reg_grp_entry = NULL;
1801 struct pt_reg_tbl *reg_entry = NULL;
1802 int reg_field = 0;
1804 /* find Header register group */
1805 reg_grp_entry = pt_find_reg_grp(ptdev, PCI_CAPABILITY_LIST);
1806 if (reg_grp_entry)
1808 /* find Capabilities Pointer register */
1809 reg_entry = pt_find_reg(reg_grp_entry, PCI_CAPABILITY_LIST);
1810 if (reg_entry)
1812 /* check Capabilities Pointer register */
1813 if (reg_entry->data)
1814 reg_field |= PCI_STATUS_CAP_LIST;
1815 else
1816 reg_field &= ~PCI_STATUS_CAP_LIST;
1818 else
1820 /* exit I/O emulator */
1821 PT_LOG("Internal error: Couldn't find pt_reg_tbl for "
1822 "Capabilities Pointer register. I/O emulator exit.\n");
1823 exit(1);
1826 else
1828 /* exit I/O emulator */
1829 PT_LOG("Internal error: Couldn't find pt_reg_grp_tbl for Header. "
1830 "I/O emulator exit.\n");
1831 exit(1);
1834 return reg_field;
1837 /* initialize Interrupt Pin register */
1838 static uint32_t pt_irqpin_reg_init(struct pt_dev *ptdev,
1839 struct pt_reg_info_tbl *reg, uint32_t real_offset)
1841 int reg_field = 0;
1843 /* set Interrupt Pin register to use INTA# if it has */
1844 if (ptdev->dev.config[real_offset])
1845 reg_field = 0x01;
1847 return reg_field;
1850 /* initialize BAR */
1851 static uint32_t pt_bar_reg_init(struct pt_dev *ptdev,
1852 struct pt_reg_info_tbl *reg, uint32_t real_offset)
1854 int reg_field = 0;
1855 int index;
1857 /* get BAR index */
1858 index = pt_bar_offset_to_index(reg->offset);
1859 if (index < 0)
1861 /* exit I/O emulator */
1862 PT_LOG("Internal error: Invalid BAR index[%d]. "
1863 "I/O emulator exit.\n", index);
1864 exit(1);
1867 /* set initial guest physical base address to -1 */
1868 ptdev->bases[index].e_physbase = -1;
1870 /* set BAR flag */
1871 ptdev->bases[index].bar_flag = pt_bar_reg_parse(ptdev, reg);
1872 if (ptdev->bases[index].bar_flag == PT_BAR_FLAG_UNUSED)
1873 reg_field = PT_INVALID_REG;
1875 return reg_field;
1878 /* initialize Link Control register */
1879 static uint32_t pt_linkctrl_reg_init(struct pt_dev *ptdev,
1880 struct pt_reg_info_tbl *reg, uint32_t real_offset)
1882 uint8_t cap_ver = 0;
1883 uint8_t dev_type = 0;
1885 cap_ver = (ptdev->dev.config[(real_offset - reg->offset) + PCI_EXP_FLAGS] &
1886 (uint8_t)PCI_EXP_FLAGS_VERS);
1887 dev_type = (ptdev->dev.config[(real_offset - reg->offset) + PCI_EXP_FLAGS] &
1888 (uint8_t)PCI_EXP_FLAGS_TYPE) >> 4;
1890 /* no need to initialize in case of Root Complex Integrated Endpoint
1891 * with cap_ver 1.x
1892 */
1893 if ((dev_type == PCI_EXP_TYPE_ROOT_INT_EP) && (cap_ver == 1))
1894 return PT_INVALID_REG;
1896 return reg->init_val;
1899 /* initialize Device Control 2 register */
1900 static uint32_t pt_devctrl2_reg_init(struct pt_dev *ptdev,
1901 struct pt_reg_info_tbl *reg, uint32_t real_offset)
1903 uint8_t cap_ver = 0;
1905 cap_ver = (ptdev->dev.config[(real_offset - reg->offset) + PCI_EXP_FLAGS] &
1906 (uint8_t)PCI_EXP_FLAGS_VERS);
1908 /* no need to initialize in case of cap_ver 1.x */
1909 if (cap_ver == 1)
1910 return PT_INVALID_REG;
1912 return reg->init_val;
1915 /* initialize Link Control 2 register */
1916 static uint32_t pt_linkctrl2_reg_init(struct pt_dev *ptdev,
1917 struct pt_reg_info_tbl *reg, uint32_t real_offset)
1919 int reg_field = 0;
1920 uint8_t cap_ver = 0;
1922 cap_ver = (ptdev->dev.config[(real_offset - reg->offset) + PCI_EXP_FLAGS] &
1923 (uint8_t)PCI_EXP_FLAGS_VERS);
1925 /* no need to initialize in case of cap_ver 1.x */
1926 if (cap_ver == 1)
1927 return PT_INVALID_REG;
1929 /* set Supported Link Speed */
1930 reg_field |=
1931 (0x0F &
1932 ptdev->dev.config[(real_offset - reg->offset) + PCI_EXP_LNKCAP]);
1934 return reg_field;
1937 /* initialize Message Control register */
1938 static uint32_t pt_msgctrl_reg_init(struct pt_dev *ptdev,
1939 struct pt_reg_info_tbl *reg, uint32_t real_offset)
1941 PCIDevice *d = (struct PCIDevice *)ptdev;
1942 struct pci_dev *pdev = ptdev->pci_dev;
1943 uint32_t reg_field = 0;
1945 /* use I/O device register's value as initial value */
1946 reg_field |= *((uint16_t*)(d->config + real_offset));
1948 if (reg_field & PCI_MSI_FLAGS_ENABLE)
1950 PT_LOG("MSI enabled already, disable first\n");
1951 pci_write_word(pdev, real_offset, reg_field & ~PCI_MSI_FLAGS_ENABLE);
1953 ptdev->msi->flags |= (reg_field | MSI_FLAG_UNINIT);
1955 /* All register is 0 after reset, except first 4 byte */
1956 reg_field &= reg->ro_mask;
1958 return reg_field;
1961 /* initialize Message Address register */
1962 static uint32_t pt_msgaddr32_reg_init(struct pt_dev *ptdev,
1963 struct pt_reg_info_tbl *reg, uint32_t real_offset)
1965 PCIDevice *d = (struct PCIDevice *)ptdev;
1966 uint32_t reg_field = 0;
1968 /* use I/O device register's value as initial value */
1969 reg_field |= *((uint32_t*)(d->config + real_offset));
1971 return reg_field;
1974 /* initialize Message Upper Address register */
1975 static uint32_t pt_msgaddr64_reg_init(struct pt_dev *ptdev,
1976 struct pt_reg_info_tbl *reg, uint32_t real_offset)
1978 PCIDevice *d = (struct PCIDevice *)ptdev;
1979 uint32_t reg_field = 0;
1981 /* no need to initialize in case of 32 bit type */
1982 if (!(ptdev->msi->flags & PCI_MSI_FLAGS_64BIT))
1983 return PT_INVALID_REG;
1985 /* use I/O device register's value as initial value */
1986 reg_field |= *((uint32_t*)(d->config + real_offset));
1988 return reg_field;
1991 /* this function will be called twice (for 32 bit and 64 bit type) */
1992 /* initialize Message Data register */
1993 static uint32_t pt_msgdata_reg_init(struct pt_dev *ptdev,
1994 struct pt_reg_info_tbl *reg, uint32_t real_offset)
1996 PCIDevice *d = (struct PCIDevice *)ptdev;
1997 uint32_t flags = ptdev->msi->flags;
1998 uint32_t offset = reg->offset;
2000 /* check the offset whether matches the type or not */
2001 if (((offset == PCI_MSI_DATA_64) && (flags & PCI_MSI_FLAGS_64BIT)) ||
2002 ((offset == PCI_MSI_DATA_32) && !(flags & PCI_MSI_FLAGS_64BIT)))
2003 return *((uint16_t*)(d->config + real_offset));
2004 else
2005 return PT_INVALID_REG;
2008 /* initialize Message Control register for MSI-X */
2009 static uint32_t pt_msixctrl_reg_init(struct pt_dev *ptdev,
2010 struct pt_reg_info_tbl *reg, uint32_t real_offset)
2012 PCIDevice *d = (struct PCIDevice *)ptdev;
2013 struct pci_dev *pdev = ptdev->pci_dev;
2014 uint16_t reg_field = 0;
2016 /* use I/O device register's value as initial value */
2017 reg_field |= *((uint16_t*)(d->config + real_offset));
2019 if (reg_field & PCI_MSIX_ENABLE)
2021 PT_LOG("MSIX enabled already, disable first\n");
2022 pci_write_word(pdev, real_offset, reg_field & ~PCI_MSIX_ENABLE);
2023 reg_field &= ~(PCI_MSIX_ENABLE | PCI_MSIX_MASK);
2026 return reg_field;
2029 /* get register group size */
2030 static uint8_t pt_reg_grp_size_init(struct pt_dev *ptdev,
2031 struct pt_reg_grp_info_tbl *grp_reg, uint32_t base_offset)
2033 return grp_reg->grp_size;
2036 /* get MSI Capability Structure register group size */
2037 static uint8_t pt_msi_size_init(struct pt_dev *ptdev,
2038 struct pt_reg_grp_info_tbl *grp_reg, uint32_t base_offset)
2040 PCIDevice *d = &ptdev->dev;
2041 uint16_t msg_ctrl = 0;
2042 uint8_t msi_size = 0xa;
2044 msg_ctrl = *((uint16_t*)(d->config + (base_offset + PCI_MSI_FLAGS)));
2046 /* check 64 bit address capable & Per-vector masking capable */
2047 if (msg_ctrl & PCI_MSI_FLAGS_64BIT)
2048 msi_size += 4;
2049 if (msg_ctrl & PCI_MSI_FLAGS_MASK_BIT)
2050 msi_size += 10;
2052 ptdev->msi = malloc(sizeof(struct pt_msi_info));
2053 if ( !ptdev->msi )
2055 /* exit I/O emulator */
2056 PT_LOG("error allocation pt_msi_info. I/O emulator exit.\n");
2057 exit(1);
2059 memset(ptdev->msi, 0, sizeof(struct pt_msi_info));
2061 return msi_size;
2064 /* get MSI-X Capability Structure register group size */
2065 static uint8_t pt_msix_size_init(struct pt_dev *ptdev,
2066 struct pt_reg_grp_info_tbl *grp_reg, uint32_t base_offset)
2068 int ret = 0;
2070 ret = pt_msix_init(ptdev, base_offset);
2072 if (ret == -1)
2074 /* exit I/O emulator */
2075 PT_LOG("Internal error: Invalid pt_msix_init return value[%d]. "
2076 "I/O emulator exit.\n", ret);
2077 exit(1);
2080 return grp_reg->grp_size;
2083 /* get Vendor Specific Capability Structure register group size */
2084 static uint8_t pt_vendor_size_init(struct pt_dev *ptdev,
2085 struct pt_reg_grp_info_tbl *grp_reg, uint32_t base_offset)
2087 return ptdev->dev.config[base_offset + 0x02];
2090 /* get PCI Express Capability Structure register group size */
2091 static uint8_t pt_pcie_size_init(struct pt_dev *ptdev,
2092 struct pt_reg_grp_info_tbl *grp_reg, uint32_t base_offset)
2094 PCIDevice *d = &ptdev->dev;
2095 uint16_t exp_flag = 0;
2096 uint16_t type = 0;
2097 uint16_t vers = 0;
2098 uint8_t pcie_size = 0;
2100 exp_flag = *((uint16_t*)(d->config + (base_offset + PCI_EXP_FLAGS)));
2101 type = (exp_flag & PCI_EXP_FLAGS_TYPE) >> 4;
2102 vers = (exp_flag & PCI_EXP_FLAGS_VERS);
2104 /* calculate size depend on capability version and device/port type */
2105 /* in case of PCI Express Base Specification Rev 1.x */
2106 if (vers == 1)
2108 /* The PCI Express Capabilities, Device Capabilities, and Device
2109 * Status/Control registers are required for all PCI Express devices.
2110 * The Link Capabilities and Link Status/Control are required for all
2111 * Endpoints that are not Root Complex Integrated Endpoints. Endpoints
2112 * are not required to implement registers other than those listed
2113 * above and terminate the capability structure.
2114 */
2115 switch (type) {
2116 case PCI_EXP_TYPE_ENDPOINT:
2117 case PCI_EXP_TYPE_LEG_END:
2118 pcie_size = 0x14;
2119 break;
2120 case PCI_EXP_TYPE_ROOT_INT_EP:
2121 /* has no link */
2122 pcie_size = 0x0C;
2123 break;
2124 /* only EndPoint passthrough is supported */
2125 case PCI_EXP_TYPE_ROOT_PORT:
2126 case PCI_EXP_TYPE_UPSTREAM:
2127 case PCI_EXP_TYPE_DOWNSTREAM:
2128 case PCI_EXP_TYPE_PCI_BRIDGE:
2129 case PCI_EXP_TYPE_PCIE_BRIDGE:
2130 case PCI_EXP_TYPE_ROOT_EC:
2131 default:
2132 /* exit I/O emulator */
2133 PT_LOG("Internal error: Unsupported device/port type[%d]. "
2134 "I/O emulator exit.\n", type);
2135 exit(1);
2138 /* in case of PCI Express Base Specification Rev 2.0 */
2139 else if (vers == 2)
2141 switch (type) {
2142 case PCI_EXP_TYPE_ENDPOINT:
2143 case PCI_EXP_TYPE_LEG_END:
2144 case PCI_EXP_TYPE_ROOT_INT_EP:
2145 /* For Functions that do not implement the registers,
2146 * these spaces must be hardwired to 0b.
2147 */
2148 pcie_size = 0x3C;
2149 break;
2150 /* only EndPoint passthrough is supported */
2151 case PCI_EXP_TYPE_ROOT_PORT:
2152 case PCI_EXP_TYPE_UPSTREAM:
2153 case PCI_EXP_TYPE_DOWNSTREAM:
2154 case PCI_EXP_TYPE_PCI_BRIDGE:
2155 case PCI_EXP_TYPE_PCIE_BRIDGE:
2156 case PCI_EXP_TYPE_ROOT_EC:
2157 default:
2158 /* exit I/O emulator */
2159 PT_LOG("Internal error: Unsupported device/port type[%d]. "
2160 "I/O emulator exit.\n", type);
2161 exit(1);
2164 else
2166 /* exit I/O emulator */
2167 PT_LOG("Internal error: Unsupported capability version[%d]. "
2168 "I/O emulator exit.\n", vers);
2169 exit(1);
2172 return pcie_size;
2175 /* read byte size emulate register */
2176 static int pt_byte_reg_read(struct pt_dev *ptdev,
2177 struct pt_reg_tbl *cfg_entry,
2178 uint8_t *value, uint8_t valid_mask)
2180 struct pt_reg_info_tbl *reg = cfg_entry->reg;
2181 uint8_t valid_emu_mask = 0;
2183 /* emulate byte register */
2184 valid_emu_mask = reg->emu_mask & valid_mask;
2185 *value = ((*value & ~valid_emu_mask) |
2186 (cfg_entry->data & valid_emu_mask));
2188 return 0;
2191 /* read word size emulate register */
2192 static int pt_word_reg_read(struct pt_dev *ptdev,
2193 struct pt_reg_tbl *cfg_entry,
2194 uint16_t *value, uint16_t valid_mask)
2196 struct pt_reg_info_tbl *reg = cfg_entry->reg;
2197 uint16_t valid_emu_mask = 0;
2199 /* emulate word register */
2200 valid_emu_mask = reg->emu_mask & valid_mask;
2201 *value = ((*value & ~valid_emu_mask) |
2202 (cfg_entry->data & valid_emu_mask));
2204 return 0;
2207 /* read long size emulate register */
2208 static int pt_long_reg_read(struct pt_dev *ptdev,
2209 struct pt_reg_tbl *cfg_entry,
2210 uint32_t *value, uint32_t valid_mask)
2212 struct pt_reg_info_tbl *reg = cfg_entry->reg;
2213 uint32_t valid_emu_mask = 0;
2215 /* emulate long register */
2216 valid_emu_mask = reg->emu_mask & valid_mask;
2217 *value = ((*value & ~valid_emu_mask) |
2218 (cfg_entry->data & valid_emu_mask));
2220 return 0;
2223 /* read BAR */
2224 static int pt_bar_reg_read(struct pt_dev *ptdev,
2225 struct pt_reg_tbl *cfg_entry,
2226 uint32_t *value, uint32_t valid_mask)
2228 struct pt_reg_info_tbl *reg = cfg_entry->reg;
2229 uint32_t valid_emu_mask = 0;
2230 uint32_t bar_emu_mask = 0;
2231 int index;
2233 /* get BAR index */
2234 index = pt_bar_offset_to_index(reg->offset);
2235 if (index < 0)
2237 /* exit I/O emulator */
2238 PT_LOG("Internal error: Invalid BAR index[%d]. "
2239 "I/O emulator exit.\n", index);
2240 exit(1);
2243 /* set emulate mask depend on BAR flag */
2244 switch (ptdev->bases[index].bar_flag)
2246 case PT_BAR_FLAG_MEM:
2247 bar_emu_mask = PT_BAR_MEM_EMU_MASK;
2248 break;
2249 case PT_BAR_FLAG_IO:
2250 bar_emu_mask = PT_BAR_IO_EMU_MASK;
2251 break;
2252 case PT_BAR_FLAG_UPPER:
2253 bar_emu_mask = PT_BAR_ALLF;
2254 break;
2255 default:
2256 break;
2259 /* emulate BAR */
2260 valid_emu_mask = bar_emu_mask & valid_mask;
2261 *value = ((*value & ~valid_emu_mask) |
2262 (cfg_entry->data & valid_emu_mask));
2264 return 0;
2267 /* write byte size emulate register */
2268 static int pt_byte_reg_write(struct pt_dev *ptdev,
2269 struct pt_reg_tbl *cfg_entry,
2270 uint8_t *value, uint8_t dev_value, uint8_t valid_mask)
2272 struct pt_reg_info_tbl *reg = cfg_entry->reg;
2273 uint8_t writable_mask = 0;
2274 uint8_t throughable_mask = 0;
2276 /* modify emulate register */
2277 writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask;
2278 cfg_entry->data = ((*value & writable_mask) |
2279 (cfg_entry->data & ~writable_mask));
2281 /* create value for writing to I/O device register */
2282 throughable_mask = ~reg->emu_mask & valid_mask;
2283 *value = ((*value & throughable_mask) |
2284 (dev_value & ~throughable_mask));
2286 return 0;
2289 /* write word size emulate register */
2290 static int pt_word_reg_write(struct pt_dev *ptdev,
2291 struct pt_reg_tbl *cfg_entry,
2292 uint16_t *value, uint16_t dev_value, uint16_t valid_mask)
2294 struct pt_reg_info_tbl *reg = cfg_entry->reg;
2295 uint16_t writable_mask = 0;
2296 uint16_t throughable_mask = 0;
2298 /* modify emulate register */
2299 writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask;
2300 cfg_entry->data = ((*value & writable_mask) |
2301 (cfg_entry->data & ~writable_mask));
2303 /* create value for writing to I/O device register */
2304 throughable_mask = ~reg->emu_mask & valid_mask;
2305 *value = ((*value & throughable_mask) |
2306 (dev_value & ~throughable_mask));
2308 return 0;
2311 /* write long size emulate register */
2312 static int pt_long_reg_write(struct pt_dev *ptdev,
2313 struct pt_reg_tbl *cfg_entry,
2314 uint32_t *value, uint32_t dev_value, uint32_t valid_mask)
2316 struct pt_reg_info_tbl *reg = cfg_entry->reg;
2317 uint32_t writable_mask = 0;
2318 uint32_t throughable_mask = 0;
2320 /* modify emulate register */
2321 writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask;
2322 cfg_entry->data = ((*value & writable_mask) |
2323 (cfg_entry->data & ~writable_mask));
2325 /* create value for writing to I/O device register */
2326 throughable_mask = ~reg->emu_mask & valid_mask;
2327 *value = ((*value & throughable_mask) |
2328 (dev_value & ~throughable_mask));
2330 return 0;
2333 /* write Command register */
2334 static int pt_cmd_reg_write(struct pt_dev *ptdev,
2335 struct pt_reg_tbl *cfg_entry,
2336 uint16_t *value, uint16_t dev_value, uint16_t valid_mask)
2338 struct pt_reg_info_tbl *reg = cfg_entry->reg;
2339 uint16_t writable_mask = 0;
2340 uint16_t throughable_mask = 0;
2341 uint16_t wr_value = *value;
2343 /* modify emulate register */
2344 writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask;
2345 cfg_entry->data = ((*value & writable_mask) |
2346 (cfg_entry->data & ~writable_mask));
2348 /* create value for writing to I/O device register */
2349 throughable_mask = ~reg->emu_mask & valid_mask;
2350 *value = ((*value & throughable_mask) | (dev_value & ~throughable_mask));
2352 /* mapping BAR */
2353 pt_bar_mapping(ptdev, wr_value & PCI_COMMAND_IO,
2354 wr_value & PCI_COMMAND_MEMORY);
2356 return 0;
2359 /* write BAR */
2360 static int pt_bar_reg_write(struct pt_dev *ptdev,
2361 struct pt_reg_tbl *cfg_entry,
2362 uint32_t *value, uint32_t dev_value, uint32_t valid_mask)
2364 struct pt_reg_info_tbl *reg = cfg_entry->reg;
2365 struct pt_reg_grp_tbl *reg_grp_entry = NULL;
2366 struct pt_reg_tbl *reg_entry = NULL;
2367 struct pt_region *base = NULL;
2368 PCIDevice *d = (PCIDevice *)&ptdev->dev;
2369 PCIIORegion *r;
2370 uint32_t writable_mask = 0;
2371 uint32_t throughable_mask = 0;
2372 uint32_t bar_emu_mask = 0;
2373 uint32_t bar_ro_mask = 0;
2374 uint32_t new_addr, last_addr;
2375 uint32_t prev_offset;
2376 uint32_t r_size = 0;
2377 int index = 0;
2379 /* get BAR index */
2380 index = pt_bar_offset_to_index(reg->offset);
2381 if (index < 0)
2383 /* exit I/O emulator */
2384 PT_LOG("Internal error: Invalid BAR index[%d]. "
2385 "I/O emulator exit.\n", index);
2386 exit(1);
2389 r = &d->io_regions[index];
2390 r_size = r->size;
2391 base = &ptdev->bases[index];
2392 /* align resource size (memory type only) */
2393 PT_GET_EMUL_SIZE(base->bar_flag, r_size);
2395 /* set emulate mask and read-only mask depend on BAR flag */
2396 switch (ptdev->bases[index].bar_flag)
2398 case PT_BAR_FLAG_MEM:
2399 bar_emu_mask = PT_BAR_MEM_EMU_MASK;
2400 bar_ro_mask = PT_BAR_MEM_RO_MASK | (r_size - 1);
2401 break;
2402 case PT_BAR_FLAG_IO:
2403 bar_emu_mask = PT_BAR_IO_EMU_MASK;
2404 bar_ro_mask = PT_BAR_IO_RO_MASK | (r_size - 1);
2405 break;
2406 case PT_BAR_FLAG_UPPER:
2407 bar_emu_mask = PT_BAR_ALLF;
2408 bar_ro_mask = 0; /* all upper 32bit are R/W */
2409 break;
2410 default:
2411 break;
2414 /* modify emulate register */
2415 writable_mask = bar_emu_mask & ~bar_ro_mask & valid_mask;
2416 cfg_entry->data = ((*value & writable_mask) |
2417 (cfg_entry->data & ~writable_mask));
2419 /* check whether we need to update the virtual region address or not */
2420 switch (ptdev->bases[index].bar_flag)
2422 case PT_BAR_FLAG_MEM:
2423 /* nothing to do */
2424 break;
2425 case PT_BAR_FLAG_IO:
2426 new_addr = cfg_entry->data;
2427 last_addr = new_addr + r_size - 1;
2428 /* check invalid address */
2429 if (last_addr <= new_addr || !new_addr || last_addr >= 0x10000)
2431 /* check 64K range */
2432 if ((last_addr >= 0x10000) &&
2433 (cfg_entry->data != (PT_BAR_ALLF & ~bar_ro_mask)))
2435 PT_LOG("Guest attempt to set Base Address over the 64KB. "
2436 "[%02x:%02x.%x][Offset:%02xh][Address:%08xh][Size:%08xh]\n",
2437 pci_bus_num(d->bus),
2438 ((d->devfn >> 3) & 0x1F), (d->devfn & 0x7),
2439 reg->offset, new_addr, r_size);
2441 /* just remove mapping */
2442 r->addr = -1;
2443 goto exit;
2445 break;
2446 case PT_BAR_FLAG_UPPER:
2447 if (cfg_entry->data)
2449 if (cfg_entry->data != (PT_BAR_ALLF & ~bar_ro_mask))
2451 PT_LOG("Guest attempt to set high MMIO Base Address. "
2452 "Ignore mapping. "
2453 "[%02x:%02x.%x][Offset:%02xh][High Address:%08xh]\n",
2454 pci_bus_num(d->bus),
2455 ((d->devfn >> 3) & 0x1F), (d->devfn & 0x7),
2456 reg->offset, cfg_entry->data);
2458 /* clear lower address */
2459 d->io_regions[index-1].addr = -1;
2461 else
2463 /* find lower 32bit BAR */
2464 prev_offset = (reg->offset - 4);
2465 reg_grp_entry = pt_find_reg_grp(ptdev, prev_offset);
2466 if (reg_grp_entry)
2468 reg_entry = pt_find_reg(reg_grp_entry, prev_offset);
2469 if (reg_entry)
2470 /* restore lower address */
2471 d->io_regions[index-1].addr = reg_entry->data;
2472 else
2473 return -1;
2475 else
2476 return -1;
2479 /* never mapping the 'empty' upper region,
2480 * because we'll do it enough for the lower region.
2481 */
2482 r->addr = -1;
2483 goto exit;
2484 default:
2485 break;
2488 /* update the corresponding virtual region address */
2489 r->addr = cfg_entry->data;
2491 exit:
2492 /* create value for writing to I/O device register */
2493 throughable_mask = ~bar_emu_mask & valid_mask;
2494 *value = ((*value & throughable_mask) |
2495 (dev_value & ~throughable_mask));
2497 return 0;
2500 /* write Exp ROM BAR */
2501 static int pt_exp_rom_bar_reg_write(struct pt_dev *ptdev,
2502 struct pt_reg_tbl *cfg_entry,
2503 uint32_t *value, uint32_t dev_value, uint32_t valid_mask)
2505 struct pt_reg_info_tbl *reg = cfg_entry->reg;
2506 struct pt_region *base = NULL;
2507 PCIDevice *d = (PCIDevice *)&ptdev->dev;
2508 PCIIORegion *r;
2509 uint32_t writable_mask = 0;
2510 uint32_t throughable_mask = 0;
2511 uint32_t r_size = 0;
2512 uint32_t bar_emu_mask = 0;
2513 uint32_t bar_ro_mask = 0;
2515 r = &d->io_regions[PCI_ROM_SLOT];
2516 r_size = r->size;
2517 base = &ptdev->bases[PCI_ROM_SLOT];
2518 /* align memory type resource size */
2519 PT_GET_EMUL_SIZE(base->bar_flag, r_size);
2521 /* set emulate mask and read-only mask */
2522 bar_emu_mask = reg->emu_mask;
2523 bar_ro_mask = reg->ro_mask | (r_size - 1);
2525 /* modify emulate register */
2526 writable_mask = bar_emu_mask & ~bar_ro_mask & valid_mask;
2527 cfg_entry->data = ((*value & writable_mask) |
2528 (cfg_entry->data & ~writable_mask));
2530 /* update the corresponding virtual region address */
2531 r->addr = cfg_entry->data;
2533 /* create value for writing to I/O device register */
2534 throughable_mask = ~bar_emu_mask & valid_mask;
2535 *value = ((*value & throughable_mask) |
2536 (dev_value & ~throughable_mask));
2538 return 0;
2541 /* write Power Management Control/Status register */
2542 static int pt_pmcsr_reg_write(struct pt_dev *ptdev,
2543 struct pt_reg_tbl *cfg_entry,
2544 uint16_t *value, uint16_t dev_value, uint16_t valid_mask)
2546 struct pt_reg_info_tbl *reg = cfg_entry->reg;
2547 uint16_t writable_mask = 0;
2548 uint16_t throughable_mask = 0;
2549 uint16_t pmcsr_mask = (PCI_PM_CTRL_PME_ENABLE |
2550 PCI_PM_CTRL_DATA_SEL_MASK |
2551 PCI_PM_CTRL_PME_STATUS);
2553 /* modify emulate register */
2554 writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask & ~pmcsr_mask;
2555 /* ignore it when the requested state neither D3 nor D0 */
2556 if (((*value & PCI_PM_CTRL_STATE_MASK) != PCI_PM_CTRL_STATE_MASK) &&
2557 ((*value & PCI_PM_CTRL_STATE_MASK) != 0))
2558 writable_mask &= ~PCI_PM_CTRL_STATE_MASK;
2560 cfg_entry->data = ((*value & writable_mask) |
2561 (cfg_entry->data & ~writable_mask));
2563 /* create value for writing to I/O device register */
2564 throughable_mask = ~reg->emu_mask & valid_mask;
2565 *value = ((*value & throughable_mask) |
2566 (dev_value & ~throughable_mask));
2568 return 0;
2571 /* write Device Control register */
2572 static int pt_devctrl_reg_write(struct pt_dev *ptdev,
2573 struct pt_reg_tbl *cfg_entry,
2574 uint16_t *value, uint16_t dev_value, uint16_t valid_mask)
2576 struct pt_reg_info_tbl *reg = cfg_entry->reg;
2577 uint16_t writable_mask = 0;
2578 uint16_t throughable_mask = 0;
2579 uint16_t devctrl_mask = (PCI_EXP_DEVCTL_AUX_PME | 0x8000);
2581 /* modify emulate register */
2582 writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask & ~devctrl_mask;
2583 cfg_entry->data = ((*value & writable_mask) |
2584 (cfg_entry->data & ~writable_mask));
2586 /* create value for writing to I/O device register */
2587 throughable_mask = ~reg->emu_mask & valid_mask;
2588 *value = ((*value & throughable_mask) |
2589 (dev_value & ~throughable_mask));
2591 return 0;
2594 /* write Link Control register */
2595 static int pt_linkctrl_reg_write(struct pt_dev *ptdev,
2596 struct pt_reg_tbl *cfg_entry,
2597 uint16_t *value, uint16_t dev_value, uint16_t valid_mask)
2599 struct pt_reg_info_tbl *reg = cfg_entry->reg;
2600 uint16_t writable_mask = 0;
2601 uint16_t throughable_mask = 0;
2602 uint16_t linkctrl_mask = (PCI_EXP_LNKCTL_ASPM | 0x04 |
2603 PCI_EXP_LNKCTL_DISABLE |
2604 PCI_EXP_LNKCTL_RETRAIN |
2605 0x0400 | 0x0800 | 0xF000);
2607 /* modify emulate register */
2608 writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask & ~linkctrl_mask;
2609 cfg_entry->data = ((*value & writable_mask) |
2610 (cfg_entry->data & ~writable_mask));
2612 /* create value for writing to I/O device register */
2613 throughable_mask = ~reg->emu_mask & valid_mask;
2614 *value = ((*value & throughable_mask) |
2615 (dev_value & ~throughable_mask));
2617 return 0;
2620 /* write Device Control2 register */
2621 static int pt_devctrl2_reg_write(struct pt_dev *ptdev,
2622 struct pt_reg_tbl *cfg_entry,
2623 uint16_t *value, uint16_t dev_value, uint16_t valid_mask)
2625 struct pt_reg_info_tbl *reg = cfg_entry->reg;
2626 uint16_t writable_mask = 0;
2627 uint16_t throughable_mask = 0;
2628 uint16_t devctrl2_mask = 0xFFE0;
2630 /* modify emulate register */
2631 writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask & ~devctrl2_mask;
2632 cfg_entry->data = ((*value & writable_mask) |
2633 (cfg_entry->data & ~writable_mask));
2635 /* create value for writing to I/O device register */
2636 throughable_mask = ~reg->emu_mask & valid_mask;
2637 *value = ((*value & throughable_mask) |
2638 (dev_value & ~throughable_mask));
2640 return 0;
2643 /* write Link Control2 register */
2644 static int pt_linkctrl2_reg_write(struct pt_dev *ptdev,
2645 struct pt_reg_tbl *cfg_entry,
2646 uint16_t *value, uint16_t dev_value, uint16_t valid_mask)
2648 struct pt_reg_info_tbl *reg = cfg_entry->reg;
2649 uint16_t writable_mask = 0;
2650 uint16_t throughable_mask = 0;
2651 uint16_t linkctrl2_mask = (0x0040 | 0xE000);
2653 /* modify emulate register */
2654 writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask &
2655 ~linkctrl2_mask;
2656 cfg_entry->data = ((*value & writable_mask) |
2657 (cfg_entry->data & ~writable_mask));
2659 /* create value for writing to I/O device register */
2660 throughable_mask = ~reg->emu_mask & valid_mask;
2661 *value = ((*value & throughable_mask) |
2662 (dev_value & ~throughable_mask));
2664 return 0;
2667 /* write Message Control register */
2668 static int pt_msgctrl_reg_write(struct pt_dev *ptdev,
2669 struct pt_reg_tbl *cfg_entry,
2670 uint16_t *value, uint16_t dev_value, uint16_t valid_mask)
2672 struct pt_reg_info_tbl *reg = cfg_entry->reg;
2673 uint16_t writable_mask = 0;
2674 uint16_t throughable_mask = 0;
2675 uint16_t old_ctrl = cfg_entry->data;
2676 PCIDevice *pd = (PCIDevice *)ptdev;
2678 /* Currently no support for multi-vector */
2679 if ((*value & PCI_MSI_FLAGS_QSIZE) != 0x0)
2680 PT_LOG("try to set more than 1 vector ctrl %x\n", *value);
2682 /* modify emulate register */
2683 writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask;
2684 cfg_entry->data = ((*value & writable_mask) |
2685 (cfg_entry->data & ~writable_mask));
2686 /* update the msi_info too */
2687 ptdev->msi->flags |= cfg_entry->data &
2688 ~(MSI_FLAG_UNINIT | PT_MSI_MAPPED | PCI_MSI_FLAGS_ENABLE);
2690 PT_LOG("old_ctrl:%04xh new_ctrl:%04xh\n", old_ctrl, cfg_entry->data);
2692 /* create value for writing to I/O device register */
2693 throughable_mask = ~reg->emu_mask & valid_mask;
2694 *value = ((*value & throughable_mask) | (dev_value & ~throughable_mask));
2696 /* update MSI */
2697 if (*value & PCI_MSI_FLAGS_ENABLE)
2699 /* setup MSI pirq for the first time */
2700 if (ptdev->msi->flags & MSI_FLAG_UNINIT)
2702 /* Init physical one */
2703 PT_LOG("setup msi for dev %x\n", pd->devfn);
2704 if (pt_msi_setup(ptdev))
2706 PT_LOG("pt_msi_setup error!!!\n");
2707 return -1;
2709 pt_msi_update(ptdev);
2711 ptdev->msi->flags &= ~MSI_FLAG_UNINIT;
2712 ptdev->msi->flags |= PT_MSI_MAPPED;
2714 ptdev->msi->flags |= PCI_MSI_FLAGS_ENABLE;
2716 else
2717 ptdev->msi->flags &= ~PCI_MSI_FLAGS_ENABLE;
2719 return 0;
2722 /* write Message Address register */
2723 static int pt_msgaddr32_reg_write(struct pt_dev *ptdev,
2724 struct pt_reg_tbl *cfg_entry,
2725 uint32_t *value, uint32_t dev_value, uint32_t valid_mask)
2727 struct pt_reg_info_tbl *reg = cfg_entry->reg;
2728 uint32_t writable_mask = 0;
2729 uint32_t throughable_mask = 0;
2730 uint32_t old_addr = cfg_entry->data;
2732 /* modify emulate register */
2733 writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask;
2734 cfg_entry->data = ((*value & writable_mask) |
2735 (cfg_entry->data & ~writable_mask));
2736 /* update the msi_info too */
2737 ptdev->msi->addr_lo = cfg_entry->data;
2739 PT_LOG("old_addr_lo:%08xh new_addr_lo:%08xh\n", old_addr, cfg_entry->data);
2741 /* create value for writing to I/O device register */
2742 throughable_mask = ~reg->emu_mask & valid_mask;
2743 *value = ((*value & throughable_mask) | (dev_value & ~throughable_mask));
2745 /* update MSI */
2746 if (cfg_entry->data != old_addr)
2748 if (ptdev->msi->flags & PCI_MSI_FLAGS_ENABLE)
2749 pt_msi_update(ptdev);
2752 return 0;
2755 /* write Message Upper Address register */
2756 static int pt_msgaddr64_reg_write(struct pt_dev *ptdev,
2757 struct pt_reg_tbl *cfg_entry,
2758 uint32_t *value, uint32_t dev_value, uint32_t valid_mask)
2760 struct pt_reg_info_tbl *reg = cfg_entry->reg;
2761 uint32_t writable_mask = 0;
2762 uint32_t throughable_mask = 0;
2763 uint32_t old_addr = cfg_entry->data;
2765 /* check whether the type is 64 bit or not */
2766 if (!(ptdev->msi->flags & PCI_MSI_FLAGS_64BIT))
2768 /* exit I/O emulator */
2769 PT_LOG("why comes to Upper Address without 64 bit support??\n");
2770 return -1;
2773 /* modify emulate register */
2774 writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask;
2775 cfg_entry->data = ((*value & writable_mask) |
2776 (cfg_entry->data & ~writable_mask));
2777 /* update the msi_info too */
2778 ptdev->msi->addr_hi = cfg_entry->data;
2780 PT_LOG("old_addr_hi:%08xh new_addr_hi:%08xh\n", old_addr, cfg_entry->data);
2782 /* create value for writing to I/O device register */
2783 throughable_mask = ~reg->emu_mask & valid_mask;
2784 *value = ((*value & throughable_mask) | (dev_value & ~throughable_mask));
2786 /* update MSI */
2787 if (cfg_entry->data != old_addr)
2789 if (ptdev->msi->flags & PCI_MSI_FLAGS_ENABLE)
2790 pt_msi_update(ptdev);
2793 return 0;
2796 /* this function will be called twice (for 32 bit and 64 bit type) */
2797 /* write Message Data register */
2798 static int pt_msgdata_reg_write(struct pt_dev *ptdev,
2799 struct pt_reg_tbl *cfg_entry,
2800 uint16_t *value, uint16_t dev_value, uint16_t valid_mask)
2802 struct pt_reg_info_tbl *reg = cfg_entry->reg;
2803 uint16_t writable_mask = 0;
2804 uint16_t throughable_mask = 0;
2805 uint16_t old_data = cfg_entry->data;
2806 uint32_t flags = ptdev->msi->flags;
2807 uint32_t offset = reg->offset;
2809 /* check the offset whether matches the type or not */
2810 if (!((offset == PCI_MSI_DATA_64) && (flags & PCI_MSI_FLAGS_64BIT)) &&
2811 !((offset == PCI_MSI_DATA_32) && !(flags & PCI_MSI_FLAGS_64BIT)))
2813 /* exit I/O emulator */
2814 PT_LOG("Error: the offset is not match with the 32/64 bit type!!\n");
2815 return -1;
2818 /* modify emulate register */
2819 writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask;
2820 cfg_entry->data = ((*value & writable_mask) |
2821 (cfg_entry->data & ~writable_mask));
2822 /* update the msi_info too */
2823 ptdev->msi->data = cfg_entry->data;
2825 PT_LOG("old_data:%04xh new_data:%04xh\n", old_data, cfg_entry->data);
2827 /* create value for writing to I/O device register */
2828 throughable_mask = ~reg->emu_mask & valid_mask;
2829 *value = ((*value & throughable_mask) | (dev_value & ~throughable_mask));
2831 /* update MSI */
2832 if (cfg_entry->data != old_data)
2834 if (flags & PCI_MSI_FLAGS_ENABLE)
2835 pt_msi_update(ptdev);
2838 return 0;
2841 /* write Message Control register for MSI-X */
2842 static int pt_msixctrl_reg_write(struct pt_dev *ptdev,
2843 struct pt_reg_tbl *cfg_entry,
2844 uint16_t *value, uint16_t dev_value, uint16_t valid_mask)
2846 struct pt_reg_info_tbl *reg = cfg_entry->reg;
2847 uint16_t writable_mask = 0;
2848 uint16_t throughable_mask = 0;
2849 uint16_t old_ctrl = cfg_entry->data;
2851 /* modify emulate register */
2852 writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask;
2853 cfg_entry->data = ((*value & writable_mask) |
2854 (cfg_entry->data & ~writable_mask));
2856 PT_LOG("old_ctrl:%04xh new_ctrl:%04xh\n", old_ctrl, cfg_entry->data);
2858 /* create value for writing to I/O device register */
2859 throughable_mask = ~reg->emu_mask & valid_mask;
2860 *value = ((*value & throughable_mask) | (dev_value & ~throughable_mask));
2862 /* update MSI-X */
2863 if ((*value & PCI_MSIX_ENABLE) && !(*value & PCI_MSIX_MASK))
2864 pt_msix_update(ptdev);
2866 ptdev->msix->enabled = !!(*value & PCI_MSIX_ENABLE);
2868 return 0;
2871 struct pt_dev * register_real_device(PCIBus *e_bus,
2872 const char *e_dev_name, int e_devfn, uint8_t r_bus, uint8_t r_dev,
2873 uint8_t r_func, uint32_t machine_irq, struct pci_access *pci_access)
2875 int rc = -1, i;
2876 struct pt_dev *assigned_device = NULL;
2877 struct pci_dev *pci_dev;
2878 uint8_t e_device, e_intx;
2879 struct pci_config_cf8 machine_bdf;
2880 int free_pci_slot = -1;
2882 PT_LOG("Assigning real physical device %02x:%02x.%x ...\n",
2883 r_bus, r_dev, r_func);
2885 /* Find real device structure */
2886 for (pci_dev = pci_access->devices; pci_dev != NULL;
2887 pci_dev = pci_dev->next)
2889 if ((r_bus == pci_dev->bus) && (r_dev == pci_dev->dev)
2890 && (r_func == pci_dev->func))
2891 break;
2893 if ( pci_dev == NULL )
2895 PT_LOG("Error: couldn't locate device in libpci structures\n");
2896 return NULL;
2898 pci_fill_info(pci_dev, PCI_FILL_IRQ | PCI_FILL_BASES | PCI_FILL_ROM_BASE | PCI_FILL_SIZES);
2900 if ( e_devfn == PT_VIRT_DEVFN_AUTO ) {
2901 /*indicate a static assignment(not hotplug), so find a free PCI hot plug slot */
2902 free_pci_slot = __insert_to_pci_slot(r_bus, r_dev, r_func, 0);
2903 if ( free_pci_slot > 0 )
2904 e_devfn = free_pci_slot << 3;
2905 else
2906 PT_LOG("Error: no free virtual PCI hot plug slot, thus no live migration.\n");
2909 /* Register device */
2910 assigned_device = (struct pt_dev *) pci_register_device(e_bus, e_dev_name,
2911 sizeof(struct pt_dev), e_devfn,
2912 pt_pci_read_config, pt_pci_write_config);
2913 if ( assigned_device == NULL )
2915 PT_LOG("Error: couldn't register real device\n");
2916 return NULL;
2919 if ( free_pci_slot > 0 )
2920 dpci_infos.php_devs[PCI_TO_PHP_SLOT(free_pci_slot)].pt_dev = assigned_device;
2922 assigned_device->pci_dev = pci_dev;
2924 /* Assign device */
2925 machine_bdf.reg = 0;
2926 machine_bdf.bus = r_bus;
2927 machine_bdf.dev = r_dev;
2928 machine_bdf.func = r_func;
2929 rc = xc_assign_device(xc_handle, domid, machine_bdf.value);
2930 if ( rc < 0 )
2931 PT_LOG("Error: xc_assign_device error %d\n", rc);
2933 /* Initialize virtualized PCI configuration (Extended 256 Bytes) */
2934 for ( i = 0; i < PCI_CONFIG_SIZE; i++ )
2935 assigned_device->dev.config[i] = pci_read_byte(pci_dev, i);
2937 /* Handle real device's MMIO/PIO BARs */
2938 pt_register_regions(assigned_device);
2940 /* reinitialize each config register to be emulated */
2941 rc = pt_config_init(assigned_device);
2942 if ( rc < 0 ) {
2943 return NULL;
2946 /* Bind interrupt */
2947 if (!assigned_device->dev.config[0x3d])
2948 goto out;
2950 e_device = (assigned_device->dev.devfn >> 3) & 0x1f;
2951 /* fix virtual interrupt pin to INTA# */
2952 e_intx = 0;
2954 if ( PT_MACHINE_IRQ_AUTO == machine_irq )
2956 int pirq = pci_dev->irq;
2958 machine_irq = pci_dev->irq;
2959 rc = xc_physdev_map_pirq(xc_handle, domid, machine_irq, &pirq);
2961 if ( rc )
2963 /* TBD: unregister device in case of an error */
2964 PT_LOG("Error: Mapping irq failed, rc = %d\n", rc);
2966 else
2967 machine_irq = pirq;
2970 /* bind machine_irq to device */
2971 if ( 0 != machine_irq )
2973 rc = xc_domain_bind_pt_pci_irq(xc_handle, domid, machine_irq, 0,
2974 e_device, e_intx);
2975 if ( rc < 0 )
2977 /* TBD: unregister device in case of an error */
2978 PT_LOG("Error: Binding of interrupt failed! rc=%d\n", rc);
2981 else {
2982 /* Disable PCI intx assertion (turn on bit10 of devctl) */
2983 assigned_device->dev.config[0x05] |= 0x04;
2984 pci_write_word(pci_dev, 0x04,
2985 *(uint16_t *)(&assigned_device->dev.config[0x04]));
2988 out:
2989 PT_LOG("Real physical device %02x:%02x.%x registered successfuly!\n",
2990 r_bus, r_dev, r_func);
2992 return assigned_device;
2995 int unregister_real_device(int php_slot)
2997 struct php_dev *php_dev;
2998 struct pci_dev *pci_dev;
2999 uint8_t e_device, e_intx;
3000 struct pt_dev *assigned_device = NULL;
3001 uint32_t machine_irq;
3002 uint32_t bdf = 0;
3003 int rc = -1;
3005 if ( php_slot < 0 || php_slot >= PHP_SLOT_LEN )
3006 return -1;
3008 php_dev = &dpci_infos.php_devs[php_slot];
3009 assigned_device = php_dev->pt_dev;
3011 if ( !assigned_device || !php_dev->valid )
3012 return -1;
3014 pci_dev = assigned_device->pci_dev;
3016 /* hide pci dev from qemu */
3017 pci_hide_device((PCIDevice*)assigned_device);
3019 /* Unbind interrupt */
3020 e_device = (assigned_device->dev.devfn >> 3) & 0x1f;
3021 /* fix virtual interrupt pin to INTA# */
3022 e_intx = 0;
3023 machine_irq = pci_dev->irq;
3025 if ( machine_irq != 0 ) {
3026 rc = xc_domain_unbind_pt_irq(xc_handle, domid, machine_irq, PT_IRQ_TYPE_PCI, 0,
3027 e_device, e_intx, 0);
3028 if ( rc < 0 )
3030 /* TBD: unregister device in case of an error */
3031 PT_LOG("Error: Unbinding of interrupt failed! rc=%d\n", rc);
3035 /* delete all emulated config registers */
3036 pt_config_delete(assigned_device);
3038 /* unregister real device's MMIO/PIO BARs */
3039 pt_unregister_regions(assigned_device);
3041 /* deassign the dev to dom0 */
3042 bdf |= (pci_dev->bus & 0xff) << 16;
3043 bdf |= (pci_dev->dev & 0x1f) << 11;
3044 bdf |= (pci_dev->func & 0x1f) << 8;
3045 if ( (rc = xc_deassign_device(xc_handle, domid, bdf)) != 0)
3046 PT_LOG("Error: Revoking the device failed! rc=%d\n", rc);
3048 /* mark this slot as free */
3049 php_dev->valid = 0;
3050 php_dev->pt_dev = NULL;
3051 qemu_free(assigned_device);
3053 return 0;
3056 int power_on_php_slot(int php_slot)
3058 struct php_dev *php_dev = &dpci_infos.php_devs[php_slot];
3059 int pci_slot = php_slot + PHP_SLOT_START;
3060 struct pt_dev *pt_dev;
3061 pt_dev =
3062 register_real_device(dpci_infos.e_bus,
3063 "DIRECT PCI",
3064 pci_slot << 3,
3065 php_dev->r_bus,
3066 php_dev->r_dev,
3067 php_dev->r_func,
3068 PT_MACHINE_IRQ_AUTO,
3069 dpci_infos.pci_access);
3071 php_dev->pt_dev = pt_dev;
3073 return 0;
3077 int power_off_php_slot(int php_slot)
3079 return unregister_real_device(php_slot);
3082 int pt_init(PCIBus *e_bus, char *direct_pci)
3084 int seg, b, d, f, php_slot = 0;
3085 struct pt_dev *pt_dev;
3086 struct pci_access *pci_access;
3087 char *vslots;
3088 char slot_str[8];
3090 /* Initialize libpci */
3091 pci_access = pci_alloc();
3092 if ( pci_access == NULL )
3094 PT_LOG("pci_access is NULL\n");
3095 return -1;
3097 pci_init(pci_access);
3098 pci_scan_bus(pci_access);
3100 memset(&dpci_infos, 0, sizeof(struct dpci_infos));
3101 dpci_infos.pci_access = pci_access;
3102 dpci_infos.e_bus = e_bus;
3104 if ( strlen(direct_pci) == 0 ) {
3105 return 0;
3108 /* the virtual pci slots of all pass-through devs
3109 * with hex format: xx;xx...;
3110 */
3111 vslots = qemu_mallocz ( strlen(direct_pci) / 3 );
3113 /* Assign given devices to guest */
3114 while ( next_bdf(&direct_pci, &seg, &b, &d, &f) )
3116 /* Register real device with the emulated bus */
3117 pt_dev = register_real_device(e_bus, "DIRECT PCI", PT_VIRT_DEVFN_AUTO,
3118 b, d, f, PT_MACHINE_IRQ_AUTO, pci_access);
3119 if ( pt_dev == NULL )
3121 PT_LOG("Error: Registration failed (%02x:%02x.%x)\n", b, d, f);
3122 return -1;
3125 /* Record the virtual slot info */
3126 if ( php_slot < PHP_SLOT_LEN &&
3127 dpci_infos.php_devs[php_slot].pt_dev == pt_dev )
3129 sprintf(slot_str, "0x%x;", PHP_TO_PCI_SLOT(php_slot));
3131 else
3132 sprintf(slot_str, "0x%x;", 0);
3134 strcat(vslots, slot_str);
3135 php_slot++;
3138 /* Write virtual slots info to xenstore for Control panel use */
3139 xenstore_write_vslots(vslots);
3141 qemu_free(vslots);
3143 /* Success */
3144 return 0;