ia64/xen-unstable

view linux-2.6-xen-sparse/include/asm-ia64/io.h @ 9762:a3cc276f2e87

[IA64] dma paravirtualization

Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
author awilliam@localhost
date Tue Apr 25 16:53:27 2006 -0600 (2006-04-25)
parents c160c05da8d4
children d8d2b5c08245
line source
1 #ifndef _ASM_IA64_IO_H
2 #define _ASM_IA64_IO_H
4 /*
5 * This file contains the definitions for the emulated IO instructions
6 * inb/inw/inl/outb/outw/outl and the "string versions" of the same
7 * (insb/insw/insl/outsb/outsw/outsl). You can also use "pausing"
8 * versions of the single-IO instructions (inb_p/inw_p/..).
9 *
10 * This file is not meant to be obfuscating: it's just complicated to
11 * (a) handle it all in a way that makes gcc able to optimize it as
12 * well as possible and (b) trying to avoid writing the same thing
13 * over and over again with slight variations and possibly making a
14 * mistake somewhere.
15 *
16 * Copyright (C) 1998-2003 Hewlett-Packard Co
17 * David Mosberger-Tang <davidm@hpl.hp.com>
18 * Copyright (C) 1999 Asit Mallick <asit.k.mallick@intel.com>
19 * Copyright (C) 1999 Don Dugger <don.dugger@intel.com>
20 */
22 /* We don't use IO slowdowns on the ia64, but.. */
23 #define __SLOW_DOWN_IO do { } while (0)
24 #define SLOW_DOWN_IO do { } while (0)
26 #define __IA64_UNCACHED_OFFSET RGN_BASE(RGN_UNCACHED)
28 /*
29 * The legacy I/O space defined by the ia64 architecture supports only 65536 ports, but
30 * large machines may have multiple other I/O spaces so we can't place any a priori limit
31 * on IO_SPACE_LIMIT. These additional spaces are described in ACPI.
32 */
33 #define IO_SPACE_LIMIT 0xffffffffffffffffUL
35 #define MAX_IO_SPACES_BITS 4
36 #define MAX_IO_SPACES (1UL << MAX_IO_SPACES_BITS)
37 #define IO_SPACE_BITS 24
38 #define IO_SPACE_SIZE (1UL << IO_SPACE_BITS)
40 #define IO_SPACE_NR(port) ((port) >> IO_SPACE_BITS)
41 #define IO_SPACE_BASE(space) ((space) << IO_SPACE_BITS)
42 #define IO_SPACE_PORT(port) ((port) & (IO_SPACE_SIZE - 1))
44 #define IO_SPACE_SPARSE_ENCODING(p) ((((p) >> 2) << 12) | ((p) & 0xfff))
46 struct io_space {
47 unsigned long mmio_base; /* base in MMIO space */
48 int sparse;
49 };
51 extern struct io_space io_space[];
52 extern unsigned int num_io_spaces;
54 # ifdef __KERNEL__
56 /*
57 * All MMIO iomem cookies are in region 6; anything less is a PIO cookie:
58 * 0xCxxxxxxxxxxxxxxx MMIO cookie (return from ioremap)
59 * 0x000000001SPPPPPP PIO cookie (S=space number, P..P=port)
60 *
61 * ioread/writeX() uses the leading 1 in PIO cookies (PIO_OFFSET) to catch
62 * code that uses bare port numbers without the prerequisite pci_iomap().
63 */
64 #define PIO_OFFSET (1UL << (MAX_IO_SPACES_BITS + IO_SPACE_BITS))
65 #define PIO_MASK (PIO_OFFSET - 1)
66 #define PIO_RESERVED __IA64_UNCACHED_OFFSET
67 #define HAVE_ARCH_PIO_SIZE
69 #include <asm/intrinsics.h>
70 #include <asm/machvec.h>
71 #include <asm/page.h>
72 #include <asm/system.h>
73 #include <asm-generic/iomap.h>
74 #ifdef CONFIG_XEN
75 #include <asm/privop.h>
76 #include <asm/hypervisor.h>
77 #endif
79 /*
80 * Change virtual addresses to physical addresses and vv.
81 */
82 static inline unsigned long
83 virt_to_phys (volatile void *address)
84 {
85 return (unsigned long) address - PAGE_OFFSET;
86 }
88 static inline void*
89 phys_to_virt (unsigned long address)
90 {
91 return (void *) (address + PAGE_OFFSET);
92 }
94 #define ARCH_HAS_VALID_PHYS_ADDR_RANGE
95 extern int valid_phys_addr_range (unsigned long addr, size_t *count); /* efi.c */
96 extern int valid_mmap_phys_addr_range (unsigned long addr, size_t *count);
98 /*
99 * The following two macros are deprecated and scheduled for removal.
100 * Please use the PCI-DMA interface defined in <asm/pci.h> instead.
101 */
102 #ifndef CONFIG_XEN_IA64_DOM0_VP
103 #define bus_to_virt phys_to_virt
104 #define virt_to_bus virt_to_phys
105 #define page_to_bus page_to_phys
106 #define page_to_phys(page) (page_to_pfn(page) << PAGE_SHIFT)
107 #define page_to_pseudophys(page) page_to_phys(page)
108 #else
109 #define bus_to_virt(bus) \
110 phys_to_virt(machine_to_phys_for_dma(bus))
111 #define virt_to_bus(virt) \
112 phys_to_machine_for_dma(virt_to_phys(virt))
113 #define page_to_bus(page) \
114 phys_to_machine_for_dma(page_to_pseudophys(page))
116 #define page_to_pseudophys(page) \
117 ((dma_addr_t)page_to_pfn(page) << PAGE_SHIFT)
118 // XXX
119 // the following drivers are broken because they use page_to_phys() to
120 // get bus address. fix them.
121 // drivers/ide/cris/ide-cris.c
122 // drivers/scsi/dec_esp.c
123 #define page_to_phys(page) (page_to_pseudophys(page))
124 #define bvec_to_bus(bv) (page_to_bus((bv)->bv_page) + \
125 (unsigned long) (bv)->bv_offset)
126 #define bio_to_pseudophys(bio) (page_to_pseudophys(bio_page((bio))) + \
127 (unsigned long) bio_offset((bio)))
128 #define bvec_to_pseudophys(bv) (page_to_pseudophys((bv)->bv_page) + \
129 (unsigned long) (bv)->bv_offset)
130 #define BIOVEC_PHYS_MERGEABLE(vec1, vec2) \
131 (((bvec_to_bus((vec1)) + (vec1)->bv_len) == bvec_to_bus((vec2))) && \
132 ((bvec_to_pseudophys((vec1)) + (vec1)->bv_len) == \
133 bvec_to_pseudophys((vec2))))
134 #endif
136 # endif /* KERNEL */
138 /*
139 * Memory fence w/accept. This should never be used in code that is
140 * not IA-64 specific.
141 */
142 #define __ia64_mf_a() ia64_mfa()
144 /**
145 * ___ia64_mmiowb - I/O write barrier
146 *
147 * Ensure ordering of I/O space writes. This will make sure that writes
148 * following the barrier will arrive after all previous writes. For most
149 * ia64 platforms, this is a simple 'mf.a' instruction.
150 *
151 * See Documentation/DocBook/deviceiobook.tmpl for more information.
152 */
153 static inline void ___ia64_mmiowb(void)
154 {
155 ia64_mfa();
156 }
158 static inline void*
159 __ia64_mk_io_addr (unsigned long port)
160 {
161 struct io_space *space;
162 unsigned long offset;
164 space = &io_space[IO_SPACE_NR(port)];
165 port = IO_SPACE_PORT(port);
166 if (space->sparse)
167 offset = IO_SPACE_SPARSE_ENCODING(port);
168 else
169 offset = port;
171 return (void *) (space->mmio_base | offset);
172 }
174 #define __ia64_inb ___ia64_inb
175 #define __ia64_inw ___ia64_inw
176 #define __ia64_inl ___ia64_inl
177 #define __ia64_outb ___ia64_outb
178 #define __ia64_outw ___ia64_outw
179 #define __ia64_outl ___ia64_outl
180 #define __ia64_readb ___ia64_readb
181 #define __ia64_readw ___ia64_readw
182 #define __ia64_readl ___ia64_readl
183 #define __ia64_readq ___ia64_readq
184 #define __ia64_readb_relaxed ___ia64_readb
185 #define __ia64_readw_relaxed ___ia64_readw
186 #define __ia64_readl_relaxed ___ia64_readl
187 #define __ia64_readq_relaxed ___ia64_readq
188 #define __ia64_writeb ___ia64_writeb
189 #define __ia64_writew ___ia64_writew
190 #define __ia64_writel ___ia64_writel
191 #define __ia64_writeq ___ia64_writeq
192 #define __ia64_mmiowb ___ia64_mmiowb
194 /*
195 * For the in/out routines, we need to do "mf.a" _after_ doing the I/O access to ensure
196 * that the access has completed before executing other I/O accesses. Since we're doing
197 * the accesses through an uncachable (UC) translation, the CPU will execute them in
198 * program order. However, we still need to tell the compiler not to shuffle them around
199 * during optimization, which is why we use "volatile" pointers.
200 */
202 static inline unsigned int
203 ___ia64_inb (unsigned long port)
204 {
205 volatile unsigned char *addr = __ia64_mk_io_addr(port);
206 unsigned char ret;
208 ret = *addr;
209 __ia64_mf_a();
210 return ret;
211 }
213 static inline unsigned int
214 ___ia64_inw (unsigned long port)
215 {
216 volatile unsigned short *addr = __ia64_mk_io_addr(port);
217 unsigned short ret;
219 ret = *addr;
220 __ia64_mf_a();
221 return ret;
222 }
224 static inline unsigned int
225 ___ia64_inl (unsigned long port)
226 {
227 volatile unsigned int *addr = __ia64_mk_io_addr(port);
228 unsigned int ret;
230 ret = *addr;
231 __ia64_mf_a();
232 return ret;
233 }
235 static inline void
236 ___ia64_outb (unsigned char val, unsigned long port)
237 {
238 volatile unsigned char *addr = __ia64_mk_io_addr(port);
240 *addr = val;
241 __ia64_mf_a();
242 }
244 static inline void
245 ___ia64_outw (unsigned short val, unsigned long port)
246 {
247 volatile unsigned short *addr = __ia64_mk_io_addr(port);
249 *addr = val;
250 __ia64_mf_a();
251 }
253 static inline void
254 ___ia64_outl (unsigned int val, unsigned long port)
255 {
256 volatile unsigned int *addr = __ia64_mk_io_addr(port);
258 *addr = val;
259 __ia64_mf_a();
260 }
262 static inline void
263 __insb (unsigned long port, void *dst, unsigned long count)
264 {
265 unsigned char *dp = dst;
267 while (count--)
268 *dp++ = platform_inb(port);
269 }
271 static inline void
272 __insw (unsigned long port, void *dst, unsigned long count)
273 {
274 unsigned short *dp = dst;
276 while (count--)
277 *dp++ = platform_inw(port);
278 }
280 static inline void
281 __insl (unsigned long port, void *dst, unsigned long count)
282 {
283 unsigned int *dp = dst;
285 while (count--)
286 *dp++ = platform_inl(port);
287 }
289 static inline void
290 __outsb (unsigned long port, const void *src, unsigned long count)
291 {
292 const unsigned char *sp = src;
294 while (count--)
295 platform_outb(*sp++, port);
296 }
298 static inline void
299 __outsw (unsigned long port, const void *src, unsigned long count)
300 {
301 const unsigned short *sp = src;
303 while (count--)
304 platform_outw(*sp++, port);
305 }
307 static inline void
308 __outsl (unsigned long port, const void *src, unsigned long count)
309 {
310 const unsigned int *sp = src;
312 while (count--)
313 platform_outl(*sp++, port);
314 }
316 /*
317 * Unfortunately, some platforms are broken and do not follow the IA-64 architecture
318 * specification regarding legacy I/O support. Thus, we have to make these operations
319 * platform dependent...
320 */
321 #define __inb platform_inb
322 #define __inw platform_inw
323 #define __inl platform_inl
324 #define __outb platform_outb
325 #define __outw platform_outw
326 #define __outl platform_outl
327 #define __mmiowb platform_mmiowb
329 #define inb(p) __inb(p)
330 #define inw(p) __inw(p)
331 #define inl(p) __inl(p)
332 #define insb(p,d,c) __insb(p,d,c)
333 #define insw(p,d,c) __insw(p,d,c)
334 #define insl(p,d,c) __insl(p,d,c)
335 #define outb(v,p) __outb(v,p)
336 #define outw(v,p) __outw(v,p)
337 #define outl(v,p) __outl(v,p)
338 #define outsb(p,s,c) __outsb(p,s,c)
339 #define outsw(p,s,c) __outsw(p,s,c)
340 #define outsl(p,s,c) __outsl(p,s,c)
341 #define mmiowb() __mmiowb()
343 /*
344 * The address passed to these functions are ioremap()ped already.
345 *
346 * We need these to be machine vectors since some platforms don't provide
347 * DMA coherence via PIO reads (PCI drivers and the spec imply that this is
348 * a good idea). Writes are ok though for all existing ia64 platforms (and
349 * hopefully it'll stay that way).
350 */
351 static inline unsigned char
352 ___ia64_readb (const volatile void __iomem *addr)
353 {
354 return *(volatile unsigned char __force *)addr;
355 }
357 static inline unsigned short
358 ___ia64_readw (const volatile void __iomem *addr)
359 {
360 return *(volatile unsigned short __force *)addr;
361 }
363 static inline unsigned int
364 ___ia64_readl (const volatile void __iomem *addr)
365 {
366 return *(volatile unsigned int __force *) addr;
367 }
369 static inline unsigned long
370 ___ia64_readq (const volatile void __iomem *addr)
371 {
372 return *(volatile unsigned long __force *) addr;
373 }
375 static inline void
376 __writeb (unsigned char val, volatile void __iomem *addr)
377 {
378 *(volatile unsigned char __force *) addr = val;
379 }
381 static inline void
382 __writew (unsigned short val, volatile void __iomem *addr)
383 {
384 *(volatile unsigned short __force *) addr = val;
385 }
387 static inline void
388 __writel (unsigned int val, volatile void __iomem *addr)
389 {
390 *(volatile unsigned int __force *) addr = val;
391 }
393 static inline void
394 __writeq (unsigned long val, volatile void __iomem *addr)
395 {
396 *(volatile unsigned long __force *) addr = val;
397 }
399 #define __readb platform_readb
400 #define __readw platform_readw
401 #define __readl platform_readl
402 #define __readq platform_readq
403 #define __readb_relaxed platform_readb_relaxed
404 #define __readw_relaxed platform_readw_relaxed
405 #define __readl_relaxed platform_readl_relaxed
406 #define __readq_relaxed platform_readq_relaxed
408 #define readb(a) __readb((a))
409 #define readw(a) __readw((a))
410 #define readl(a) __readl((a))
411 #define readq(a) __readq((a))
412 #define readb_relaxed(a) __readb_relaxed((a))
413 #define readw_relaxed(a) __readw_relaxed((a))
414 #define readl_relaxed(a) __readl_relaxed((a))
415 #define readq_relaxed(a) __readq_relaxed((a))
416 #define __raw_readb readb
417 #define __raw_readw readw
418 #define __raw_readl readl
419 #define __raw_readq readq
420 #define __raw_readb_relaxed readb_relaxed
421 #define __raw_readw_relaxed readw_relaxed
422 #define __raw_readl_relaxed readl_relaxed
423 #define __raw_readq_relaxed readq_relaxed
424 #define writeb(v,a) __writeb((v), (a))
425 #define writew(v,a) __writew((v), (a))
426 #define writel(v,a) __writel((v), (a))
427 #define writeq(v,a) __writeq((v), (a))
428 #define __raw_writeb writeb
429 #define __raw_writew writew
430 #define __raw_writel writel
431 #define __raw_writeq writeq
433 #ifndef inb_p
434 # define inb_p inb
435 #endif
436 #ifndef inw_p
437 # define inw_p inw
438 #endif
439 #ifndef inl_p
440 # define inl_p inl
441 #endif
443 #ifndef outb_p
444 # define outb_p outb
445 #endif
446 #ifndef outw_p
447 # define outw_p outw
448 #endif
449 #ifndef outl_p
450 # define outl_p outl
451 #endif
453 /*
454 * An "address" in IO memory space is not clearly either an integer or a pointer. We will
455 * accept both, thus the casts.
456 *
457 * On ia-64, we access the physical I/O memory space through the uncached kernel region.
458 */
459 static inline void __iomem *
460 ioremap (unsigned long offset, unsigned long size)
461 {
462 #ifdef CONFIG_XEN
463 offset = HYPERVISOR_ioremap(offset, size);
464 #endif
465 return (void __iomem *) (__IA64_UNCACHED_OFFSET | (offset));
466 }
468 static inline void
469 iounmap (volatile void __iomem *addr)
470 {
471 }
473 #define ioremap_nocache(o,s) ioremap(o,s)
475 # ifdef __KERNEL__
477 /*
478 * String version of IO memory access ops:
479 */
480 extern void memcpy_fromio(void *dst, const volatile void __iomem *src, long n);
481 extern void memcpy_toio(volatile void __iomem *dst, const void *src, long n);
482 extern void memset_io(volatile void __iomem *s, int c, long n);
484 #define dma_cache_inv(_start,_size) do { } while (0)
485 #define dma_cache_wback(_start,_size) do { } while (0)
486 #define dma_cache_wback_inv(_start,_size) do { } while (0)
488 # endif /* __KERNEL__ */
490 /*
491 * Enabling BIO_VMERGE_BOUNDARY forces us to turn off I/O MMU bypassing. It is said that
492 * BIO-level virtual merging can give up to 4% performance boost (not verified for ia64).
493 * On the other hand, we know that I/O MMU bypassing gives ~8% performance improvement on
494 * SPECweb-like workloads on zx1-based machines. Thus, for now we favor I/O MMU bypassing
495 * over BIO-level virtual merging.
496 */
497 extern unsigned long ia64_max_iommu_merge_mask;
498 #if 1
499 #define BIO_VMERGE_BOUNDARY 0
500 #else
501 /*
502 * It makes no sense at all to have this BIO_VMERGE_BOUNDARY macro here. Should be
503 * replaced by dma_merge_mask() or something of that sort. Note: the only way
504 * BIO_VMERGE_BOUNDARY is used is to mask off bits. Effectively, our definition gets
505 * expanded into:
506 *
507 * addr & ((ia64_max_iommu_merge_mask + 1) - 1) == (addr & ia64_max_iommu_vmerge_mask)
508 *
509 * which is precisely what we want.
510 */
511 #define BIO_VMERGE_BOUNDARY (ia64_max_iommu_merge_mask + 1)
512 #endif
514 #endif /* _ASM_IA64_IO_H */