ia64/xen-unstable

view linux-2.6-xen-sparse/arch/ia64/kernel/setup.c @ 9762:a3cc276f2e87

[IA64] dma paravirtualization

Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
author awilliam@localhost
date Tue Apr 25 16:53:27 2006 -0600 (2006-04-25)
parents 15a04f998083
children b736d3335641
line source
1 /*
2 * Architecture-specific setup.
3 *
4 * Copyright (C) 1998-2001, 2003-2004 Hewlett-Packard Co
5 * David Mosberger-Tang <davidm@hpl.hp.com>
6 * Stephane Eranian <eranian@hpl.hp.com>
7 * Copyright (C) 2000, 2004 Intel Corp
8 * Rohit Seth <rohit.seth@intel.com>
9 * Suresh Siddha <suresh.b.siddha@intel.com>
10 * Gordon Jin <gordon.jin@intel.com>
11 * Copyright (C) 1999 VA Linux Systems
12 * Copyright (C) 1999 Walt Drummond <drummond@valinux.com>
13 *
14 * 12/26/04 S.Siddha, G.Jin, R.Seth
15 * Add multi-threading and multi-core detection
16 * 11/12/01 D.Mosberger Convert get_cpuinfo() to seq_file based show_cpuinfo().
17 * 04/04/00 D.Mosberger renamed cpu_initialized to cpu_online_map
18 * 03/31/00 R.Seth cpu_initialized and current->processor fixes
19 * 02/04/00 D.Mosberger some more get_cpuinfo fixes...
20 * 02/01/00 R.Seth fixed get_cpuinfo for SMP
21 * 01/07/99 S.Eranian added the support for command line argument
22 * 06/24/99 W.Drummond added boot_cpu_data.
23 * 05/28/05 Z. Menyhart Dynamic stride size for "flush_icache_range()"
24 */
25 #include <linux/config.h>
26 #include <linux/module.h>
27 #include <linux/init.h>
29 #include <linux/acpi.h>
30 #include <linux/bootmem.h>
31 #include <linux/console.h>
32 #include <linux/delay.h>
33 #include <linux/kernel.h>
34 #include <linux/reboot.h>
35 #include <linux/sched.h>
36 #include <linux/seq_file.h>
37 #include <linux/string.h>
38 #include <linux/threads.h>
39 #include <linux/tty.h>
40 #include <linux/serial.h>
41 #include <linux/serial_core.h>
42 #include <linux/efi.h>
43 #include <linux/initrd.h>
44 #include <linux/platform.h>
45 #include <linux/pm.h>
46 #include <linux/cpufreq.h>
48 #include <asm/ia32.h>
49 #include <asm/machvec.h>
50 #include <asm/mca.h>
51 #include <asm/meminit.h>
52 #include <asm/page.h>
53 #include <asm/patch.h>
54 #include <asm/pgtable.h>
55 #include <asm/processor.h>
56 #include <asm/sal.h>
57 #include <asm/sections.h>
58 #include <asm/serial.h>
59 #include <asm/setup.h>
60 #include <asm/smp.h>
61 #include <asm/system.h>
62 #include <asm/unistd.h>
63 #include <asm/system.h>
64 #ifdef CONFIG_XEN
65 #include <asm/hypervisor.h>
66 #endif
67 #include <linux/dma-mapping.h>
69 #if defined(CONFIG_SMP) && (IA64_CPU_SIZE > PAGE_SIZE)
70 # error "struct cpuinfo_ia64 too big!"
71 #endif
73 #ifdef CONFIG_SMP
74 unsigned long __per_cpu_offset[NR_CPUS];
75 EXPORT_SYMBOL(__per_cpu_offset);
76 #endif
78 extern void ia64_setup_printk_clock(void);
80 DEFINE_PER_CPU(struct cpuinfo_ia64, cpu_info);
81 DEFINE_PER_CPU(unsigned long, local_per_cpu_offset);
82 DEFINE_PER_CPU(unsigned long, ia64_phys_stacked_size_p8);
83 unsigned long ia64_cycles_per_usec;
84 struct ia64_boot_param *ia64_boot_param;
85 struct screen_info screen_info;
86 unsigned long vga_console_iobase;
87 unsigned long vga_console_membase;
89 static struct resource data_resource = {
90 .name = "Kernel data",
91 .flags = IORESOURCE_BUSY | IORESOURCE_MEM
92 };
94 static struct resource code_resource = {
95 .name = "Kernel code",
96 .flags = IORESOURCE_BUSY | IORESOURCE_MEM
97 };
98 extern void efi_initialize_iomem_resources(struct resource *,
99 struct resource *);
100 extern char _text[], _end[], _etext[];
102 unsigned long ia64_max_cacheline_size;
104 int dma_get_cache_alignment(void)
105 {
106 return ia64_max_cacheline_size;
107 }
108 EXPORT_SYMBOL(dma_get_cache_alignment);
110 unsigned long ia64_iobase; /* virtual address for I/O accesses */
111 EXPORT_SYMBOL(ia64_iobase);
112 struct io_space io_space[MAX_IO_SPACES];
113 EXPORT_SYMBOL(io_space);
114 unsigned int num_io_spaces;
116 /*
117 * "flush_icache_range()" needs to know what processor dependent stride size to use
118 * when it makes i-cache(s) coherent with d-caches.
119 */
120 #define I_CACHE_STRIDE_SHIFT 5 /* Safest way to go: 32 bytes by 32 bytes */
121 unsigned long ia64_i_cache_stride_shift = ~0;
123 /*
124 * The merge_mask variable needs to be set to (max(iommu_page_size(iommu)) - 1). This
125 * mask specifies a mask of address bits that must be 0 in order for two buffers to be
126 * mergeable by the I/O MMU (i.e., the end address of the first buffer and the start
127 * address of the second buffer must be aligned to (merge_mask+1) in order to be
128 * mergeable). By default, we assume there is no I/O MMU which can merge physically
129 * discontiguous buffers, so we set the merge_mask to ~0UL, which corresponds to a iommu
130 * page-size of 2^64.
131 */
132 unsigned long ia64_max_iommu_merge_mask = ~0UL;
133 EXPORT_SYMBOL(ia64_max_iommu_merge_mask);
135 /*
136 * We use a special marker for the end of memory and it uses the extra (+1) slot
137 */
138 struct rsvd_region rsvd_region[IA64_MAX_RSVD_REGIONS + 1];
139 int num_rsvd_regions;
142 /*
143 * Filter incoming memory segments based on the primitive map created from the boot
144 * parameters. Segments contained in the map are removed from the memory ranges. A
145 * caller-specified function is called with the memory ranges that remain after filtering.
146 * This routine does not assume the incoming segments are sorted.
147 */
148 int
149 filter_rsvd_memory (unsigned long start, unsigned long end, void *arg)
150 {
151 unsigned long range_start, range_end, prev_start;
152 void (*func)(unsigned long, unsigned long, int);
153 int i;
155 #if IGNORE_PFN0
156 if (start == PAGE_OFFSET) {
157 printk(KERN_WARNING "warning: skipping physical page 0\n");
158 start += PAGE_SIZE;
159 if (start >= end) return 0;
160 }
161 #endif
162 /*
163 * lowest possible address(walker uses virtual)
164 */
165 prev_start = PAGE_OFFSET;
166 func = arg;
168 for (i = 0; i < num_rsvd_regions; ++i) {
169 range_start = max(start, prev_start);
170 range_end = min(end, rsvd_region[i].start);
172 if (range_start < range_end)
173 call_pernode_memory(__pa(range_start), range_end - range_start, func);
175 /* nothing more available in this segment */
176 if (range_end == end) return 0;
178 prev_start = rsvd_region[i].end;
179 }
180 /* end of memory marker allows full processing inside loop body */
181 return 0;
182 }
184 static void
185 sort_regions (struct rsvd_region *rsvd_region, int max)
186 {
187 int j;
189 /* simple bubble sorting */
190 while (max--) {
191 for (j = 0; j < max; ++j) {
192 if (rsvd_region[j].start > rsvd_region[j+1].start) {
193 struct rsvd_region tmp;
194 tmp = rsvd_region[j];
195 rsvd_region[j] = rsvd_region[j + 1];
196 rsvd_region[j + 1] = tmp;
197 }
198 }
199 }
200 }
202 /*
203 * Request address space for all standard resources
204 */
205 static int __init register_memory(void)
206 {
207 code_resource.start = ia64_tpa(_text);
208 code_resource.end = ia64_tpa(_etext) - 1;
209 data_resource.start = ia64_tpa(_etext);
210 data_resource.end = ia64_tpa(_end) - 1;
211 efi_initialize_iomem_resources(&code_resource, &data_resource);
213 return 0;
214 }
216 __initcall(register_memory);
218 /**
219 * reserve_memory - setup reserved memory areas
220 *
221 * Setup the reserved memory areas set aside for the boot parameters,
222 * initrd, etc. There are currently %IA64_MAX_RSVD_REGIONS defined,
223 * see include/asm-ia64/meminit.h if you need to define more.
224 */
225 void
226 reserve_memory (void)
227 {
228 int n = 0;
230 /*
231 * none of the entries in this table overlap
232 */
233 rsvd_region[n].start = (unsigned long) ia64_boot_param;
234 rsvd_region[n].end = rsvd_region[n].start + sizeof(*ia64_boot_param);
235 n++;
237 rsvd_region[n].start = (unsigned long) __va(ia64_boot_param->efi_memmap);
238 rsvd_region[n].end = rsvd_region[n].start + ia64_boot_param->efi_memmap_size;
239 n++;
241 rsvd_region[n].start = (unsigned long) __va(ia64_boot_param->command_line);
242 rsvd_region[n].end = (rsvd_region[n].start
243 + strlen(__va(ia64_boot_param->command_line)) + 1);
244 n++;
246 rsvd_region[n].start = (unsigned long) ia64_imva((void *)KERNEL_START);
247 rsvd_region[n].end = (unsigned long) ia64_imva(_end);
248 n++;
250 #ifdef CONFIG_XEN
251 if (running_on_xen) {
252 rsvd_region[n].start = (unsigned long)__va((HYPERVISOR_shared_info->arch.start_info_pfn << PAGE_SHIFT));
253 rsvd_region[n].end = rsvd_region[n].start + PAGE_SIZE;
254 n++;
255 }
256 #endif
258 #ifdef CONFIG_BLK_DEV_INITRD
259 if (ia64_boot_param->initrd_start) {
260 rsvd_region[n].start = (unsigned long)__va(ia64_boot_param->initrd_start);
261 rsvd_region[n].end = rsvd_region[n].start + ia64_boot_param->initrd_size;
262 n++;
263 }
264 #endif
266 efi_memmap_init(&rsvd_region[n].start, &rsvd_region[n].end);
267 n++;
269 /* end of memory marker */
270 rsvd_region[n].start = ~0UL;
271 rsvd_region[n].end = ~0UL;
272 n++;
274 num_rsvd_regions = n;
275 BUG_ON(IA64_MAX_RSVD_REGIONS + 1 < n);
277 sort_regions(rsvd_region, num_rsvd_regions);
278 }
280 /**
281 * find_initrd - get initrd parameters from the boot parameter structure
282 *
283 * Grab the initrd start and end from the boot parameter struct given us by
284 * the boot loader.
285 */
286 void
287 find_initrd (void)
288 {
289 #ifdef CONFIG_BLK_DEV_INITRD
290 if (ia64_boot_param->initrd_start) {
291 initrd_start = (unsigned long)__va(ia64_boot_param->initrd_start);
292 initrd_end = initrd_start+ia64_boot_param->initrd_size;
294 printk(KERN_INFO "Initial ramdisk at: 0x%lx (%lu bytes)\n",
295 initrd_start, ia64_boot_param->initrd_size);
296 }
297 #endif
298 }
300 static void __init
301 io_port_init (void)
302 {
303 unsigned long phys_iobase;
305 /*
306 * Set `iobase' based on the EFI memory map or, failing that, the
307 * value firmware left in ar.k0.
308 *
309 * Note that in ia32 mode, IN/OUT instructions use ar.k0 to compute
310 * the port's virtual address, so ia32_load_state() loads it with a
311 * user virtual address. But in ia64 mode, glibc uses the
312 * *physical* address in ar.k0 to mmap the appropriate area from
313 * /dev/mem, and the inX()/outX() interfaces use MMIO. In both
314 * cases, user-mode can only use the legacy 0-64K I/O port space.
315 *
316 * ar.k0 is not involved in kernel I/O port accesses, which can use
317 * any of the I/O port spaces and are done via MMIO using the
318 * virtual mmio_base from the appropriate io_space[].
319 */
320 phys_iobase = efi_get_iobase();
321 if (!phys_iobase) {
322 phys_iobase = ia64_get_kr(IA64_KR_IO_BASE);
323 printk(KERN_INFO "No I/O port range found in EFI memory map, "
324 "falling back to AR.KR0 (0x%lx)\n", phys_iobase);
325 }
326 ia64_iobase = (unsigned long) ioremap(phys_iobase, 0);
327 ia64_set_kr(IA64_KR_IO_BASE, __pa(ia64_iobase));
329 /* setup legacy IO port space */
330 io_space[0].mmio_base = ia64_iobase;
331 io_space[0].sparse = 1;
332 num_io_spaces = 1;
333 }
335 /**
336 * early_console_setup - setup debugging console
337 *
338 * Consoles started here require little enough setup that we can start using
339 * them very early in the boot process, either right after the machine
340 * vector initialization, or even before if the drivers can detect their hw.
341 *
342 * Returns non-zero if a console couldn't be setup.
343 */
344 static inline int __init
345 early_console_setup (char *cmdline)
346 {
347 int earlycons = 0;
349 #ifdef CONFIG_XEN
350 if (!early_xen_console_setup(cmdline))
351 earlycons++;
352 #endif
353 #ifdef CONFIG_SERIAL_SGI_L1_CONSOLE
354 {
355 extern int sn_serial_console_early_setup(void);
356 if (!sn_serial_console_early_setup())
357 earlycons++;
358 }
359 #endif
360 #ifdef CONFIG_EFI_PCDP
361 if (!efi_setup_pcdp_console(cmdline))
362 earlycons++;
363 #endif
364 #ifdef CONFIG_SERIAL_8250_CONSOLE
365 if (!early_serial_console_init(cmdline))
366 earlycons++;
367 #endif
369 return (earlycons) ? 0 : -1;
370 }
372 static inline void
373 mark_bsp_online (void)
374 {
375 #ifdef CONFIG_SMP
376 /* If we register an early console, allow CPU 0 to printk */
377 cpu_set(smp_processor_id(), cpu_online_map);
378 #endif
379 }
381 #ifdef CONFIG_SMP
382 static void
383 check_for_logical_procs (void)
384 {
385 pal_logical_to_physical_t info;
386 s64 status;
388 status = ia64_pal_logical_to_phys(0, &info);
389 if (status == -1) {
390 printk(KERN_INFO "No logical to physical processor mapping "
391 "available\n");
392 return;
393 }
394 if (status) {
395 printk(KERN_ERR "ia64_pal_logical_to_phys failed with %ld\n",
396 status);
397 return;
398 }
399 /*
400 * Total number of siblings that BSP has. Though not all of them
401 * may have booted successfully. The correct number of siblings
402 * booted is in info.overview_num_log.
403 */
404 smp_num_siblings = info.overview_tpc;
405 smp_num_cpucores = info.overview_cpp;
406 }
407 #endif
409 void __init
410 setup_arch (char **cmdline_p)
411 {
412 unw_init();
413 #ifdef CONFIG_XEN
414 if (running_on_xen)
415 setup_xen_features();
416 #endif
418 ia64_patch_vtop((u64) __start___vtop_patchlist, (u64) __end___vtop_patchlist);
420 *cmdline_p = __va(ia64_boot_param->command_line);
421 strlcpy(saved_command_line, *cmdline_p, COMMAND_LINE_SIZE);
423 efi_init();
424 io_port_init();
426 #ifdef CONFIG_IA64_GENERIC
427 {
428 const char *mvec_name = strstr (*cmdline_p, "machvec=");
429 char str[64];
431 if (mvec_name) {
432 const char *end;
433 size_t len;
435 mvec_name += 8;
436 end = strchr (mvec_name, ' ');
437 if (end)
438 len = end - mvec_name;
439 else
440 len = strlen (mvec_name);
441 len = min(len, sizeof (str) - 1);
442 strncpy (str, mvec_name, len);
443 str[len] = '\0';
444 mvec_name = str;
445 } else
446 mvec_name = acpi_get_sysname();
447 machvec_init(mvec_name);
448 }
449 #endif
451 if (early_console_setup(*cmdline_p) == 0)
452 mark_bsp_online();
454 parse_early_param();
455 #ifdef CONFIG_ACPI
456 /* Initialize the ACPI boot-time table parser */
457 acpi_table_init();
458 # ifdef CONFIG_ACPI_NUMA
459 acpi_numa_init();
460 # endif
461 #else
462 # ifdef CONFIG_SMP
463 smp_build_cpu_map(); /* happens, e.g., with the Ski simulator */
464 # endif
465 #endif /* CONFIG_APCI_BOOT */
467 find_memory();
469 /* process SAL system table: */
470 ia64_sal_init(efi.sal_systab);
472 ia64_setup_printk_clock();
474 #ifdef CONFIG_SMP
475 cpu_physical_id(0) = hard_smp_processor_id();
477 cpu_set(0, cpu_sibling_map[0]);
478 cpu_set(0, cpu_core_map[0]);
480 check_for_logical_procs();
481 if (smp_num_cpucores > 1)
482 printk(KERN_INFO
483 "cpu package is Multi-Core capable: number of cores=%d\n",
484 smp_num_cpucores);
485 if (smp_num_siblings > 1)
486 printk(KERN_INFO
487 "cpu package is Multi-Threading capable: number of siblings=%d\n",
488 smp_num_siblings);
489 #endif
491 cpu_init(); /* initialize the bootstrap CPU */
492 mmu_context_init(); /* initialize context_id bitmap */
494 #ifdef CONFIG_ACPI
495 acpi_boot_init();
496 #endif
498 #ifdef CONFIG_VT
499 if (!conswitchp) {
500 # if defined(CONFIG_DUMMY_CONSOLE)
501 conswitchp = &dummy_con;
502 # endif
503 # if defined(CONFIG_VGA_CONSOLE)
504 /*
505 * Non-legacy systems may route legacy VGA MMIO range to system
506 * memory. vga_con probes the MMIO hole, so memory looks like
507 * a VGA device to it. The EFI memory map can tell us if it's
508 * memory so we can avoid this problem.
509 */
510 if (efi_mem_type(0xA0000) != EFI_CONVENTIONAL_MEMORY)
511 conswitchp = &vga_con;
512 # endif
513 }
514 #ifdef CONFIG_XEN
515 if (running_on_xen) {
516 extern shared_info_t *HYPERVISOR_shared_info;
518 /* xen_start_info isn't setup yet, get the flags manually */
519 if (HYPERVISOR_shared_info->arch.flags & SIF_INITDOMAIN) {
520 if (!(HYPERVISOR_shared_info->arch.flags & SIF_PRIVILEGED))
521 panic("Xen granted us console access "
522 "but not privileged status");
523 } else {
524 extern int console_use_vt;
525 conswitchp = NULL;
526 console_use_vt = 0;
527 }
528 }
529 #endif
530 #endif
532 /* enable IA-64 Machine Check Abort Handling unless disabled */
533 if (!strstr(saved_command_line, "nomca"))
534 ia64_mca_init();
536 platform_setup(cmdline_p);
537 paging_init();
538 contiguous_bitmap_init(max_pfn);
539 }
541 /*
542 * Display cpu info for all cpu's.
543 */
544 static int
545 show_cpuinfo (struct seq_file *m, void *v)
546 {
547 #ifdef CONFIG_SMP
548 # define lpj c->loops_per_jiffy
549 # define cpunum c->cpu
550 #else
551 # define lpj loops_per_jiffy
552 # define cpunum 0
553 #endif
554 static struct {
555 unsigned long mask;
556 const char *feature_name;
557 } feature_bits[] = {
558 { 1UL << 0, "branchlong" },
559 { 1UL << 1, "spontaneous deferral"},
560 { 1UL << 2, "16-byte atomic ops" }
561 };
562 char family[32], features[128], *cp, sep;
563 struct cpuinfo_ia64 *c = v;
564 unsigned long mask;
565 unsigned long proc_freq;
566 int i;
568 mask = c->features;
570 switch (c->family) {
571 case 0x07: memcpy(family, "Itanium", 8); break;
572 case 0x1f: memcpy(family, "Itanium 2", 10); break;
573 default: sprintf(family, "%u", c->family); break;
574 }
576 /* build the feature string: */
577 memcpy(features, " standard", 10);
578 cp = features;
579 sep = 0;
580 for (i = 0; i < (int) ARRAY_SIZE(feature_bits); ++i) {
581 if (mask & feature_bits[i].mask) {
582 if (sep)
583 *cp++ = sep;
584 sep = ',';
585 *cp++ = ' ';
586 strcpy(cp, feature_bits[i].feature_name);
587 cp += strlen(feature_bits[i].feature_name);
588 mask &= ~feature_bits[i].mask;
589 }
590 }
591 if (mask) {
592 /* print unknown features as a hex value: */
593 if (sep)
594 *cp++ = sep;
595 sprintf(cp, " 0x%lx", mask);
596 }
598 proc_freq = cpufreq_quick_get(cpunum);
599 if (!proc_freq)
600 proc_freq = c->proc_freq / 1000;
602 seq_printf(m,
603 "processor : %d\n"
604 "vendor : %s\n"
605 "arch : IA-64\n"
606 "family : %s\n"
607 "model : %u\n"
608 "revision : %u\n"
609 "archrev : %u\n"
610 "features :%s\n" /* don't change this---it _is_ right! */
611 "cpu number : %lu\n"
612 "cpu regs : %u\n"
613 "cpu MHz : %lu.%06lu\n"
614 "itc MHz : %lu.%06lu\n"
615 "BogoMIPS : %lu.%02lu\n",
616 cpunum, c->vendor, family, c->model, c->revision, c->archrev,
617 features, c->ppn, c->number,
618 proc_freq / 1000, proc_freq % 1000,
619 c->itc_freq / 1000000, c->itc_freq % 1000000,
620 lpj*HZ/500000, (lpj*HZ/5000) % 100);
621 #ifdef CONFIG_SMP
622 seq_printf(m, "siblings : %u\n", cpus_weight(cpu_core_map[cpunum]));
623 if (c->threads_per_core > 1 || c->cores_per_socket > 1)
624 seq_printf(m,
625 "physical id: %u\n"
626 "core id : %u\n"
627 "thread id : %u\n",
628 c->socket_id, c->core_id, c->thread_id);
629 #endif
630 seq_printf(m,"\n");
632 return 0;
633 }
635 static void *
636 c_start (struct seq_file *m, loff_t *pos)
637 {
638 #ifdef CONFIG_SMP
639 while (*pos < NR_CPUS && !cpu_isset(*pos, cpu_online_map))
640 ++*pos;
641 #endif
642 return *pos < NR_CPUS ? cpu_data(*pos) : NULL;
643 }
645 static void *
646 c_next (struct seq_file *m, void *v, loff_t *pos)
647 {
648 ++*pos;
649 return c_start(m, pos);
650 }
652 static void
653 c_stop (struct seq_file *m, void *v)
654 {
655 }
657 struct seq_operations cpuinfo_op = {
658 .start = c_start,
659 .next = c_next,
660 .stop = c_stop,
661 .show = show_cpuinfo
662 };
664 void
665 identify_cpu (struct cpuinfo_ia64 *c)
666 {
667 union {
668 unsigned long bits[5];
669 struct {
670 /* id 0 & 1: */
671 char vendor[16];
673 /* id 2 */
674 u64 ppn; /* processor serial number */
676 /* id 3: */
677 unsigned number : 8;
678 unsigned revision : 8;
679 unsigned model : 8;
680 unsigned family : 8;
681 unsigned archrev : 8;
682 unsigned reserved : 24;
684 /* id 4: */
685 u64 features;
686 } field;
687 } cpuid;
688 pal_vm_info_1_u_t vm1;
689 pal_vm_info_2_u_t vm2;
690 pal_status_t status;
691 unsigned long impl_va_msb = 50, phys_addr_size = 44; /* Itanium defaults */
692 int i;
694 for (i = 0; i < 5; ++i)
695 cpuid.bits[i] = ia64_get_cpuid(i);
697 memcpy(c->vendor, cpuid.field.vendor, 16);
698 #ifdef CONFIG_SMP
699 c->cpu = smp_processor_id();
701 /* below default values will be overwritten by identify_siblings()
702 * for Multi-Threading/Multi-Core capable cpu's
703 */
704 c->threads_per_core = c->cores_per_socket = c->num_log = 1;
705 c->socket_id = -1;
707 identify_siblings(c);
708 #endif
709 c->ppn = cpuid.field.ppn;
710 c->number = cpuid.field.number;
711 c->revision = cpuid.field.revision;
712 c->model = cpuid.field.model;
713 c->family = cpuid.field.family;
714 c->archrev = cpuid.field.archrev;
715 c->features = cpuid.field.features;
717 status = ia64_pal_vm_summary(&vm1, &vm2);
718 if (status == PAL_STATUS_SUCCESS) {
719 impl_va_msb = vm2.pal_vm_info_2_s.impl_va_msb;
720 phys_addr_size = vm1.pal_vm_info_1_s.phys_add_size;
721 }
722 c->unimpl_va_mask = ~((7L<<61) | ((1L << (impl_va_msb + 1)) - 1));
723 c->unimpl_pa_mask = ~((1L<<63) | ((1L << phys_addr_size) - 1));
724 }
726 void
727 setup_per_cpu_areas (void)
728 {
729 /* start_kernel() requires this... */
730 #ifdef CONFIG_ACPI_HOTPLUG_CPU
731 prefill_possible_map();
732 #endif
733 }
735 /*
736 * Calculate the max. cache line size.
737 *
738 * In addition, the minimum of the i-cache stride sizes is calculated for
739 * "flush_icache_range()".
740 */
741 static void
742 get_max_cacheline_size (void)
743 {
744 unsigned long line_size, max = 1;
745 unsigned int cache_size = 0;
746 u64 l, levels, unique_caches;
747 pal_cache_config_info_t cci;
748 s64 status;
750 status = ia64_pal_cache_summary(&levels, &unique_caches);
751 if (status != 0) {
752 printk(KERN_ERR "%s: ia64_pal_cache_summary() failed (status=%ld)\n",
753 __FUNCTION__, status);
754 max = SMP_CACHE_BYTES;
755 /* Safest setup for "flush_icache_range()" */
756 ia64_i_cache_stride_shift = I_CACHE_STRIDE_SHIFT;
757 goto out;
758 }
760 for (l = 0; l < levels; ++l) {
761 status = ia64_pal_cache_config_info(l, /* cache_type (data_or_unified)= */ 2,
762 &cci);
763 if (status != 0) {
764 printk(KERN_ERR
765 "%s: ia64_pal_cache_config_info(l=%lu, 2) failed (status=%ld)\n",
766 __FUNCTION__, l, status);
767 max = SMP_CACHE_BYTES;
768 /* The safest setup for "flush_icache_range()" */
769 cci.pcci_stride = I_CACHE_STRIDE_SHIFT;
770 cci.pcci_unified = 1;
771 }
772 line_size = 1 << cci.pcci_line_size;
773 if (line_size > max)
774 max = line_size;
775 if (cache_size < cci.pcci_cache_size)
776 cache_size = cci.pcci_cache_size;
777 if (!cci.pcci_unified) {
778 status = ia64_pal_cache_config_info(l,
779 /* cache_type (instruction)= */ 1,
780 &cci);
781 if (status != 0) {
782 printk(KERN_ERR
783 "%s: ia64_pal_cache_config_info(l=%lu, 1) failed (status=%ld)\n",
784 __FUNCTION__, l, status);
785 /* The safest setup for "flush_icache_range()" */
786 cci.pcci_stride = I_CACHE_STRIDE_SHIFT;
787 }
788 }
789 if (cci.pcci_stride < ia64_i_cache_stride_shift)
790 ia64_i_cache_stride_shift = cci.pcci_stride;
791 }
792 out:
793 #ifdef CONFIG_SMP
794 max_cache_size = max(max_cache_size, cache_size);
795 #endif
796 if (max > ia64_max_cacheline_size)
797 ia64_max_cacheline_size = max;
798 }
800 /*
801 * cpu_init() initializes state that is per-CPU. This function acts
802 * as a 'CPU state barrier', nothing should get across.
803 */
804 void
805 cpu_init (void)
806 {
807 extern void __devinit ia64_mmu_init (void *);
808 unsigned long num_phys_stacked;
809 pal_vm_info_2_u_t vmi;
810 unsigned int max_ctx;
811 struct cpuinfo_ia64 *cpu_info;
812 void *cpu_data;
814 cpu_data = per_cpu_init();
816 /*
817 * We set ar.k3 so that assembly code in MCA handler can compute
818 * physical addresses of per cpu variables with a simple:
819 * phys = ar.k3 + &per_cpu_var
820 */
821 ia64_set_kr(IA64_KR_PER_CPU_DATA,
822 ia64_tpa(cpu_data) - (long) __per_cpu_start);
824 get_max_cacheline_size();
826 /*
827 * We can't pass "local_cpu_data" to identify_cpu() because we haven't called
828 * ia64_mmu_init() yet. And we can't call ia64_mmu_init() first because it
829 * depends on the data returned by identify_cpu(). We break the dependency by
830 * accessing cpu_data() through the canonical per-CPU address.
831 */
832 cpu_info = cpu_data + ((char *) &__ia64_per_cpu_var(cpu_info) - __per_cpu_start);
833 identify_cpu(cpu_info);
835 #ifdef CONFIG_MCKINLEY
836 {
837 # define FEATURE_SET 16
838 struct ia64_pal_retval iprv;
840 if (cpu_info->family == 0x1f) {
841 PAL_CALL_PHYS(iprv, PAL_PROC_GET_FEATURES, 0, FEATURE_SET, 0);
842 if ((iprv.status == 0) && (iprv.v0 & 0x80) && (iprv.v2 & 0x80))
843 PAL_CALL_PHYS(iprv, PAL_PROC_SET_FEATURES,
844 (iprv.v1 | 0x80), FEATURE_SET, 0);
845 }
846 }
847 #endif
849 /* Clear the stack memory reserved for pt_regs: */
850 memset(task_pt_regs(current), 0, sizeof(struct pt_regs));
852 ia64_set_kr(IA64_KR_FPU_OWNER, 0);
854 /*
855 * Initialize the page-table base register to a global
856 * directory with all zeroes. This ensure that we can handle
857 * TLB-misses to user address-space even before we created the
858 * first user address-space. This may happen, e.g., due to
859 * aggressive use of lfetch.fault.
860 */
861 ia64_set_kr(IA64_KR_PT_BASE, __pa(ia64_imva(empty_zero_page)));
863 /*
864 * Initialize default control register to defer speculative faults except
865 * for those arising from TLB misses, which are not deferred. The
866 * kernel MUST NOT depend on a particular setting of these bits (in other words,
867 * the kernel must have recovery code for all speculative accesses). Turn on
868 * dcr.lc as per recommendation by the architecture team. Most IA-32 apps
869 * shouldn't be affected by this (moral: keep your ia32 locks aligned and you'll
870 * be fine).
871 */
872 ia64_setreg(_IA64_REG_CR_DCR, ( IA64_DCR_DP | IA64_DCR_DK | IA64_DCR_DX | IA64_DCR_DR
873 | IA64_DCR_DA | IA64_DCR_DD | IA64_DCR_LC));
874 atomic_inc(&init_mm.mm_count);
875 current->active_mm = &init_mm;
876 if (current->mm)
877 BUG();
879 ia64_mmu_init(ia64_imva(cpu_data));
880 ia64_mca_cpu_init(ia64_imva(cpu_data));
882 #ifdef CONFIG_IA32_SUPPORT
883 ia32_cpu_init();
884 #endif
886 /* Clear ITC to eliminiate sched_clock() overflows in human time. */
887 ia64_set_itc(0);
889 /* disable all local interrupt sources: */
890 ia64_set_itv(1 << 16);
891 ia64_set_lrr0(1 << 16);
892 ia64_set_lrr1(1 << 16);
893 ia64_setreg(_IA64_REG_CR_PMV, 1 << 16);
894 ia64_setreg(_IA64_REG_CR_CMCV, 1 << 16);
896 /* clear TPR & XTP to enable all interrupt classes: */
897 ia64_setreg(_IA64_REG_CR_TPR, 0);
898 #ifdef CONFIG_SMP
899 normal_xtp();
900 #endif
902 /* set ia64_ctx.max_rid to the maximum RID that is supported by all CPUs: */
903 if (ia64_pal_vm_summary(NULL, &vmi) == 0)
904 max_ctx = (1U << (vmi.pal_vm_info_2_s.rid_size - 3)) - 1;
905 else {
906 printk(KERN_WARNING "cpu_init: PAL VM summary failed, assuming 18 RID bits\n");
907 max_ctx = (1U << 15) - 1; /* use architected minimum */
908 }
909 while (max_ctx < ia64_ctx.max_ctx) {
910 unsigned int old = ia64_ctx.max_ctx;
911 if (cmpxchg(&ia64_ctx.max_ctx, old, max_ctx) == old)
912 break;
913 }
915 if (ia64_pal_rse_info(&num_phys_stacked, NULL) != 0) {
916 printk(KERN_WARNING "cpu_init: PAL RSE info failed; assuming 96 physical "
917 "stacked regs\n");
918 num_phys_stacked = 96;
919 }
920 /* size of physical stacked register partition plus 8 bytes: */
921 __get_cpu_var(ia64_phys_stacked_size_p8) = num_phys_stacked*8 + 8;
922 platform_cpu_init();
923 pm_idle = default_idle;
924 }
926 /*
927 * On SMP systems, when the scheduler does migration-cost autodetection,
928 * it needs a way to flush as much of the CPU's caches as possible.
929 */
930 void sched_cacheflush(void)
931 {
932 ia64_sal_cache_flush(3);
933 }
935 void
936 check_bugs (void)
937 {
938 ia64_patch_mckinley_e9((unsigned long) __start___mckinley_e9_bundles,
939 (unsigned long) __end___mckinley_e9_bundles);
940 }